Rainbow Electronics MAX1197 User Manual

Page 1

General Description

The MAX1197 is a 3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1197 is optimized for low-power, small size, and high-dynamic performance for applications in imaging, instrumentation and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 120mW while delivering a typical signal-to-noise and distortion (SINAD) of 48.5dB at an input frequency of 30MHz and a sampling rate of 60Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1197 features a 3mA sleep mode as well as a

0.1µA power-down mode to conserve power during idle periods.

An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range.

The MAX1197 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1197 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.

Pin-compatible lower and higher speed versions of the MAX1197 are also available. Refer to the MAX1195 data sheet for 40Msps and the MAX1198 data sheet for 100Msps. In addition to these speed grades, this family will include a multiplexed output version (MAX1196, 40Msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port.

For a 10-bit, pin-compatible upgrade, refer to the MAX1182 data sheet. With the N.C. pins of the MAX1197 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1182.

Applications

Features

♦ Single 2.7V to 3.6V Operation

♦ Excellent Dynamic Performance

48.5dB/45.3dB SINAD at f

= 30MHz/200MHz

69dBc/53.5dBc SFDR at fIN= 30MHz/200MHz

♦ -72dB Interchannel Crosstalk at fIN= 20MHz

♦ Low Power

120mW (Normal Operation) 9mW (Sleep Mode)

0.3µW (Shutdown Mode)

♦ 0.05dB Gain and ±0.05° Phase Matching ♦ Wide ±1V

P-P

Differential Analog Input Voltage

Range

♦ 400MHz -3dB Input Bandwidth

♦ On-Chip 2.048V Precision Bandgap Reference

♦ User-Selectable Output Format—Two’s

Complement or Offset Binary

♦ Pin-Compatible 8-Bit and 10-Bit Upgrades

Available

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-2411; Rev 0; 4/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Functional Diagram and Pin Compatible Upgrades table appear at end of data sheet.

*EP = Exposed paddle

Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical

Imaging Battery-Powered

Instrumentation

WLAN, WWAN, WLL, MMDS Modems

Set-Top Boxes VSAT Terminals

PART TEMP RANGE PIN-PACKAGE

MAX1197ECM -40°C to +85°C 48 TQFP-EP*

REFN

REFP

REFIN

REFOUT

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

COM

V GND INA+ INA-

V GND INBINB+ GND

CLK

4847464544434241403938

1314151617181920212223

GND

MAX1197

GND

TQFP-EP

T/B

SLEEP

D7B

D6B

D5B

D4B

N.C. N.C.

OGND

N.C.

D0B

D1B

D2B

D3B

Page 2

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 60MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND ...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

REFIN, REFOUT, REFP, REFN,

COM, CLK to GND .................................-0.3V to (V

+ 0.3V)

OE, PD, SLEEP, T/B, D7A–D0A,

D7B–D0B to OGND .............................-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution 8 Bits

Integral Nonlinearity INL fIN = 7.5MHz (Note 1) ±0.3 ±1 LSB

Differential Nonlinearity DNL

Offset Error ±4%FS Gain Error ±4%FS Gain Temperature Coefficient ±100 ppm/°C

ANALOG INPUT

Differential Input Voltage Range V

Common-Mode Input Voltage Range

Input Resistance R

Input Capacitance C

CONVERSION RATE

Maximum Clock Frequency f

Data Latency 5

DYNAMIC CHARACTERISTICS (f

Signal-to-Noise Ratio SNR

PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS

= 7.5MHz, no missing codes guaranteed

(Note 1)

DIFF

CLK

= 60MHz, 4096-point FFT)

CLK

Differential or single-ended inputs ±1.0 V

Switched capacitor load 95 kΩ

= 7.5MHz at -1dB FS 48.7

INA or B

= 20MHz at -1dB FS 47 48.7

INA or B

= 30MHz at -1dB FS 48.6

INA or B

= 115.1MHz at -1dB FS 48.3

INA or B

±0.2 ±1 LSB

D D

±0.2

60 MHz

/ 2

5pF

Clock

Cycles

Page 3

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 60MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Signal-to-Noise and Distortion

Spurious-Free Dynamic Range

Third-Harmonic Distortion

Intermodulation Distortion (First Five Odd-Order IMDs)

Third-Order Intermodulation Distortion

Total Harmonic Distortion (First Four Harmonics)

Small-Signal Bandwidth Input at -20dB FS, differential inputs 500 MHz

Full-Power Bandwidth FPBW Input at -1dB FS, differential inputs 400 MHz

Gain Flatness (12MHz Spacing)

Aperture Delay t

Aperture Jitter t Overdrive Recovery Time For 1.5 × full-scale input 2 ns IN T ER N A L REF ER EN C E ( RE FIN = RE FOU T thr oug h 10kΩ r esi stor ; RE FP , RE FN , and C OM l evel s ar e g ener ated i nter nal l y.)

Reference Output Voltage V

Positive Reference Output Voltage

Negative Reference Output Voltage

Common-Mode Level V

PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS

= 7.5MHz at -1dB FS 48.6

INA or B

= 20MHz at -1dB FS 46.5 48.6

SINAD

SFDR

HD3

IMD

INA or B

= 30MHz at -1dB FS 48.5

INA or B

= 115.1MHz at -1dB FS 48.2

INA or B

= 7.5MHz at -1dB FS 71

INA or B

= 20MHz at -1dB FS 60 69

INA or B

= 30MHz at -1dB FS 69

INA or B

= 115.1MHz at -1dB FS 68

INA or B

= 7.5MHz at -1dB FS - 75

INA or B

= 20MHz at -1dB FS - 72

INA or B

= 30MHz at -1dB FS - 72

INA or B

= 115.1MHz at -1dB FS - 68

INA or B

IN1(A or B)

IN2(A or B)

= 1.985MHz at -7dB FS = 2.029MHz at -7dB FS

- 70 dBc

dBc

(Note 2)

IM3

IN1(A or B)

IN2(A or B)

= 1.985MHz at -7dB FS = 2.029MHz at -7dB FS

- 71.8 dBc

(Note 2)

= 7.5MHz at -1dB FS - 69

INA or B

= 20MHz at -1dB FS - 67 - 57

THD

INA or B

= 30MHz at -1dB FS - 67

INA or B

= 115.1MHz at -1dB FS - 65

INA or B

IN1(A or B)

IN2(A or B)

= 106 MHz at -1dB FS = 118 MHz at -1dB FS

0.05 dB

dBc

(Note 3)

REFOUT

REFP

REFN

COM

1dB SNR degradation at Nyquist 2 ps

(Note 4)

(Note 5) 2.012 V

(Note 5) 0.988 V

(Note 5)

1ns

2.048 ± 3%

/ 2

D D

±0.1

RMS

Page 4

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 60MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Differential Reference Output Voltage Range

Reference Temperature Coefficient

BUFFERED EXTERNAL REFERENCE (V

Positive Reference Output Voltage

Negative Reference Output Voltage

Common-Mode Level V

Differential Reference Output Voltage Range

REFIN Resistance R

Maximum REFP, COM Source Current

Maximum REFP, COM Sink Current

Maximum REFN Source Current I

Maximum REFN Sink Current I

U N B U F F ER ED EXT ER N A L R EF ER EN C E ( V

REFP, REFN Input Resistance

REFP, REFN, COM Input Capacitance

Differential Reference Input Voltage Range

COM Input Voltage Range V

REFP Input Voltage V

REFN Input Voltage V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

Input High Threshold V

PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS

∆V

REFP

REFN

COM

∆V

REFIN

SOURCE

SINK

SOURCE

SINK

REFP

REFN

∆V

COM

REFP

REFN

∆V

REF

REFIN

= V

REF

= 2.048V)

REFP

- V

REFN

(Note 5) 2.012 V

(Note 5) 0.988 V

(Note 5)

∆V

REF

RE F IN

= V

REF

= AGN D , r efer ence vol tag e ap p l i ed to RE FP , RE FN , and C OM )

Measured between REFP, COM, REFN,

REFP

- V

REFN

and COM

∆V

REF

= V

REFP

- V

REFN

CLK

PD, OE, SLEEP, T/B

0.8 ×

1.024

± 3%

±100 ppm/°C

/ 2

D D

± 0.1

1.024

± 2%

750 MΩ

5mA

- 250 µA

250 µA

- 5mA

4kΩ

15 pF

1.024

±10%

/ 2

D D

±5%

C OM

∆V

/ 2

RE F

C OM

∆V

/ 2

RE F

Page 5

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 60MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Input Low Threshold V

Input Hysteresis V

Input Leakage

Input Capacitance C

DIGITAL OUTPUTS (D7A–D0A, D7B–D0B)

Output Voltage Low V

Output Voltage High V

Three-State Leakage Current I

Three-State Output Capacitance C

POWER REQUIREMENTS

Analog Supply Voltage Range V

Output Supply Voltage Range OV

Analog Supply Current I

Output Supply Current I

Analog Power Dissipation PDISS

Power-Supply Rejection

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid Time

OE Fall to Output Enable Time t OE Rise to Output Disable Time t

CLK Pulse Width High t

CLK Pulse Width Low t

PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS

CLK

PD, OE, SLEEP, T/B

HYST

LEAK

OUT

VIH = VDD = OV

VIL = 0 ±20

= -200µA 0.2 V

SINK

SOURCE

OE = OV OE = OV

CL = 15pF 1.7 3 3.6 V

Operating, f

= 200µA

INA & B

= 20MHz at

-1dB FS applied to both channels

VDD

Sleep mode 3 Shutdown, clock idle, PD = OE = OV

Operating, f

INA & B

= 20MHz at

-1dB FS applied to both channels (Note 6)

OVDD

Sleep mode 3 Shutdown, clock idle, PD = OE = OV

Operating, f

INA & B

= 20MHz at

-1dB FS applied to both channels

0.2 ×

0.15 V

±20

5pF

- 0.2

±10 µA

5pF

2.7 3 3.6 V

40 50

0.1 20 µA

9mA

310

120 150

Sleep mode 9

0.3 60 µW

mV/V

5ns

PSRR

ENABLE

DISABLE

Shutdown, clock idle, PD = OE = OV

Offset, VDD ±5% ±3

Gain, V

±5% ±3

CL = 20pF (Notes 1, 7) 6 9 ns

Clock period: 16.67ns (Note 7) 8.33 ± 1.5 ns

µA

Page 6

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs, f

CLK

= 60MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two

applied input signals with the same magnitude (peak-to-peak) at f

IN1

and f

IN2

Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 6: Typical analog output current at f

INA&B

= 20MHz. For digital output currents vs. analog input frequency,

see Typical Operating Characteristics.

Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock

level to 50% of the data output level.

Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.

Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.

Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-

mental of the calculated FFT.

Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental

of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.

Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.

Wake-Up Time t

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

Gain Matching f

Phase Matching f

PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS

WAKE

Wake up from sleep mode 1

Wake up from shutdown mode (Note 11) 20

= 20MHz at -1dB FS (Note 8) - 72 dB

INA or B

= 20MHz at -1dB FS (Note 9) 0.05 dB

INA or B

= 20MHz at -1dB FS (Note 10) ± 0.05 Degrees

INA or B

µs

Page 7

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(VDD= 3V, OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF TA= +25°C, unless otherwise

noted.)

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

-10

-20

-30

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

ANALOG INPUT FREQUENCY (MHz)

CLK

INA

INB

AIN = -1dB FS COHERENT SAMPLING

INA

HD2

= 60.056789MHz = 7.4851051MHz = 19.9333995MHz

HD3

252015105030

TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,

INB

CLK

-10

MAX1197 toc01

INA

INB

-20 AIN = -1dB FS

COHERENT SAMPLING

-30

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

030

TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1197 toc04

CLK

-10

= 9.969325MHz

IN1

= 10.013275MHz

IN2

-20

AIN = -7dB FS COHERENT SAMPLING

-30

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

-10

-20

-30

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

05.0

ANALOG INPUT FREQUENCY (MHz)

IN1

= 60.00640MHz

CLK

= 1.985075MHz

IN1

= 2.029025MHz

IN2

AIN = -7dB FS COHERENT SAMPLING

IN2

4.54.03.0 3.51.0 1.5 2.0 2.50.5

8192-POINT DATA RECORD)

= 60.056789MHz = 29.859778MHz = 19.9333995MHz

HD2

ANALOG INPUT FREQUENCY (MHz)

8192-POINT DATA RECORD)

= 60.00640MHz

ANALOG INPUT FREQUENCY (MHz)

INB

IN1

IN2

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

255101520

HD3

-10

MAX1197 toc02

-20

-30

INA

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

ANALOG INPUT FREQUENCY (MHz)

INA

HD2

= 60.056789MHz

CLK

= 114.974441MHz

INA

= 99.945816MHz

INB

AIN = -1dB FS COHERENT SAMPLING

INB

HD3

255101520030

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1197 toc05

SNR (dB)

1412 138 9 10 117

0 200

ANALOG INPUT FREQUENCY (MHz)

CHA

CHB

1601208040

MAX1197 toc03

MAX1197 toc06

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

SINAD (dB)

0 200

ANALOG INPUT FREQUENCY (MHz)

CHB

CHA

TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY

-40

MAX1197 toc07

-50

CHB

-60

THD (dBc)

-70

-80

1601208040

-90 0 200

ANALOG INPUT FREQUENCY (MHz)

CHA

1601208040

MAX1197 toc08

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

SFDR (dBc)

CHB

CHA

0 200

ANALOG INPUT FREQUENCY (MHz)

MAX1197 toc09

1601208040

Page 8

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF TA= +25°C, unless otherwise

noted.)

DIFFERENTIAL NONLINEARITY

(262144-POINT DATA RECORD)

MAX1197 toc18

DIGITAL OUTPUT CODE

DNL (LSB)

224192128 16064 9832

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5 0 256

INTEGRAL NONLINEARITY

(262144-POINT DATA RECORD)

MAX1197 toc17

DIGITAL OUTPUT CODE

INL (LSB)

224192128 16064 9832

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5 0 256

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f

= 19.9333995MHz)

MAX1197 toc16

INPUT POWER (dB FS)

SFDR (dBc)

-4-8-12-16

-20 0

TOTAL HARMONIC DISTORTION

vs. INPUT POWER (f

= 19.9333995MHz)

MAX1197 toc15

INPUT POWER (dB FS)

THD (dBc)

-4-8-12-16

-70

-65

-60

-55

-50

-45

-75

-20 0

SIGNAL-TO-NOISE + DISTORTION

vs. INPUT POWER (f

= 19.9333995MHz)

MAX1197 toc14

INPUT POWER (dB FS)

SINAD (dB)

-4-8-12-16

-20 0

SIGNAL-TO-NOISE RATIO vs. INPUT POWER

= 19.9333995MHz)

MAX1197 toc13

INPUT POWER (dB FS)

SNR (dB)

-4-8-12-16

-20 0

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

MAX1197 toc12

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

10010

-3

-2

-1

-4 1 1000

VIN = 100mV

P-P

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

MAX1197 toc11

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

10010

-4

-3

-2

-1

-5 1 1000

SNR/SINAD, THD/SFDR

vs. TEMPERATURE

MAX1197 toc10

TEMPERATURE (°C)

SNR/SINAD, THD/SFDR (dB, dBc)

603510-15

-40 85

THD

SFDR

SNR

SINAD

fIN = 19.9333995MHz

Page 9

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF TA= +25°C, unless otherwise

noted.)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1197 toc26

TEMPERATURE (°C)

REFOUT

(V)

603510-15

2.024

2.028

2.032

2.036

2.040

2.020

-40 85

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1197 toc25

VDD (V)

REFOUT

(V)

3.453.303.153.002.85

2.0315

2.0317

2.0319

2.0321

2.0313

2.70 3.60

SNR/SINAD, THD/SFDR

vs. CLOCK DUTY CYCLE

MAX1195 toc24

CLOCK DUTY CYCLE (%)

SNR/SINAD, THD/SFDR (dB, dBc)

605040

30 70

SNR

SINAD

THD

SFDR

fIN = 19.9333995MHz

DIGITAL SUPPLY CURRENT

vs. ANALOG INPUT FREQUENCY

MAX1197 toc23

ANALOG INPUT FREQUENCY (MHz)

OVDD

(mA)

2015105

025

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1197 toc22

TEMPERATURE (°C)

VDD

(mA)

6035-15 10

-40 85

SNR/SINAD, THD/SFDR

vs. SAMPLING SPEED

MAX1197 toc21

SAMPLING SPEED (Msps)

SNR/SINAD, THD/SFDR (dB, dBc)

80604020

-80

-60

-40

-20

100

-100 0 100

SNR

SINAD

THD

fIN = 19.9333995MHz

SFDR

MAX1197 toc20

TEMPERATURE (°C)

OFFSET ERROR (%FS)

603510-15

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-1.0

-40 85

OFFSET ERROR vs. TEMPERATURE, EXTERNAL

REFERENCE V

REFIN

= 2.048V

CHA

CHB

GAIN ERROR vs. TEMPERATURE, EXTERNAL

REFERENCE V

REFIN

= 2.048V

MAX1197 toc19

TEMPERATURE (°C)

GAIN ERROR (%FS)

603510-15

0.1

0.2

0.3

0.4

0.5

-0.1

-40 85

CHB

CHA

Page 10

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage I/O. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11, 14, 15 V

3, 7, 10, 13, 16 GND Analog Ground

4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

18 SLEEP

19 PD

20 OE

21 D7B Three-State Digital Output, Bit 7 (MSB), Channel B

22 D6B Three-State Digital Output, Bit 6, Channel B

23 D5B Three-State Digital Output, Bit 5, Channel B

24 D4B Three-State Digital Output, Bit 4, Channel B

25 D3B Three-State Digital Output, Bit 3, Channel B

26 D2B Three-State Digital Output, Bit 2, Channel B

27 D1B Three-State Digital Output, Bit 1, Channel B

28 D0B Three-State Digital Output, Bit 0, Channel B

29, 30, 35, 36 N.C. No Connect

31, 34 OGND Output Driver Ground

32, 33 OV

37 D0A Three-State Digital Output, Bit 0, Channel A

38 D1A Three-State Digital Output, Bit 1, Channel A

39 D2A Three-State Digital Output, Bit 2, Channel A

40 D3A Three-State Digital Output, Bit 3, Channel A

41 D4A Three-State Digital Output, Bit 4, Channel A

Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with

0.1µF.

T/B Selects the ADC Digital Output Format High: Two’s complement Low: Straight offset binary

Sleep Mode Input High: Disables both quantizers, but leaves the reference bias circuit active Low: Normal operation

High-Active Power Down Input High: Power-down mode Low: Normal operation

Low-Active Output Enable Input High: Digital outputs disabled Low: Digital outputs enabled

Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF.

Page 11

Detailed Description

The MAX1197 uses a seven-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles.

Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results

back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all seven stages.

Input Track-and-Hold Circuits

Figure 2 displays a simplified functional diagram of the input T/H circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 11

Pin Description (continued)

Figure 1. Pipelined Architecture—Stage Blocks

PIN NAME FUNCTION

42 D5A Three-State Digital Output, Bit 5, Channel A

43 D6A Three-State Digital Output, Bit 6, Channel A

44 D7A Three-State Digital Output, Bit 7 (MSB), Channel A

45 REFOUT

46 REFIN

47 REFP

48 REFN

STAGE 1 STAGE 2

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider.

Reference Input. V Bypass to GND with a > 0.1µF capacitor.

Positive Reference I/O. Conversion range is ±(V Bypass to GND with a > 0.1µF capacitor.

Negative Reference I/O. Conversion range is ±(V Bypass to GND with a > 0.1µF capacitor.

STAGE 6

REFIN

2-BIT FLASH

STAGE 7

= 2 x (V

ADC

REFP

– V

REFN

– V

REFP

– V

REFP

STAGE 1 STAGE 2

REFN

2-BIT FLASH

ADC

STAGE 6 STAGE 7

DIGITAL ALIGNMENT LOGIC

T/H

INA

D7A–D0A

= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

INA

= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

INB

DIGITAL ALIGNMENT LOGIC

T/H

INB

D7B–D0B

Page 12

MAX1197

are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1 sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connects capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on

capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1197 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+ and INA-, INB-) can be driven either differentially or single-ended.

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

12 ______________________________________________________________________________________

Figure 2. MAX1197 T/H Amplifiers

INA+

INA-

INB+

S4a

S4b

S4a

S4c

C2a

C2b

C2a

INTERNAL

BIAS

S2a

S2b

INTERNAL

BIAS

INTERNAL

BIAS

S2a

C1a

C1b

C1a

COM

S5a

S5b

S5a

S3a

S3b

S3a

OUT

HOLD

TRACK

HOLD

TRACK

CLK

INTERNAL NONOVERLAPPING CLOCK SIGNALS

INB-

S4b

C2b

S2b

INTERNAL

BIAS

C1b

S5b

COM

OUT

MAX1197

S3b

Page 13

Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to mid-supply (VDD/2) for optimum performance.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1197 is determined by the internally generated voltage difference between REFP (VDD/2 + V

REFIN

/4) and REFN (VDD/2 - V

REFIN

/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose.

The MAX1197 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources.

For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section.

Clock Input (CLK)

The MAX1197’s CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows:

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 13

Figure 3. System Timing Diagram

5-CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

D7A–D0A

DATA OUTPUT

D7B–D0B

N - 6

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N + 6

N + 1

Page 14

MAX1197

where fINrepresents the analog input frequency and tAJis the time of the aperture jitter.

Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.

The MAX1197 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics table.

System Timing Requirements

Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1197 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 3 also determines the relationship between the input clock parameters and the valid output data on channels A and B.

Digital Output Data (D0A/B–D7A/B), Output

Data Format Selection (T/B), Output

Enable (OE)

All digital outputs, D0A–D7A (channel A) and D0B–D7B (channel B), are TTL/CMOS-logic compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can either be straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A–D7A and D0B–D7B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1197, thereby degrading its dynamic performance. Using

buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1197, small series resistors (e.g., 100Ω) may be added to the digital output paths close to the MAX1197.

Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid.

Power-Down and Sleep Modes

The MAX1197 offers two power-save modes—sleep mode (SLEEP) and full power-down (PD) mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3mA.

To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed operational amplifiers. The user can select the R

ISO

and CINvalues to optimize the filter performance, to suit a particular application. For the application in Figure 5, a R

ISO

of 50Ω is placed

before the capacitive load to prevent ringing and oscil-

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

14 ______________________________________________________________________________________

Figure 4. Output Timing Diagram

Table 1. MAX1197 Output Codes For Differential Inputs

REF

= V

REFP

- V

REFN

ENABLE

OUTPUT

D7A–D0A

OUTPUT

D7B–D0B

SNR

log=×

DISABLE

VALID DATA

×× ×

2 π

IN AJ

D IFF ER EN T IAL

HIGH-ZHIGH-Z

IN PU T

VO LT A G E*

x 255/256

REF

x 1/256 +1LSB 1000 0001 0000 0001

REF

0 Bipolar zero 1000 0000 0000 0000

-V

x 1/256 -1LSB 0111 1111 1111 1111

REF

-V

x 255/256

REF

-V

x 256/256 -Full Scale 0000 0000 1000 0000

REF

D IFF ER EN T IAL

IN PU T

+Full Scale

-1LSB

-Full Scale +1LSB

ST RA IG HT

O F FSET B INA R Y

T/B = 0 T/B = 1

1111 1111 0111 1111

0000 0001 1000 0001

T WO’S

C O M PL EM EN T

Page 15

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 15

Figure 5. Typical Application for Single-Ended-to-Differential Conversion

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

300Ω

0.1µF

300Ω

600Ω

0.1µF

+5V

MAX4108

-5V

+5V

MAX4108

-5V

+5V

600Ω

0.1µF

600Ω

0.1µF

LOWPASS FILTER

IS0

50Ω

LOWPASS FILTER

IS0

50Ω

LOWPASS FILTER

C 22pF

INA-

COM

INA+

MAX1197

MAX4108

-5V

+5V

MAX4108

-5V

0.1µF

600Ω

0.1µF

600Ω

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

600Ω

300Ω

0.1µF 600Ω

300Ω

0.1µF

IS0

50Ω

LOWPASS FILTER

IS0

50Ω

22pF

C 22pF

INB-

INB+

Page 16

MAX1197

lation. The 22pF CINcapacitor acts as a small filter capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1197 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.

In general, the MAX1197 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are

balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.

Buffered External Reference Drives

Multiple ADCs

Multiple-converter systems based on the MAX1197 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source.

A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise voltage density of 150nV/√Hz. Its output passes through a 1-pole lowpass filter (with 10Hz

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

16 ______________________________________________________________________________________

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

Figure 6. Transformer-Coupled Input Drive

Ω

0.1µF 1

N.C.

MINICIRCUITS

TT1–6-KK81

MINICIRCUITS

TT1–6-KK81

0.1µF

22pF

2.2µF

0.1µF

Ω

22pF

Ω

22pF

0.1µF

Ω

22pF

INA+

COM

INA-

INB+

INB-

MAX1197

MAX4108

100Ω

MAX4108

100Ω

0.1µF

REFP

REFN

REFP

REFN

1kΩ

0.1µF

R 50Ω

ISO

22pF

ISO

50Ω

22pF

ISO

22pF

ISO

50Ω

22pF

INA+

COM

INA-

MAX1197

INB+

INB-

Page 17

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 17

cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation.

Unbuffered External Reference Drives

Multiple ADCs

Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. These three voltages are buffered by the

MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/√Hz. The 2.0V and

1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and

1.0V buffers drive the ADC’s internal ladder resistances between them.

Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended.

Typical QAM Demodulation Application

A frequently used modulation technique in digital communications applications is quadrature amplitude

MAX4250

MAX6062

16.2k

Ω

162

Ω

3.3V

10Hz LOWPASS FILTER

REFOUT

REFP

REFIN

1µF

MAX1197

N = 1

REFN

29N.C.

2.048V

N.C.

COM

REFOUT

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.

REFP

REFIN

MAX1197

N = 1000

REFN

COM

0.1µF

3.3V

0.1µF0.1µF0.1µF

0.1µF

2.2µF 10V

0.1µF0.1µF

0.1µF

100µF

0.1µF

Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference

Page 18

MAX1197

modulation (QAM). Typically found in spread-spectrumbased systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90° phase shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3V, 8-bit ADC MAX1197 and the MAX2451 quadrature demodulator to recover and digi-

tize the I and Q baseband signals. Before being digitized by the MAX1197, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.

Grounding, Bypassing,

and Board Layout

The MAX1197 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

18 ______________________________________________________________________________________

Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066

3.3V

MAX6066

MAX4254 POWER SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP.

3.3V

0.1µF

21.5kΩ

1µF

21.5kΩ

2.0V

1.5V

1.0V

3.3V

1/4 MAX4252

3.3V

1/4 MAX4252

3.3V

1/4 MAX4252

10µF 6V

47kΩ

1.47kΩ

47kΩ

1.47kΩ

47kΩ

1.47kΩ

2.0V AT 8mA

330µF

1.5V AT 0mA

1.0V AT -8mA

330µF

N.C.

29N.C.

REFOUT

REFIN

REFP

REFN

N = 1

COM

REFOUT

REFIN

REFP

REFN

COM

MAX1197

0.1µF

N = 32

MAX1197

0.1µF0.1µF0.1µF

2.2µF

10V

0.1µF

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.

0.1µF0.1µF

Page 19

inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short.

Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated

from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns.

Static Parameter Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1197 are measured using the best-straight-line-fit method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 19

Figure 10. Typical QAM Application Using the MAX1197

Figure 11. T/H Aperture Timing

DOWNCONVERTER

CLK

ANALOG

INPUT

SAMPLED

DATA (T/H)

TRACK TRACK

T/H

HOLD

MAX2451

INA+ INA-

INB+ INB-

MAX1197

DSP

POST-

PROCESSING

Page 20

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

20 ______________________________________________________________________________________

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-bits):

SNR

dB[max]

= 6.02

✕ N + 1.76

In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.

Effective Number of Bits

Effective number of bits (ENOB) specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:

Total Harmonic Distortion

THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion

The two-tone intermodulation distortion (IMD) is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale and their envelope is at -1dB full scale.

Chip Information

TRANSISTOR COUNT: 11,601

PROCESS: CMOS

ENOB

SINAD

−176

602

VVVV

+++

THD

log=×

2232425

Page 21

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 21

Pin-Compatible Upgrades

(Sampling Speed and Resolution)

Functional Diagram

*Future product, please contact factory for availability.

GND

INA+

INA-

CLK

INB+

INB-

T/H

CONTROL

REFERENCE

ADC

DEC

OUTPUT DRIVERS

MAX1197

REFOUT

REFN

COM

REFP

REFIN

OGND OV

D7A–D0A

D7B–D0B

T/B

PD SLEEP

8-BIT PART 10-BIT PART SAMPLING SPEED (Msps)

MAX1195 MAX1183 40

MAX1197 MAX1182 60

MAX1198 MAX1180 100

MAX1196* MAX1186 40, multiplexed

Page 22

MAX1197

Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

48L,TQFP.EPS