The MAX1195 is a 3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1195
is optimized for low-power, small size, and high-dynamic
performance for applications in imaging, instrumentation
and digital communications. This ADC operates from a
single 2.7V to 3.6V supply, consuming only 87mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 48.5dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters
may also be operated with single-ended inputs. In addition to low operating power, the MAX1195 features a
3mA sleep mode as well as a 0.1µA power-down mode
to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1195 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s
complement or straight offset binary through a single control pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1195 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher speed versions of the MAX1195
are also available. Refer to the MAX1197 data sheet for
60Msps and the MAX1198 data sheet for 100Msps. In
addition to these speed grades, this family will include a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1183 data sheet. With the N.C. pins of the MAX1195
internally pulled down to ground, this ADC becomes a
drop-in replacement for the MAX1183.
Applications
Features
♦ Single 2.7V to 3.6V Operation
♦ Excellent Dynamic Performance
48.5dB/46.7dB SINAD at f
IN
= 20MHz/200MHz
68.7dBc/55.7dBc SFDR at fIN= 20MHz/200MHz
♦ -72dB Interchannel Crosstalk at fIN= 20MHz
♦ Low Power
87mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)
♦ 0.05dB Gain and ±0.05° Phase Matching
♦ Wide ±1V
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs, f
CLK
= 40MHz, TA= T
MIN
to T
MAX
, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at
T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND .................................-0.3V to (V
DD
+ 0.3V)
OE, PD, SLEEP, T/B, D7A–D0A,
D7B–D0B to OGND .............................-0.3V to (OV
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs, f
CLK
= 40MHz, TA= T
MIN
to T
MAX
, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at
T
A
= +25°C.)
Signal-to-Noise
and Distortion
Spurious-Free
Dynamic Range
Third-Harmonic
Distortion
Intermodulation Distortion
(First Five Odd-Order IMDs)
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
(First Four Harmonics)
Small-Signal BandwidthInput at -20dB FS, differential inputs500MHz
Full-Power BandwidthFPBWInput at -1dB FS, differential inputs400MHz
Gain Flatness
(12MHz Spacing)
Aperture Delayt
Aperture Jittert
Overdrive Recovery TimeFor 1.5 × full-scale input2ns
IN T ER N A L REF ER EN C E ( RE FIN = RE FOU T thr oug h 10kΩ r esi stor ; RE FP , RE FN , and C OM l evel s ar e g ener ated i nter nal l y. )
Reference Output VoltageV
Positive Reference Output
Voltage
Negative Reference Output
Voltage
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITS
f
= 1MHz at -1dB FS48.6
INA or B
f
= 7.5MHz at -1dB FS48.5
SINAD
SFDR
HD3
IMD
INA or B
f
= 20MHz at -1dB FS4748.5
INA or B
f
= 115.1MHz at -1dB FS47.8
INA or B
f
= 1MHz at -1dB FS73
INA or B
f
= 7.5MHz at -1dB FS69
INA or B
f
= 20MHz at -1dB FS6068.7
INA or B
= 115.1MHz at -1dB FS63
f
INA or B
f
= 1MHz at -1dB FS- 75
INA or B
f
= 7.5MHz at -1dB FS- 73
INA or B
f
= 20MHz at -1dB FS- 70
INA or B
= 115.1MHz at -1dB FS- 63
f
INA or B
f
IN1(A or B)
f
IN2(A or B)
= 1.997MHz at -7dB FS
= 2.046MHz at -7dB FS
dB
dBc
dBc
- 69.5dBc
(Note 2)
IM3
f
IN1(A or B)
f
IN2(A or B)
= 1.997MHz at -7dB FS
= 2.046 MHz at -7dB FS
- 71.7dBc
(Note 2)
f
= 1MHz at -1dB FS- 70
INA or B
f
= 7.5MHz at -1dB FS- 69
THD
INA or B
f
= 20MHz at -1dB FS- 69-57
INA or B
= 115.1MHz at -1dB FS- 62
f
INA or B
f
IN1(A or B)
f
IN2(A or B)
= 106 MHz at -1dB FS
= 118 MHz at -1dB FS
0.05dB
dBc
(Note 3)
AD
AJ
REFOUT
V
REFP
V
REFN
(Note 1)1ns
1dB SNR degradation at Nyquist2ps
(Note 4)
2.048
± 3%
(Note 5)2.012V
(Note 5)0.988V
RMS
V
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Note 1: Guaranteed by design. Not subject to production testing.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at f
IN1
and f
IN2
.
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6: Typical analog output current at f
INA&B
= 20MHz. For digital output currents vs. analog input frequency,
see Typical Operating Characteristics.
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock
level to 50% of the data output level.
Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.
Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental
of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs, f
CLK
= 40MHz, TA= T
MIN
to T
MAX
, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at
T
A
= +25°C.)
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE Fall to Output Enable Timet
OE Rise to Output Disable Timet