Rainbow Electronics MAX1182 User Manual

General Description

The MAX1182 is a +3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, 9stage ADCs. The MAX1182 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation and digital communication applications. This ADC operates from a single +2.7V to +3.6V supply, consuming only 195mW while delivering a typical signal-to-noise ratio (SNR) of 59dB at an input frequency of 20MHz and a sampling rate of 65Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1182 features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods.

An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range.

The MAX1182 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1182 is available in a 7mm x 7mm, 48pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.

Pin-compatible higher and lower speed versions of the MAX1182 are also available. Please refer to the MAX1180 datasheet for 105Msps, the MAX1181 datasheet for 80Msps, the MAX1183 datasheet for 40Msps, and the MAX1184 datasheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port.

Applications

High Resolution Imaging

I/Q Channel Digitization

Multchannel IF Undersampling

Instrumentation

Video Application

Features

♦ Single +3V Operation ♦ Excellent Dynamic Performance:

59dB SNR at f

= 20MHz

77dB SFDR at f

= 20MHz

♦ Low Power:

65mA (Normal Operation)

2.8mA (Sleep Mode) 1µA (Shutdown Mode)

♦ 0.02dB Gain and 0.25° Phase Matching (typ) ♦ Wide ±1V

P-P

Differential Analog Input Voltage

Range

♦ 400MHz -3dB Input Bandwidth ♦ On-Chip +2.048V Precision Bandgap Reference ♦ User-Selectable Output Format—Two’s

Complement or Offset Binary

♦ 48-Pin TQFP Package with Exposed Pad for

Improved Thermal Dissipation

♦ Evaluation Kit Available

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

19-2094; Rev 0; 7/01

Ordering Information

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP. RANGE PIN-PACKAGE

MAX1182ECM -40°C to +85°C 48 TQFP-EP

REFN

REFP

REFIN

REFOUT

D9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

COM

V GND INA+ INA-

V GND INBINB+ GND

CLK

4847464544434241403938

1314151617181920212223

GND

MAX1182

T/B

GND

48 TQFP-EP

SLEEP

D9B

D8B

D7B

D6B

D1A D0A

OGND

D0B

D1B

D2B

D3B

D4B

D5B

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 65MHz (50% duty cycle),

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDD to GND...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

REFIN, REFOUT, REFP, REFN, CLK,

COM to GND ..........................................-0.3V to (V

+ 0.3V)

OE, PD, SLEEP, T/B, D9A–D0A,

D9B–D0B to OGND .............................-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead temperature (soldering, 10s) ..................................+300°C

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.47MHz ±0.6 ±1.9 LSB

Differential Nonlinearity DNL fIN = 7.47MHz, no missing codes guaranteed ±0.4 ±1.0 LSB Offset Error < ±1 ±1.7 % FS Gain Error 0 ±2 % FS

ANALOG INPUT

Differential Input Voltage Range

Common-Mode Input Voltage Range

Input Resistance R

Input Capacitance C

CONVERSION RATE

Maximum Clock Frequency f

Data Latency 5

DYNAMIC CHARACTERISTICS (f

Signal-to-Noise Ratio SNR

Signal-to-Noise and Distortion (up to 5th harmonic)

Spurious-Free Dynamic Range SFDR

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFF

CLK

= 65MHz, 4096-point FFT)

CLK

SINAD

Differential or single-ended inputs ±1.0 V

Switched capacitor load 33 kΩ

= 7.47MHz, TA = +25°C 56.8 59.5

INA or B

= 20MHz, TA = +25°C 56.5 59

INA or B

= 39.9MHz (Note 1) 59

INA or B

= 7.47MHz, TA = +25°C 56.5 59

INA or B

= 20MHz, TA = +25°C 56 58.5

INA or B

= 39.9MHz (Note 1) 58.5

INA or B

= 7.47MHz, TA = +25°C6576

INA or B

= 20MHz, TA = +25°C6577

INA or B

= 39.9MHz, (Note 1) 75

INA or B

VDD/2

± 0.5

5pF

65 MHz

Clock

Cycles

dBc

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 65MHz (50% duty cycle),

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Intermodulation Distortion (first 5 odd-order IMDs)

Total Harmonic Distortion (first 5 harmonics)

Small-Signal Bandwidth Input at -20dB FS, differential inputs 500 MHz

Full-Power Bandwidth FPBW Input at -0.5dB FS, differential inputs 400 MHz

Aperture Delay t

Aperture Jitter t

Overdrive Recovery Time For 1.5 x full-scale input 2 ns Differential Gain ±1% Differential Phase ±0.25 d egr ees

Output Noise INA+ = INA- = INB+ = INB- = COM 0.2 LSB

INTERNAL REFERENCE

Reference Output Voltage REFOUT

Reference Temperature Coefficient

Load Regulation 1.25 mV/mA

BUFFERED EXTERNAL REFERENCE (V

REFIN Input Voltage V

Positive Reference Output Voltage

Negative Reference Output Voltage

Differential Reference Output Voltage Range

REFIN Resistance R

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 7.47MHz -83

INA or B

= 20MHz -82Third-Harmonic Distortion HD3

INA or B

= 39.9MHz (Note 1) -77

INA or B

= 19.13042MHz at -6.5dB FS

REF

REFIN

REF

INA or B

= 21.2886M H z at - 6.5d B FS ( N ote 2)

I N A o r B

= 7.47MHz, TA = +25°C -75.5 -64

INA or B

= 20MHz, TA = +25°C -76 -63

INA or B

= 39.9MHz, (Note 1) -74

INA or B

= +2.048V)

∆V

REF

= V

REFP

- V

REFN

IMD

THD

REFIN

REFP

REFN

∆V

REFIN

dBc

-75 dBc

dBc

1ns

2ps

2.048

±3%

60 ppm/°C

2.048 V

2.012 V

0.988 V

0.98 1.024 1.07 V

>50 MΩ

RMS

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 65MHz (50% duty cycle),

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maximum REFP, COM Source Current

Maximum REFP, COM Sink Current

Maximum REFN Source Current I

Maximum REFN Sink Current I

UNBUFFERED EXTERNAL REFERENCE

REFP, REFN Input Resistance

Differential Reference Input Voltage

COM Input Voltage V

REFP Input Voltage V

REFN Input Voltage V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

Input High Threshold V

Input Low Threshold V

Input Hysteresis V

Input Leakage

Input Capacitance C

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output Voltage Low V

Output Voltage High V

Three-State Leakage Current I

Three-State Output Capacitance C

SOURCE

SINK

SOURCE

SINK

= AGND, reference voltage applied to REFP, REFN, and COM)

REFIN

Measured between REFP and COM, and REFN and COM

∆V

REF

= V

REFP

– V

REFN

CL K 0.8 x V PD, OE, SLEEP, T/B 0.8 x OV

CL K 0.2 x V PD, OE, SLEEP, T/B 0.2 x OV

VIH = OV

or V

(CLK) ±5

VIL = 0 ±5

= 200µA 0.2 V

SINK

OE = OV OE = OV

= 200µA OVDD - 0.2 V

SOURCE

R R

∆V

LEAK

REFP

REFN

REF

COM

REFP

REFN

HYST

OUT

>5 mA

250 µA

>5 mA

4kΩ

1.024 ±10%

VDD/2 ± 10%

COM

∆V

REF

COM

∆V

REF

0.1 V

5pF

±10 µA

5pF

µA

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 65MHz (50% duty cycle),

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale

input voltage range.

Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB or better, if referenced to the two-tone envelope.

Note 3: Digital outputs settle to V

, VIL. Parameter guaranteed by design.

Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OV

range with reduced CL.

POWER REQUIREMENTS

Analog Supply Voltage Range V

Output Supply Voltage Range OV

Analog Supply Current I

Output Supply Current I

Power Dissipation PDISS

Power-Supply Rejection Ratio PSRR

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid t

Output Enable Time t

Output Disable Time t

CLK Pulse Width High t

CLK Pulse Width Low t

Wake-Up Time t

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

Gain Matching f

Phase Matching f

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VDD

OVDD

ENABLE

DISABLE

WAKE

Operating, f

Sleep mode 2.8 Shutdown, clock idle, PD = OE = OV

Operating, CL = 15pF, f

-0.5dB FS

Sleep mode 100 Shutdown, clock idle, PD = OE = OV

Operating, f

Sleep mode 8.4 Shutdown, clock idle, PD = OE = OV Offset ±0.2 mV/V Gain ±0.1 %/V

Figure 3 (Note 3) 5 8 ns

Figure 4 10 ns

Figure 4 1.5 ns

Figure 3, clock period: 15.4ns

Wakeup from Sleep mode (Note 4) 0.42

Wakeup from Shutdown (Note 4) 1.5

= 20MHz at -0.5dB FS -70 dB

INA or B

= 20MHz at -0.5dB FS 0.02 ±0.2 dB

INA or B

= 20MHz at -0.5dB FS 0.25 d eg r ees

INA or B

= 20MHz at -0.5dB FS 65 80

INA or B

= 20MHz at

INA or B

= 20MHz at -0.5dB FS 195 240

INA or B

2.7 3.0 3.6 V

1.7 2.5 3.6 V

115µA

11 mA

210

345µW

7.7 ± 1.5

µA

µs

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, f

CLK

= 65MHz, CL≈ 10pF, TA= +25°C, unless otherwise

noted.)

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

INA

= 6.0065MHz

INB

= 7.51410MHz

CLK

= 65.00057MHz

AINA = -0.55dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

INA

= 6.0065MHz

INB

= 7.51410MHz

CLK

= 65.00057MHz

AINB = -0.56dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

INA

= 20.08257MHz

INB

= 25.09727MHz

CLK

= 65.00057MHz

AINB = -0.52dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

INA

= 20.08257MHz

INB

= 25.09727MHz

CLK

= 65.00057MHz

AINB = -0.52dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

INA

= 37.31661MHz

INB

= 46.99687MHz

CLK

= 65.00057MHz

AINB = -0.52dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc06

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

INA

= 37.31661MHz

INB

= 46.99687MHz

CLK

= 65.00057MHz

AINB = -0.49dB FS

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 5 10 15 20 25 30 35

TWO-TONE IMD PLOT (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1182 toc07

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

IN1

= 19.13042MHz

IN2

= 21.28864MHz

CLK

= 65.00057MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.47dB FS

IN2

2nd ORDER IMD

3rd ORDER IMD

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1182 toc08

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

110100

CHA

CHB

DIFFERENTIAL INPUT CONFIGURATION

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1182 toc09

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

110100

CHA

CHB

DIFFERENTIAL INPUT CONFIGURATION

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, f

CLK

= 65MHz, CL≈ 10pF, TA= +25°C, unless otherwise

noted.)

THD (dB)

GAIN (dB)

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

-65 DIFFERENTIAL INPUT

CONFIGURATION

-68

-71

-74

-77

-80

110100

CHA

ANALOG INPUT FREQUENCY (MHz)

CHB

MAX1182 toc10

SFDR (dB)

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

AIN = 100mV

-2

-4

-6

P-P

MAX1182 toc13

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

DIFFERENTIAL INPUT CONFIGURATION

110100

ANALOG INPUT FREQUENCY (MHz)

SIGNAL-TO-NOISE RATIO

vs. INPUT POWER (f

SNR (dB)

= 20.085279MHz)

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

CHA

CHB

MAX1182 toc11

GAIN (dB)

-2

-4

-6

-8 1 100 100010

ANALOG INPUT FREQUENCY (MHz)

SIGNAL-TO-NOISE + DISTORTION

= 20.085279MHz)

MAX1182 toc14

SINAD (dB)

vs. INPUT POWER (f

MAX1182 toc12

MAX1182 toc15

-8 1 100 100010

ANALOG INPUT FREQUENCY (MHz)

TOTAL HARMONIC DISTORTION

vs. INPUT POWER (f

-55

-60

-65

THD (dB)

-70

-75

-80

-20 -12-16 -8 -4 0 INPUT POWER (dB FS)

= 20.085279MHz)

MAX1182 toc16

-20 -12-16 -8 -4 0 INPUT POWER (dB FS)

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f

SFDR (dB)

-20 -12-16 -8 -4 0 INPUT POWER (dB FS)

= 20.085279MHz)

MAX1182 toc17

-20 -12-16 -8 -4 0 INPUT POWER (dB FS)

INTEGRAL NONLINEARITY

1.0

0.5

INL (LSB)

-0.5

-1.0

(BEST-ENDPOINT FIT)

0 256 384128 512 640 768 896 1024

DIGITAL OUTPUT CODE

MAX1182 toc18

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, f

CLK

= 65MHz, CL≈ 10pF, TA= +25°C, unless otherwise

noted.)

GAIN ERROR vs. TEMPERATURE,

DIFFERENTIAL NONLINEARITY

0.5

0.4

0.3

0.2

0.1

DNL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5 0 256 384128 512 640 768 896 1024

DIGITAL OUTPUT CODE

MAX1182 toc19

EXTERNAL REFERENCE (V

1.0

0.5

-0.5

-1.0

-1.5

GAIN ERROR (% FS)

-2.0

-2.5

-3.0

-40 -15 10 35 60 85 TEMPERATURE (°C)

CHA

OFFSET ERROR vs. TEMPERATURE,

REFIN

CHB

= +2.048V)

0.15

0.10

MAX1182 toc20

0.05

-0.05

OFFSET ERROR (% FS)

-0.10

-0.15

EXTERNAL REFERENCE

REFIN

CHA

-40 10-15 35 60 85 TEMPERATURE (°C)

= +2.048V)

CHB

MAX1182 toc21

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

(mA)

VDD

2.70 3.152.85 3.00 3.30 3.45 3.60 VDD (V)

SFDR, SNR, THD, SINAD

vs. CLOCK DUTY CYCLE

fIN = 25.097265MHz

SFDR

SNR

SFDR, SNR, THD, SINAD (dB)

SINAD

THD

MAX1182 toc22

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

(mA)

VDD

-40 10-15 356085 TEMPERATURE (°C)

MAX1182 toc25

(V)

REFOUT

2.045

2.040

2.035

2.030

2.025

ANALOG POWER-DOWN CURRENT

vs. ANALOG POWER SUPPLY

0.30 OE = PD = OV

MAX1182 toc23

0.24

0.18

(µA)

VDD

0.12

0.06

2.70 3.002.85 3.15 3.30 3.45 3.60

INTERNAL REFERENCE VOLTAGE

vs. ANALOG POWER VOLTAGE

MAX1182 toc24

VDD (V)

MAX1182 toc26

30 40 4535 50 55 60 65 70

CLOCK DUTY CYCLE (%)

2.020

2.70 3.002.85 3.15 3.30 3.45 3.60 VDD (V)

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, f

CLK

= 65MHz, CL≈ 10pF, TA= +25°C, unless otherwise

noted.)

Pin Description

(V)

REFOUT

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.

2, 6, 11, 14, 15 V

3, 7, 10, 13, 16 GND Analog Ground

4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.06

2.05

2.04

2.03

2.02

2.01

2.00

-40 10-15 35 60 85 TEMPERATURE (°C)

Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with

0.1µF.

T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary.

MAX1182 toc27

OUTPUT NOISE HISTOGRAM (DC INPUT)

160000

140000

120000

100000

80000

COUNTS

60000

40000

20000

N-2 N-1 N N+1 N+2

129421

926

DIGITAL OUTPUT CODE

725

MAX1182 toc28

18 SLEEP

19 PD

20 OE

Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation.

Power-Down Input. High: Power-down mode Low: Normal operation

Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

10 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B

22 D8B Three-State Digital Output, Bit 8, Channel B

23 D7B Three-State Digital Output, Bit 7, Channel B

24 D6B Three-State Digital Output, Bit 6, Channel B

25 D5B Three-State Digital Output, Bit 5, Channel B

26 D4B Three-State Digital Output, Bit 4, Channel B

27 D3B Three-State Digital Output, Bit 3, Channel B

28 D2B Three-State Digital Output, Bit 2, Channel B

29 D1B Three-State Digital Output, Bit 1, Channel B

30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B

31, 34 OGND Output Driver Ground

32, 33 OV

35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A

36 D1A Three-State Digital Output, Bit 1, Channel A

37 D2A Three-State Digital Output, Bit 2, Channel A

38 D3A Three-State Digital Output, Bit 3, Channel A

39 D4A Three-State Digital Output, Bit 4, Channel A

40 D5A Three-State Digital Output, Bit 5, Channel A

41 D6A Three-State Digital Output, Bit 6, Channel A

42 D7A Three-State Digital Output, Bit 7, Channel A

43 D8A Three-State Digital Output, Bit 8, Channel A

44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A

45 REFOUT

46 REFIN Reference Input. V

47 REFP

48 REFN Negative Reference Input/Output. Conversion range is ± (V

Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF.

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider.

= 2 ✕ (V

REFIN

Positive Reference Input/Output. Conversion range is ± (V > 0.1µF capacitor.

a > 0.1µF capacitor.

REFP

- V

). Bypass to GND with a >1nF capacitor.

REFN

- V

REFP

REFN

- V

REFP

REFN

). Bypass to GND with a

). Bypass to GND with

Detailed Description

The MAX1182 uses a 9-stage, fully-differential pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles.

1.5-bit (2-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and

hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b, connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1182 to trackand-sample/hold analog inputs of high frequencies (> Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA- as well as INB+ and INB- and set the common-mode voltage to mid-supply (V

/2) for optimum performance.

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 11

Figure 1. Pipelined Architecture—Stage Blocks

T/H

OUT

T/H

OUT

FLASH

ADC

T/H

INA

DAC

1.5 BITS

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

D9A–D0A

= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)

INA

= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)

INB

2-BIT FLASH

ADC

STAGE 8 STAGE 9

FLASH

ADC

T/H

INB

DAC

1.5 BITS

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

D9B–D0B

2-BIT FLASH

ADC

STAGE 8 STAGE 9

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

12 ______________________________________________________________________________________

Figure 2. MAX1182 T/H Amplifiers

INA+

INA-

INB+

S4a

S4b

S4a

S4c

C2a

C2b

C2a

INTERNAL

BIAS

S2a

INTERNAL

BIAS

INTERNAL

BIAS

S2a

S2b

C1a

C1b

C1a

COM

S5a

S5b

S5a

S3a

S3b

S3a

OUT

HOLD

TRACK

HOLD

TRACK

CLK

INTERNAL NONOVERLAPPING CLOCK SIGNALS

INB-

S4b

C2b

INTERNAL

BIAS

S2b

C1b

S5b

COM

OUT

MAX1182

S3b

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 13

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1182 is determined by the internally generated voltage difference between REFP (VDD/2 + V

REFIN

/4) and REFN (VDD/2 - V

REFIN

/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose.

REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs.

The MAX1182 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources.

Clock Input (CLK)

The MAX1182’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows:

SNR

= 20 ✕log10(1 / [2π x fINx tAJ]),

where f

represents the analog input frequency and t

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling applications. The clock input should always be consid-

ered as an analog input and routed away from any analog input or other digital signal lines.

The MAX1182 clock input operates with a voltage threshold set to V

/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics.

System Timing Requirements

Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1182 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (/OE)

All digital outputs, D0A–D9A (Channel A) and D0B–D9B (Channel B), are TTL/CMOS logic-compatible. There is a 5-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A–D9A and D0B–D9B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1182, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1182 small-series resistors (e.g., 100Ω) maybe added to the digital output paths, close to the MAX1182.

Figure 4 displays the timing relationship between output enable and data output valid as well as power down/wake-up and data output valid.

Power-Down (PD) and

Sleep (SLEEP) Modes

The MAX1182 offers two power-save modes—sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA.

To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high impedance state.

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

14 ______________________________________________________________________________________

Applications Information

Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers, follows the

amplifiers. The user may select the R

ISO

and CINvalues to optimize the filter performance, to suit a particular application. For the application in Figure 5, a R

ISO

50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CINcapacitor acts as a small bypassing capacitor.

Using Transformer Coupling

A RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1182 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion.

In general, the MAX1182 provides better SFDR and THD with fully-differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.

Figure 3. System Timing Diagram

Figure 4. Output Timing Diagram

5 CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

D9A–D0A

DATA OUTPUT

D9B–D0B

ENABLE

OUTPUT

D9A–D0A

OUTPUT

D9B–D0B

N - 6

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1

VALID DATA

DISABLE

N - 5

N + 1

HIGH-ZHIGH-Z

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N + 6

N + 1

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 15

Table 1. MAX1182 Output Codes For Differential Inputs

REF

= V

REFP

- V

REFN

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal.

Typical QAM Demodulation Application

The most frequently used modulation technique for digital communications applications is probably the Quadrature Amplitude Modulation (QAM). Typically found in spread-spectrum based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degree phase-shifted with respect to the inphase component. At the receiver, the QAM signal is divided down into it’s I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched +3V, 10-bit ADC MAX1182 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1182, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove any unwanted images from the mixing process, thereby enhancing the overall signalto-noise (SNR) performance and minimizing inter-symbol interference.

Grounding, Bypassing, and

Board Layout

The MAX1182 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADCs package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns.

DIFFERENTIAL INPUT

VOLTAGE*

x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111

REF

x 1/512 + 1 LSB 10 0000 0001 00 0000 0001

REF

0 Bipolar Zero 10 0000 0000 00 0000 0000

- V

x 1/512 - 1 LSB 01 1111 1111 11 1111 1111

REF

-V

x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001

REF

-V

x 512/512 - FULL SCALE 00 0000 0000 10 0000 0000

REF

DIFFERENTIAL

INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

16 ______________________________________________________________________________________

Figure 5. Typical Application for Single-Ended to Differential Conversion

+5V

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

300Ω

600Ω

0.1µF

MAX4108

-5V

+5V

MAX4108

-5V

+5V

MAX4108

600Ω

0.1µF

600Ω

0.1µF

LOWPASS FILTER

IS0

50Ω

LOWPASS FILTER

IS0

50Ω

LOWPASS FILTER

IS0

50Ω

22pF

C 22pF

22pF

INA+

COM

INA-

MAX1182

INB+

+5V

-5V

600Ω

0.1µF

600Ω

0.1µF

LOWPASS FILTER

IS0

50Ω

C 22pF

INB-

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

300Ω

-5V

600Ω

0.1µF

600Ω

MAX4108

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 17

Figure 6. Transformer-Coupled Input Drive

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1182 are measured using the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL

error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9).

25Ω

INA+

22pF

0.1µF

N.C.

MINICIRCUITS

0.1µF

N.C.

MINICIRCUITS

TT1–6

2.2µF

0.1µF

25Ω

22pF

25Ω

22pF

0.1µF

25Ω

22pF

COM

INA-

MAX1182

INB+

INB-

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

18 ______________________________________________________________________________________

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits):

SNR

dB[max]

= 6.02dBx N + 1.76

In reality, there are other noise sources besides quantization noise e.g. thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from:

Figure 7: Using an Op Amp for Single-Ended, AC-Coupled Input Drive

REFP

1kΩ

ISO

50Ω

22pF

INA+

MAX4108

100Ω

0.1µF

REFN

100Ω

REFP

MAX4108

100Ω

0.1µF

REFN

1kΩ

ISO

50Ω

0.1µF

22pF

50Ω

22pF

50Ω

22pF

COM

ISO

INA-

MAX1182

INB+

ISO

INB-

ENOB

SINAD

−176

dB dB

602..

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 19

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:

where V

is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.

Figure 8. Typical QAM Application, Using the MAX1182

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

TRACK TRACK

CLK

Figure 9. T/H Aperture Timing

Chip Information

TRANSISTOR COUNT: 10,811 PROCESS: CMOS

DOWNCONVERTER

MAX2451

0°

90°

INA+ INA-

MAX1182

INB+ INB-

DSP

POST

PROCESSING

THD

=×

log



VVVV



 

+++



  

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

GND

REFERENCE

OUTPUT DRIVERS

CONTROL

T/H

PIPELINE

ADC

DEC

OUTPUT DRIVERS

REFOUT

REFN

COM

REFP

REFIN

INA+

INA-

CLK

INB+

INB-

DEC

PIPELINE

ADC

OGND OV

D9A–D0A

D9B–D0B

T/B PD SLEEP

MAX1182

Functional Diagram

20 ______________________________________________________________________________________

MAX1182

Dual 10-Bit, 65Msps, +3V, Low-Power ADC with

Internal Reference and Parallel Outputs

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21

48L,TQFP.EPS

Rainbow Electronics MAX1182 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual