Rainbow Electronics MAX118 User Manual

Page 1

19-1083; Rev 1; 8/96

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

_______________General Description

The MAX114/MAX118 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital converters (ADCs). They operate from a single +5V supply and use a half-flash technique to achieve a 660ns conversion time (1Msps). A power-down (PWRDN) pin reduces current consumption typically to 1µA. The devices return from power-down mode to normal operating mode in less than 200ns, allowing large supplycurrent reductions in burst-mode applications (in burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals). Both converters include a track/hold, enabling the ADC to digitize fast analog signals.

____________________________Features

♦ Single +5V Supply Operation ♦ 4 (MAX114) or 8 (MAX118) Analog Input Channels ♦ Low Power: 40mW (operating mode)

5µW (power-down mode)

♦ Total Unadjusted Error ≤1LSB ♦ Fast Conversion Time: 660ns per Channel ♦ No External Clock Required ♦ Internal Track/Hold ♦ 1MHz Full-Power Bandwidth ♦ Internally Connected 8th Channel Monitors

Reference Voltage (MAX118)

Microprocessor (µP) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel µP data bus or system input port. The MAX114/MAX118 input/reference configuration enables ratiometric operation.

The 4-channel MAX114 is available in a 24-pin DIP or SSOP. The 8-channel MAX118 is available in a 28-pin DIP or SSOP. For +3V applications, refer to the MAX113/MAX117 data sheet.

________________________Applications

High-Speed DSP Remote Data Acquisition Portable Equipment Communications Systems

______________Ordering Information

PART

MAX114CNG

MAX114CAG MAX114C/D 0°C to +70°C MAX114ENG MAX114EAG MAX114MRG -55°C to +125°C

Ordering Information continued on last page.

*Dice are specified at T **Contact factory for availability.

Pin Configurations appear on last page.

TEMP. RANGE PIN-PACKAGE

0°C to +70°C 0°C to +70°C

-40°C to +85°C 24 Narrow Plastic DIP

-40°C to +85°C

= +25°C, DC parameters only.

24 Narrow Plastic DIP 24 SSOP Dice*

24 SSOP 24 Narrow CERDIP**

_________________________________________________________Functional Diagram

MAX114/MAX118

REF+

D7 D6 D5 D4

D3 D2 D1 D0

Maxim Integrated Products

* MAX118 ONLY



MODE

4-BIT

FLASH

ADC

(4MSBs)

4-BIT

DAC

4-BIT

FLASH

ADC

(4LSBs)

TIMING AND

CONTROL

INT

WR/RDY

THREE-

STATE OUTPUT DRIVERS

MAX114/MAX118

*IN8

*IN7 *IN6

*IN5

IN4 IN3 IN2

IN1

________________________________________________________________

MUX

ADDRESS

LATCH 

DECODE

A1 A2 REF-

REF+

PWRDN

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

Page 2

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

ABSOLUTE MAXIMUM RATINGS

VDDto GND..............................................................-0.3V to +7V

Digital Input Voltage to GND......................-0.3V to (V

Digital Output Voltage to GND...................-0.3V to (V

REF+ to GND..............................................-0.3V to (V

REF- to GND...............................................-0.3V to (V

IN_ to GND.................................................-0.3V to (V

Continuous Power Dissipation (T

24-Pin Narrow Plastic DIP

= +70°C)

DD DD DD DD DD

+ 0.3V) + 0.3V) + 0.3V) + 0.3V) + 0.3V)

(derate 13.33mW/°C above +70°C)....................................1.08W

24-Pin SSOP (derate 8.00mW/°C above +70°C)..............640mW

24-Pin Narrow CERDIP

(derate 12.50mW/°C above +70°C).........................................1W

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

28-Pin Wide Plastic DIP

(derate 14.29mW/°C above +70°C)....................................1.14W

28-Pin SSOP (derate 9.52mW/°C above +70°C)..............762mW

28-Pin Wide CERDIP

(derate 16.67mW/°C above +70°C)....................................1.33W

Operating Temperature Ranges

MAX114/MAX118C_ _...........................................0°C to +70°C

MAX114/MAX118E_ _........................................-40°C to +85°C

MAX114/MAX118M_ _.....................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

MAX114/MAX118

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA= T

CONDITIONS

ACCURACY (Note 1)

No-missing-codes guaranteed

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

Spurious-Free Dynamic Range

SINAD

THDTotal Harmonic Distortion

SFDR

MAX11_C/E, f MAX11_M, f MAX11_C/E, f MAX11_M, f MAX11_C/E, f MAX11_M, f V

= 5Vp-p

SAMPLE

= 1MHz, f

= 740kHz, f

= 1MHz, f

= 740kHz, f

= 1MHz, f

= 740kHz, f

ANALOG INPUT

Input Voltage Range Input Leakage Current Input Capacitance

GND < V

< V

REFERENCE INPUT

Reference Resistance

REF

REF+ Input Voltage Range REF- Input Voltage Range

to T

MIN

= 195.8kHz

= 195.7kHz

= 195.8kHz

= 195.7kHz

= 195.8kHz

= 195.7kHz

, unless otherwise noted.)

MAX

45 45

50 50

REF-

-50

REF+

UNITSMIN TYP MAXSYMBOLPARAMETER

Bits8NResolution LSB±1TUETotal Unadjusted Error LSB±1DNLDifferential Nonlinearity LSB±1Zero-Code Error LSB±1Full-Scale Error LSB±1/4Channel-to-Channel Mismatch

MHz1Input Full-Power Bandwidth V/µs3.1 15Input Slew Rate, Tracking

VV µA±3I pF32C

kΩ124R

VGND V

2 _______________________________________________________________________________________

Page 3

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA= T

CONDITIONS

LOGIC INPUTS

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current Input Capacitance (Note 2)

LOGIC OUTPUTS

Output Low Voltage Output High Voltage

Three-State Current Three-State Capacitance

(Note 2)

POWER REQUIREMENTS

Supply Voltage VDDSupply Current

Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or V

CS, WR, RD, PWRDN, A0, A1, A2

INH

MODE CS, WR, RD, PWRDN, A0, A1, A2

INL

MODE

CS, RD, PWRDN, A0, A1, A2 WR

INH

MODE CS, WR, RD, PWRDN, MODE, A0, A1, A2

INL

CS, WR, RD, PWRDN, MODE, A0, A1, A2

= 1.6mA, INT, D0–D7

SINK

RDY, I I

SOURCE

D0–D7, RDY, digital outputs = 0V to V

LKG

D0–D7, RDY

OUT

CS = RD = 0V,

PWRDN = V CS = RD = VDD, PWRDN = 0V (Note 3)

VDD= 4.75V to 5.25V, V

= 2.6mA

SINK

= 360µA, INT, D0–D7

MAX11_C MAX11_E/M

= 4.75V

REF

MIN

to T

, unless otherwise noted.)

MAX

2.4

3.5

0.8

1.5 ±1 ±3

50 200

0.4

815 820

MAX114/MAX118

UNITSMIN TYP MAXSYMBOLPARAMETER

µA

µA±1I pF58C

V V4V

µA±3I pF58C

V4.75 5.25V

µA110Power-Down VDDCurrent

LSB±1/16 ±1/4PSRPower-Supply Rejection

_______________________________________________________________________________________ 3

Page 4

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

TIMING CHARACTERISTICS

(VDD= +4.75V, TA= +25°C, unless otherwise noted.) (Note 4)

TA= +25°C

SYMBOLPARAMETER

CONDITIONS

ALL GRADES

MIN TYP MAX

660

CRD

Conversion Time (WR-RD Mode)

Conversion Time (RD Mode)

Power-Up Time CS to RD, WR

Setup Time CS to RD, WR

Hold Time

MAX114/MAX118

CS to RDY Delay Data-Access Time

(RD Mode)

ACC0

RD to INT Delay (RD Mode)

Data Hold Time Minimum Acquisition

Time WR Pulse Width Delay Between WR

and RD Pulses RD Pulse Width

(WR-RD Mode) Data-Access Time

(WR-RD Mode)

ACC1

RD to INT Delay WR to INT Delay RD Pulse Width

(WR-RD Mode) Data-Access Time

(WR-RD Mode) WR to INT Delay

ACC2

IHWR

Data-Access Time after INT

Multiplexer Address Hold Time

tRD< t

CWR

(Note 5)

CRD

CSS

CSH

CL= 50pF,

RDY

RL= 5.1kΩ to V CL= 100pF (Note 5)

CL= 50pF

INTH

(Note 6)

(Note 7)

ACQ

tRD< t determined by t

tRD< t (Note 5)

CL= 50pF

INTL

tRD> t t

ACC2

tRD> t (Note 5)

Pipelined mode, CL= 50pF Pipelined mode, CL= 100pF

CL= 20pF

INTL

CL= 100pF 685 865 1125

INTL

ACC1

, CL= 100pF

INTL

, determined by

INTL

, CL= 100pF

INTL

Note 4: Input control signals are specified with tr = tf= 5ns, 10% to 90% of 5V, and timed from a voltage level of 1.6V. Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.8V or 2.4V. Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time.

TA= T

MIN

MAX11_C/E

MIN MAX MIN MAX

875 370

CRD

65 85 70

185

0.28 10

0.35

205

235 185

610

110 100

to T

MAX

MAX11_M

260

0.4 10

0.45

240

CRD

975 520

100

75 90 80

275 220

700

130 120

UNITS

ns700t ns320t ns0t

ns0t

ns70t

ns50 80t ns60 ns160t µs0.25 10t µs0.25t

ns160t

ns185t ns150t

ns380 500t ns65t

ns90t ns80t ns45

ns30t

4 _______________________________________________________________________________________

Page 5

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

__________________________________________Typical Operating Characteristics

(VDD= +5V, TA = +25°C, unless otherwise noted.)

CONVERSION TIME

vs. AMBIENT TEMPERATURE

1.5

1.4

= +5V, +25°C)

1.3

1.2 VDD = +4.75V

1.1

1.0

0.9

0.8

0.7

(NORMALIZED TO VALUE AT V

0.6

CRD

-60 140

-20 10060

AVERAGE POWER CONSUMPTION

vs. SAMPLING RATE USING PWRDN

POWER DISSIPATION (mW)

VDD = +5.25V

VDD = +5V

TEMPERATURE (°C)

MAX114/118-01

MAX114/118-03

EFFECTIVE NUMBER OF BITS vs. 

INPUT FREQUENCY (WR-RD MODE)

8.0

7.5

7.0



6.5

EFFECTIVE NUMBER OF BITS

6.0

= 1MHz

SAMPLE

= 4.96Vp-p



1k 10k 100k

INPUT FREQUENCY (Hz)

SIGNAL-TO-NOISE RATIO

-20

-40

RATIO (dB)

-60

-80

VDD = 4.75V INPUT FREQUENCY = 

195.8ksps = 4.72Vp-p

 SAMPLE  FREQUENCY = 1MHz SNR = 48.2dB

MAX114/118-02

MAX114/118-04

MAX114/MAX118

SAMPLING RATE (CONVERSIONS/SEC)

TOTAL UNADJUSTED ERROR

TUE (LSB)

vs. POWER-UP TIME

75 100 150 175 250

POWER-UP TIME, tUP (ns)

100k

10k 1M

125 200 225

MAX114/118-06

-100

SUPPLY CURRENT (mA)

100 200 500

0 400

-60

FREQUENCY (kHz)

SUPPLY CURRENT vs. TEMPERATURE

(EXCLUDING REFERENCE CURRENT)

TEMPERATURE (°C)

300

MAX114/118-08

60 100 140-20 20

_______________________________________________________________________________________

Page 6

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

______________________________________________________________Pin Description

MAX114 MAX118

IN32 4

IN14 6 7 8

MAX114/MAX118

15 16

23 24

9, 10, 11

16 17

19, 20, 21

22 23 24 25 26 27 28

MODE5

INT

REF-13

REF+14

WR/RDY

FUNCTIONNAME

Analog Input Channel 6IN6— Analog Input Channel 5IN5— 2 Analog Input Channel 4IN41 Analog Input Channel 3 Analog Input Channel 2IN23 Analog Input Channel 1 Mode Selection Input. Internally pulled low with a 50µA current source. MODE = 0 acti-

vates read mode; MODE = 1 activates write-read mode (see Three-State Data Output (LSB)D06 Three-State Data OutputsD1, D2, D37, 8, 9 Read Input. RD must be low to access data (see

Interrupt Output. INT goes low to indicate end of conversion (see section).

GroundGND12 Lower Limit of Reference Span. REF- sets the zero-code voltage. Range is GND ≤

< V

REF-

Upper Limit of Reference Span. REF+ sets the full-scale input voltage. Range is V < V

REF+

Write-Control Input/Ready-Status Output (see Chip-Select Input. CS must be low for the device to recognize WR or RD inputs.CS Three-State Data OutputsD4, D5, D617, 18, 19 Three-State Data Output (MSB)D720 Multiplexer Channel Address Input (MSB)A2— Multiplexer Channel Address Input A121 Multiplexer Channel Address Input (LSB)A022 Power-Down Input. PWRDN reduces supply current when low.PWRDN Positive Supply, +5VV

Analog Input Channel 7IN7—

REF+

≤ VDD. Internally hard-wired to IN8 (Table 1).

Digital Interface

section).RD

Digital Interface

section)

Section).

REF-

6 _______________________________________________________________________________________

Page 7

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

_______________Detailed Description

The MAX114/MAX118 use a half-flash conversion technique (see

Functional Diagram

ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower four data bits (LSBs).

An internal analog multiplexer enables the devices to read four (MAX114) or eight (MAX118) different analog voltages under microprocessor (µP) control. One of the MAX118’s analog channels, IN8, is internally hardwired and always reads V

DATA

OUTPUTS

RL = 3k

a) HIGH-Z TO V

Figure 1. Load Circuits for Data-Access Time Test

DATA

OUTPUTS

a) V

Figure 2. Load Circuits for Data-Hold Time Test

TO HIGH-Z b) V

Converter Operation

) in which two 4-bit flash

when selected.

REF+

RL = 3k

b) HIGH-Z TO V

10pF

TO HIGH-Z

10pF

DATA

OUTPUTS

DATA

OUTPUTS

In burst-mode or low sample-rate applications, the

Power-Down Mode

MAX114/MAX118 can be shut down between conversions, reducing supply current to microamp levels (see

Typical Operating Characteristics

). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1µA when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired after 360ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can be started. If the power-down feature is not required, connect PWRDN to VDD. For minimum current consumption, keep digital inputs at the supply rails in power-down mode. Refer to the

Reference

section for information on reduc-

ing reference current during power-down.

___________________Digital Interface

The MAX114/MAX118 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The A0, A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum time, t

Table 1. Truth Table for Input Channel Selection

In read mode, conversions and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of t

ACQ

With µPs that can be forced into a wait state, hold RD low until output data appears. The µP starts the conversion, waits, and then reads data with a single read instruction.

, before the next conversion starts.

ACQ

MAX114

00 01 10

11 —— —— ——

——

MAX118

A2 A1 A0A1 A0

000 001 010 011 100 101 110

111

SELECTED CHANNEL

IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8

REF+

if selected)

(reads V

Read Mode (MODE = 0)

. Initiate a conversion by driving CS and RD low.

MAX114/MAX118

_______________________________________________________________________________________ 7

Page 8

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a µP. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD.

Write-Read Mode (MODE = 1)

Figures 4 and 5 show the operating sequence for writeread mode. The comparator inputs track the analog input voltage for the duration of t

. The conversion is

ACQ

initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the

MAX114/MAX118

lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see

Timing Characteristics

A minimum acquisition time (t

) is required from INT

ACQ

going low to the start of another conversion (WR going low).

Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections).

Using Internal Delay

The µP waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs D0–D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD.

Fastest Conversion:

Reading Before Delay

Figure 5 shows an external method of controlling the conversion time. The internally generated delay (t

INTL

varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers that contain the conversion result (D0–D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tWR+ tRD+ t

A0–A2

INT

D0–D7

Figure 4. Write-Read Mode Timing (tRD> t

ACC1

ACQ

= 660ns.

CSS

ADDRESS VALID (N)

CSH

INTL

ACC2

ACQ

ADDRESS VALID (N + 1)

CSS

VALID DATA

(N)

) (MODE = 1)

INTL

CSH

INTH

)

ADDRESS VALID

ACQ

RDY

CSS

(N)

WITH EXTERNAL

PULL-UP

CRD

ACCO

PWRDN

A0–A2

RDY

INT

D0–D7

Figure 3. Read Mode Timing (MODE = 0)

CSH

ACQ

ADDRESS VALID (N + 1)

INTH

VALID DATA

(N)

CSH

A0–A2

D0–D7

CSS

INT

ACQ

ADDRESS VALID (N)

INTL

CSS

ACC1

CWR

Figure 5. Write-Read Mode Timing (tRD< t

8 _______________________________________________________________________________________

ACQ

ADDRESS VALID (N + 1)

CSH

VALID DATA

INTL

INTH

(N)

) (MODE = 1)

Page 9

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

Besides the two standard write-read-mode options,

Pipelined Operation

pipelined operation can be achieved by connecting WR to RD (Figure 6). With CS low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion.

_____________Analog Considerations

MAX114 MAX118

Reference



Figures 7a, 7b, and 7c show typical reference connections. The voltages at REF+ and REF- set the ADC’s analog input range (see Figure 10). The voltage at REFdefines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones.

The internal resistance from REF+ to REF- can be as low as 1kΩ, and current will flow through it even when the MAX114/MAX118 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REF-

IN_ GND

REF+ REF-

+5V

4.7µF

0.1µF

IN+

IN-

RD, WR

A0–A2

D0–D7

INT

CSS

ACQ

ADDRESS VALID (N)

OLD DATA (N - 1)

CSH

IHWR

INTL

ACQ

ADDRESS 

VALID (N + 1)

NEW DATA (N)

Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1)

0.1µF

IN_ GND

V REF+

REF-

MAX114 MAX118

+5V

0.1µF

4.7µF

* CURRENT PATH MUST STILL EXIST FROM V

TO GND

IN-

IN+

+2.5V

IN-

0.1µF

MAX114/MAX118

Figure 7a. Power Supply as Reference

C1

0.1µF

IN_ GND

V REF+

REF-

MAX114 MAX118

+5V

4.7µF

0.1µF

MX584

IN+

IN-

Figure 7b. External Reference, 4.096V Full Scale

_______________________________________________________________________________________ 9

Figure 7c. Input Not Referenced to GND

PWRDN

* IRML2402

+5V

0.1µF

MAX874

N-FET*

C1

3.3µF

0.1µF

REF+

REF-

PWRDN

MAX114 MAX118

Figure 7d. An N-channel MOSFET switches off the reference load during power-down

Page 10

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

to break this current path during power-down. The FET should have an on-resistance of less than 2Ω with a 5V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a period of time equal to the power-up delay (tUP) plus the Nchannel FET’s turn-on time.

Although REF+ is frequently connected to VDD, the circuit of Figure 7d uses a low-current, low-dropout,

4.096V voltage reference: the MAX874. Since the MAX874 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applications where the MAX114/MAX118 are normally in standby and are turned on in order to make measurements at intervals greater than 65µs. C1 (the capacitor connected to REF+) is slowly charged by the MAX874 during the standby period, and furnishes the

MAX114/MAX118

reference current during the short measurement period. C1’s 3.3µF value ensures a voltage drop of less than

1/2LSB when performing four to eight successive conversions. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1.

Initial Power-Up

When power is first applied, perform a conversion to initialize the MAX114/MAX118. Disregard the output data.

Bypassing

Use a 4.7µF electrolytic in parallel with a 0.1µF ceramic capacitor to bypass VDDto GND. Minimize capacitor lead lengths.

Bypass the reference inputs with 0.1µF capacitors, as shown in Figures 7a, 7b, and 7c.

Figure 8 shows the equivalent circuit of the MAX114/

Analog Inputs

MAX118 input. When a conversion starts and WR is low, V

is connected to sixteen 0.6pF capacitors.

IN_

During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge.

The typical 32pF input capacitance allows source resistance as high as 800Ω without setup problems. For larger resistances, the acquisition time (t

ACQ

) must be

increased. Internal protection diodes, which clamp the analog

input to VDDand GND, allow the channel input pins to swing from GND - 0.3V to VDD+ 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDDby more than 50mV or be lower than GND by 50mV.

If the analog input exceeds 50mV beyond the supplies, limit the input current to no more than 2mA, as excessive current will degrade the conversion accuracy of the on channel.

Track/Hold

The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, t

ACQ

MAX114

MUX

IN2

Figure 8. Equivalent Input Circuit

10 ______________________________________________________________________________________

.

. .

MAX118

T/H

Figure 9. RC Network Equivalent Input Model

IN_

22pF

10pF

MAX114 MAX118

Page 11

+5V, 1Msps, 4 & 8-Channel,

8-Bit ADCs with 1µA Power-Down

Figure 10 shows the MAX114/MAX118’s nominal trans-

Transfer Function

fer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (V

REF+

- V

REF-

) / 256.

Conversion Rate

The maximum sampling rate (f MAX118 is achieved in write-read mode (tRD< t

) for the MAX114/

MAX

INTL

and is calculated as follows:

MAX

t + t + t + t

WR RD RI ACQ

MAX

250ns 250ns 150ns 160ns

f 1.23MHz

MAX

+++

where tWR= the write pulse width, tRD= the delay between write and read pulses, tRI= RD to INT delay, and t

= minimum acquisition time.

ACQ

Signal-to-Noise Ratio and

Effective Number of Bits

Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate.

The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB.

The FFT Plot (see

Typical Operating Characteristics

shows the result of sampling a pure 195.8kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands.

The effective resolution (or “effective number of bits”) the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD -

1.76) / 6.02 (see

Typical Operating Characteristics

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency

OUTPUT CODE 11111111 11111110

11111101

FULL-SCALE

TRANSITION

1LSB =

00000011 00000010 00000001 00000000

REF-

Figure 10. Transfer Function

123

INPUT VOLTAGE (LSBs)

FS - 1LSB

band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as:

where V



+++

V V V ...V

22324

THD = 20log

is the fundamental RMS amplitude, and V

  



through VNare the amplitudes of the 2nd through Nth harmonics.

)

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC’s noise floor. See the Signal-toNoise Ratio graph in

Typical Operating Characteristics

MAX114/MAX118

- V



REF+

REF-

256

REF+



  



______________________________________________________________________________________ 11

Page 12

+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down

__Ordering Information (continued)

PART

MAX118CPI

MAX118CAI MAX118C/D 0°C to +70°C MAX118EPI MAX118EAI MAX118MJI -55°C to +125°C

TEMP. RANGE PIN-PACKAGE

0°C to +70°C 0°C to +70°C

28 Wide Plastic DIP 28 SSOP Dice*

-40°C to +85°C 28 Wide Plastic DIP

-40°C to +85°C

28 SSOP 28 Wide CERDIP**

___________________Chip Information

TRANSISTOR COUNT: 2011

*Dice are specified at TA= +25°C, DC parameters only. **Contact factory for availability.

__________________________________________________________Pin Configurations

MAX114/MAX118

TOP VIEW

MODE

GND

IN6

MODE

GND

IN5

IN4

IN3

IN2

IN1

D0 D1 D2 D3 RD

INT

MAX118

6 7 8

9 10 11 12 13 14

IN4

IN3

IN2

IN1

MAX114

INT

11 12

PWRDN

WR/RDY

REF+

REF-

DIP/SSOP

IN7 V

PWRDN

23 22

CS WR/RDY

REF+

16 15

REF-

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600