The MAX11644/MAX11645 low-power, 12-bit, 1-/2channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and
an I2C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11645) or 4.5V to 5.5V (MAX11644) and require
only 6μA at a 1ksps sample rate. AutoShutdown™ powers down the devices between conversions, reducing
supply current to less than 1μA at low throughput rates.
The MAX11644/MAX11645 each measure two singleended or one differential input. The fully differential analog inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V
DD
. The MAX11645 features a 2.048V internal reference and the MAX11644
features a 4.096V internal reference.
The MAX11644/MAX11645 are available in an ultra-tiny
1.9mm x 2.2mm WLP package and an 8-pin μMAX
®
package. The MAX11644/MAX11645 are guaranteed
over the extended temperature range (-40°C to +85°C).
For pin-compatible 10-bit parts, refer to the MAX11646/
MAX11647 data sheet.
Applications
Features
♦ Ultra-Tiny 1.9mm x 2.2mm Wafer Level Package
♦ High-Speed I
2
C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
♦ Single-Supply
2.7V to 3.6V (MAX11645)
4.5V to 5.5V (MAX11644)
♦ Internal Reference
2.048V (MAX11645)
4.096V (MAX11644)
♦ External Reference: 1V to V
DD
♦ Internal Clock
2-Channel Single-Ended or 1-Channel Fully
Differential
♦ Internal FIFO with Channel-Scan Mode
♦ Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0, AIN1, REF to GND ..............................-0.3V to the lower of
(VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin .........................................±50mA
(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), V
REF
= 2.048V (MAX11645), V
REF
= 4.096V (MAX11644),
f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Note 1:All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:For DC accuracy, the MAX11644 is tested at VDD= 5V and the MAX11645 is tested at VDD= 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:Offset nulled.
Note 5:Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
DD
.
Note 8:When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1μF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 9:ADC performance is limited by the converter’s noise floor, typically 300μV
P-P
.
Note 10: Measured for the MAX11645 as:
and for the MAX11644, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
Rise Time of SCL Signal After
Acknowledge Bit
Fal l Time of SCL Signal t
Rise Time of SDA Signal t
Fal l Time of SDA Signal t
Setup Time for STOP Condition tSU,
Capacitive Load for Each Bu s Line CB 400 pF
Pulse Width of Spike Suppressed tSP (Notes 11 and 14) 0 10 ns
PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS
t
Measured from 0.3VDD - 0.7VDD 20 160 ns
RCL1
Measured from 0.3VDD - 0.7VDD 20 80 ns
FCL
Measured from 0.3VDD - 0.7VDD 20 160 ns
RDA
Measured from 0.3VDD - 0.7V
FDA
160 ns
STO
(Note 12) 20 160 ns
DD
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FSFS
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N
⎤
2
⎥
×
⎤
⎦
V
REF
⎥
⎦
N
⎤
2
⎥
×
⎤
⎦
V
REF
⎥
⎦
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package