Rainbow Electronics MAX1127 User Manual

General Description

The MAX1127 quad, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. The MAX1127 operates from a 1.7V to

1.9V single supply and consumes only 563mW while delivering a 69.6dB signal-to-noise ratio (SNR) at a

19.3MHz input frequency. In addition to low operating power, the MAX1127 features a 675µA power-down mode for idle periods.

An internal 1.24V precision bandgap reference sets the ADC’s full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range.

A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phaselocked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock.

The MAX1127 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two’s complement or binary format.

Refer to the MAX1126 data sheet for a pin-compatible 40Msps version of the MAX1127.

The MAX1127 is available in a small, 10mm x 10mm x

0.9mm, 68-pin QFN package with exposed paddle and is specified for the extended industrial (-40°C to +85°C) temperature range.

Applications

Ultrasound and Medical Imaging Positron Emission Tomography (PET) Imaging Multichannel Communication Systems Instrumentation

Features

♦ Four ADC Channels with Serial LVDS/SLVS

Outputs

♦ Excellent Dynamic Performance

69.6dB SNR at fIN= 19.3MHz 92dBc SFDR at fIN= 19.3MHz

-87dB Channel Isolation

♦ Ultra-Low Power

135mW per Channel (Normal Operation)

1.2mW Total (Shutdown Mode)

♦ Accepts 20% to 80% Clock Duty Cycle ♦ Self-Aligning Data-Clock to Data-Output Interface ♦ Fully Differential Analog Inputs ♦ Wide ±1.4V

P-P

Differential Input Voltage Range

♦ Internal/External Reference Option ♦ Test Mode for Digital Signal Integrity ♦ LVDS Outputs Support Up to 30in FR-4 Backplane

Connections

♦ Small, 68-Pin QFN with Exposed Paddle ♦ Evaluation Kit Available (MAX1127EVKIT)

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3144; Rev 1; 3/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1127EGK -40°C to +85°C

68 QFN 10mm x x 10mm x 0.9mm

35 OUT3N

36 OUT3P

37 OV

DD

38 OUT2N

39 OUT2P

40 OV

DD

41 FRAMEN

42

FRAMEP

43

OV

DD

44

CLKOUTN

45 CLKOUTP

46 OV

DD

47 OUT1N

48 OUT1P

49 OV

DD

50 OUT0N

51 OUT0P

52

OV

DD

53

PD054PD155PD256PD357PDALL58AV

DD

59

AV

DD

60

AV

DD

61

AV

DD

62

AV

DD

6364

LVDSTEST

65

GND66REFIO

6768

GND

1GND

2IN0P

3IN0N

4GND

5IN1P

6IN1N

7GND

8AV

DD

9AV

DD

10AV

DD

11GND

12IN2P

13IN2N

14GND

15IN3P

16IN3N

17GND

18

AV

DD

19

I.C.

20

AV

DD

21

CV

DD

22

GND

23

CLK

24

GND

25

AV

DD

26

AV

DD

27

AV

DD

28DT29 30

PLL031PLL132PLL233PLL3

34

OV

DD

SLVS/LVDS

INTREF

T/B

MAX1127

QFN

10mm x 10mm x 0.9mm

EP

Pin Configuration

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto GND.........................................................-0.3V to +2.0V

CV

DD

to GND ........................................................-0.3V to +3.6V

OV

DD

to GND ........................................................-0.3V to +2.0V

IN_P, IN_N to GND...................................-0.3V to (AV

DD

+ 0.3V)

CLK to GND.............................................-0.3V to (CV

DD

+ 0.3V)

OUT_P, OUT_N, FRAME_,

CLKOUT_ to GND................................-0.3V to (OV

DD

+ 0.3V)

DT, SLVS/LVDS to GND...........................-0.3V to (AV

DD

+ 0.3V)

PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV

DD

+ 0.3V)

PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV

DD

+ 0.3V)

T/B, LVDSTEST to GND ...........................-0.3V to (AV

DD

+ 0.3V)

REFIO, INTREF to GND............................-0.3V to (AV

DD

+ 0.3V)

I.C. to GND...............................................-0.3V to (AV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C) 68-Pin QFN 10mm x 10mm x 0.9mm

(derated 41.7mW/°C above +70°C)........................3333.3mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature Range (soldering, 10s)......................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution N 12 Bits Integral Nonlinearity INL (Note 2)

LSB

Differential Nonlinearity DNL (Note 2)

LSB Offset Error Gain Error

ANALOG INPUTS (IN_P, IN_N)

Input Differential Range V

ID

Differential input 1.4

Common-Mode Voltage Range V

CMO

(Note 3)

V

Differential Input Impedance R

IN

Switched capacitor load 2 kΩ

Differential Input Capacitance C

IN

pF

CONVERSION RATE

Maximum Conversion Rate f

SMAX

65

Minimum Conversion Rate f

SMIN

16

Data Latency 6.5

DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)

fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C

Signal-to-Noise Ratio (Note 2) SNR

f

IN

= 30.3MHz at -0.5dBFS

dB

fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C

Signal-to-Noise and Distortion (First Four Harmonics) (Note 2)

SINAD

f

IN

= 30.3MHz at -0.5dBFS

dB

fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C

Effective Number of Bits (Note 2)

ENOB

f

IN

= 30.3MHz at -0.5dBFS

Bits

Fixed external reference (Note 2) ±1 Fixed external reference (Note 2) ±1.5

±0.4

±0.25

% FS % FS

66.6 69.6

66.5 69.5

0.75

12.5

69.7

69.4

69.6

69.3

11.4

11.3

V

P-P

MHz MHz

Cycles

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C

92

Spurious-Free Dynamic Range (Note 2)

SFDR

f

IN

= 30.3MHz at -0.5dBFS

dBc

fIN = 5.3MHz at -0.5dBFS -91 fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C -91

Total H ar m oni c D i stor ti on ( N ote 2)

THD

f

IN

= 30.3MHz at -0.5dBFS -88

dBc

Inter m od ul ati on D i stor ti on IMD

f

1

= 12.348685MHz at -6.5dBFS,

f

2

= 13.650845MHz at -6.5dBFS ( N ote 2)

dBc

Third-Order Intermodulation IM3 (Note 2)

dBc

Aperture Jitter t

AJ

(Note 2)

ps

RMS

Aperture Delay t

AD

(Note 2) 1 ns

Small-Signal Bandwidth SSBW Input at -20dBFS (Notes 2 and 4)

MHz

Full-Power Bandwidth LSBW Input at -0.5dBFS (Notes 2 and 4)

MHz

Output Noise INP = IN_N

LSB

RMS

Overdrive Recovery Time t

OR

RS = 25Ω, CS = 50pF 1

Clock

cycles

INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1µF)

INTREF Internal Reference Mode Enable Voltage

(Note 5) 0.1 V

INTREF Low-Leakage Current

µA

REFIO Output Voltage V

REFIO

V

Reference Temperature Coefficient

ppm/°C

EXTERNAL REFERENCE (INTREF = AVDD)

INTREF External Reference Mode Enable Voltage

(Note 5)

AV

DD

V

INTREF High-Leakage Current

µA

REFIO Input Voltage Range

V

REFIO Input Current I

REFIO

<1 µA

CLOCK INPUT (CLK)

Input High Voltage V

CLKH

0.8 x V

Input Low Voltage V

CLKL

0.2 x V

Clock Duty Cycle 50 % Clock Duty-Cycle Tolerance

%

SYMBOL

TC

REFIO

MIN TYP MAX

77.5

1.18 1.24 1.30

93.3

88.9

91.2

95.7

<0.4

100 100

0.35

200

100

-77.5

0.1V 200

1.24

CV

DD

±30

CV

DD

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

Input at GND 5

Input Leakage DI

IN

Input at AV

DD

80

µA

Input Capacitance DC

IN

5pF

DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)

Input High Threshold V

IH

0.8 x V

Input Low Threshold V

IL

0.2 x V

Input at GND, except PLL2 and PLL3 5 Input at AVDD, except PLL2 and PLL3 80Input Leakage DI

IN

PLL2 and PLL3 only 200

µA

Input Capacitance DC

IN

5pF

LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0)

Differential Output Voltage

R

TERM

= 100Ω

450 mV

Output Common-Mode Voltage V

OCM

R

TERM

= 100Ω

V

Rise Time (20% to 80%) t

R

TERM

= 100Ω, C

LOAD

= 5pF

ps

Fall Time (80% to 20%) t

F

R

TERM

= 100Ω, C

LOAD

= 5pF

ps

SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1

Differential Output Voltage

R

TERM

= 100Ω

mV

Output Common-Mode Voltage V

OCM

R

TERM

= 100Ω

mV

Rise Time (20% to 80%) t

R

TERM

= 100Ω, C

LOAD

= 5pF

ps

Fall Time (80% to 20%) t

F

R

TERM

= 100Ω, C

LOAD

= 5pF

ps

POWER-DOWN

PD Fall to Output Enable

µs

PD Rise to Output Disable

10 ns

POWER REQUIREMENTS

AVDD Supply Voltage AV

DD

1.7 1.8 1.9 V

OVDD Supply Voltage OV

DD

1.7 1.8 1.9 V

CVDD Supply Voltage CV

DD

1.7 1.8 3.6 V

SYMBOL

MIN TYP MAX UNITS

AV

DD

AV

DD

V

OHDIFF

V

OHDIFF

t

ENABLE

t

DISABLE

250

1.125 1.375 150 150

240 220 120 120

132

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

PDALL = 0, all channels active

295

PDALL = 0, all channels active, DT = 1

82 23

mA

AVDD Supply Current I

AVDD

f

IN

=

-0.5dBFS

PDALL = 1, global power down, PD[3:0] =1111, no clock input

µA

PDALL = 0, all channels active

56 65

PDALL = 0, all channels active, DT = 1

72

42 37

mA

OVDD Supply Current I

OVDD

f

IN

=

-0.5dBFS

PDALL = 1, global powerdown, PD[3:0] =1111, no clock input

µA

CVDD Supply Current I

CVDD

CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2

0mA

Power Dissipation P

DISSfIN

= 19.3MHz at -0.5dBFS

648 mW

TIMING CHARACTERISTICS (Note 6)

Data Valid to CLKOUT Rise/Fall t

OD

f

CLK

= 65MHz, Figure 5 (Notes 6 and 7)

24)

t

SAMPLE

/

24

(t

SAMPLE

/

24)

ns

CLKOUT Output Width High t

CH

Figure 5

12

ns

CLKOUT Output Width Low t

CL

Figure 5

12

ns

FRAME Rise to CLKOUT Rise t

CF

Figure 4 (Note 7)

24)

t

SAMPLE

/

24

( t

SAMPLE

/

24)

ns

Sample CLK Rise to Frame Rise t

SF

Figure 4 (Notes 7 and 8)

2)

(t

SAMPLE

/

2)

(t

SAMPLE

/

2)

ns

SYMBOL

19.3MHz at

PDALL = 0, 1 channel active PDALL = 0, PD[3:0] = 1111

MIN TYP MAX

257

300

375

(t

SAMPLE

- 0.15

(t

SAMPLE

- 0.15

(t

SAMPLE

+0.9

563

/

t

S AMP LE

t

S AMP LE

/

+1.3

+ 0.15

/

+ 0.15

+1.7

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs

6 _______________________________________________________________________________________

Note 1: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 2: See definition in the

Parameter Definitions section.

Note 3: The MAX1127 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be

overdriven to between 0.55V and 0.85V.

Note 4: Limited by MAX1127EVKIT input circuitry. Note 5: Connect INTREF to GND directly to enable internal reference mode. Connect INTREF to AV

DD

directly to disable the internal

bandgap reference and enable external reference mode.

Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 7: Guaranteed by design and characterization. Not subject to production testing. Note 8: Sample CLK rise to FRAME rise timing is measured from 50% of sample clock input level to 50% of FRAME output level.

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CHANNEL-TO-CHANNEL MATCHING

Crosstalk (Note 2) -87 dB Gain Matching fIN = 30.3MHz (Note 2)

dB

Phase Matching fIN = 30.3.MHz (Note 2) ±1

Degrees

±0.1

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 7

FFT PLOT

(32,768-POINT DATA RECORD)

MAX1127 toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-110

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-120 032

f

CLK

= 65.04448MHz

f

IN

= 5.301935MHz

A

IN

= -0.5dBFS SNR = 69.5dB SINAD = 69.47dB THD = -90.94dBc SFDR = 93.27dBc

HD2

HD3

FFT PLOT

(32,768-POINT DATA RECORD)

MAX1127toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-110

HD3

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-120 032

f

CLK

= 65.04448MHz

f

IN

= 30.30301MHz

A

IN

= -0.5dBFS SNR = 69.45dB SINAD = 69.4dB THD = -89.3dBc SFDR = 89.7dBc

HD2

CROSSTALK

(4096-POINT DATA RECORD)

MAX1127 toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-110 032

MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 0. f

IN(IN1)

= 5.3489349MHz

f

IN(IN0)

= 30.2683055MHz

CROSSTALK

(4096-POINT DATA RECORD)

MAX1127 toc04

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-110 032

MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2. f

IN(IN1)

= 5.3489349MHz

f

IN(IN2)

= 30.2683055MHz

CROSSTALK

(4096-POINT DATA RECORD)

MAX1127 toc05

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-110 032

MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 3. f

IN(IN1)

= 5.3489349MHz

f

IN(IN3)

= 30.2683055MHz

TWO-TONE INTERMODULATION DISTORTION

(32,768-POINT DATA RECORD)

MAX1127 toc06

FREQUENCY (MHz)

AMPLITUDE (dBFS)

284 8 12 2016 24

-110

-90

-100

-80

-70

-50

-30

-10

-60

-40

-20

0

-120 032

f

IN(IN1)

= 12.348685MHz

f

IN(IN2)

= 13.650845MHz

A

IN1

= -6.5dBFS

A

IN2

= -6.5dBFS IMD = 91.2dBc IM3 = 95.7dBc

1

-7 1 100 1000

GAIN BANDWIDTH PLOT

-5

-6

-4

-3

-2

-1

0

MAX1127 toc07

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

10

SMALL-SIGNAL BANDWIDTH

-20dBFS

FULL-POWER BANDWIDTH

-0.5dBFS

LIMITED BY MAX1127EVKIT INPUT CIRCUITRY

Typical Operating Characteristics

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs

8 _______________________________________________________________________________________

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

SNR (dB)

1008020 40 60

63

64

65

67

69

66

68

70

71

MAX1127 toc08

72

62

0 120

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

SINAD (dB)

1008020 40 60

63

64

65

67

69

66

68

70

71

MAX1127 toc09

72

62

0 120

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

THD (dBc)

1008020 40 60

-95

-90

-85

-75

-70

-80

-65

-60

MAX1127 toc10

-55

-100 0 120

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

SFDR (dBc)

1008020 40 60

60

65

70

80

85

75

90

95

MAX1127 toc11

100

55

0 120

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, INTREF = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)