Page 1
General Description
The MAX1121 is a monolithic 8-bit, 250Msps analog-todigital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
Applications
Wireless and Wired Broadband Communication
Digital Oscilloscopes
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Instrumentation
Features
♦ 250Msps Conversion Rate
♦ SNR = 48.8dB/48.7dB at fIN= 100MHz/500MHz
♦ SFDR = 68dBc/63.8dBc at f
IN
= 100MHz/500MHz
♦ Single 1.8V Supply
♦ 477mW Power Dissipation at 250Msps
♦ On-Chip Track-and-Hold and Internal Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ Evaluation Kit Available (Order MAX1124EVKIT)
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
________________________________________________________________ Maxim Integrated Products 1
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
AV
CC
AGND
AV
CC
TOP VIEW
AVCCOGND
OVCCORP
ORN
D7P
D7N
D6P
D6N
5253
D5P
D5N
AGND
AGND
AV
CC
CLKN
CLKP
AV
CC
AGND
OV
CC
OGND
N.C.
OV
CC
N.C.
N.C.
N.C.
D2P
D2N
OGND
OV
CC
DCLKP
DCLKN
OV
CC
D1P
D1N
D0P
35
36
37
D0N
N.C.
N.C.
AGND
INN
INP
AGND
AV
CC
AGND
AGND
AV
CC
AV
CC
AV
CC
AGND
REFADJ
REFIO
AGND
48 D3N
AV
CC
64
AGND
656667
AGND
AGND
AV
CC
68
T/B
2322212019 2726252418 2928 323130
N.C.
N.C.
3433
49
50
D4N
D3P
51 D4P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
CLKDIV 17
MAX1121
EP
Pin Configuration
Ordering Information
19-3077; Rev 1; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX1121EGK -40°C to +85°C 68 QFN-EP*
*EP = Exposed paddle.
Page 2
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OVCC.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
CC
+ 0.3V)
Digital Inputs to AGND.............................-0.3V to (AV
CC
+ 0.3V)
REF, REFADJ to AGND............................-0.3V to (AV
CC
+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OV
CC
+ 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into Any Pin............................................50mA
ELECTRICAL CHARACTERISTICS
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥25°C guar-
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity INL (Note 1) -0.6
LSB
Differential Nonlinearity DNL No missing codes (Note 1) -0.9
LSB
Transfer Curve Offset V
OS
(Note 1) -10 +10 LSB
Offset Temperature Drift ±20
µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range V
FS
(Note 1)
mV
P-P
Full-Scale Range Temperature
Drift
130
ppm/°C
Common-Mode Input Range V
CM
V
Input Capacitance C
IN
3pF
Differential Input Resistance R
IN
4.4 6.5 kΩ
Full-Power Analog Bandwidth FPBW Figure 8 600
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage V
REFIO
V
Reference Temperature Drift 90
ppm/°C
REFADJ Input High Voltage
Used to disable the internal reference
AV
CC
-
0.3
V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
250
MHz
Minimum Sampling Rate
20
MHz
±0.2 +0.6
±0.1 +0.9
1100 1250 1375
V
REFADJ
f
SAMPLE
f
SAMPLE
1.38
±0.18
3.00
1.18 1.24 1.30
Page 3
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥25°C guar-
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS MIN
UNITS
Clock Duty Cycle Set by clock management circuit
%
Aperture Delay t
AD
350 ps
Aperture Jitter t
AJ
0.2
ps
RMS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 2) 200 500
mV
P-P
Clock Input Common-Mode
Voltage Range
1.25
V
Clock Differential Input
Resistance
R
CLK
11
kΩ
Clock Differential Input
Capacitance
C
CLK
5pF
DYNAMIC CHARACTERISTICS (at -0.5dBFS)
fIN = 10MHz, TA ≥ +25°C
fIN = 100MHz, TA ≥ +25°C
fIN = 180MHz
Signal-to-Noise Ratio SNR
f
IN
= 500MHz
dB
fIN = 10MHz, TA ≥ +25°C
fIN = 100MHz, TA ≥ +25°C
fIN = 180MHz
Signal-to-Noise
and Distortion
SINAD
f
IN
= 500MHz
dB
fIN = 10MHz, TA ≥ +25°C6069
fIN = 100MHz, TA ≥ +25°C5968
fIN = 180MHz
Spurious-Free
Dynamic Range
SFDR
f
IN
= 500MHz
dBc
fIN = 10MHz
fIN = 100MHz
fIN = 180MHz
Worst Harmonics
(HD2 or HD3)
f
IN
= 500MHz
dBc
IMD
100
f
IN1
= 99MHz at -7dBFS,
f
IN2
= 101MHz at -7dBFS
-70
Two-Tone Intermodulation
Distortion
IMD
500
f
IN1
= 498.5MHz at -7dBFS,
f
IN2
= 502.5MHz at -7dBFS
-56
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D7P/N, DCLKP/N)
Differential Output Voltage |VOD| 250 400 mV
SYMBOL
47.2 48.9
46.2 48.8
47.1 48.8
46.1 48.7
TYP MAX
40 to 60
±0.25
±25%
48.8
48.7
48.7
48.6
69.1
63.8
-74.6
-68.4
-69.1
-63.8
Page 4
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥25°C guar-
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
Output Offset Voltage OV
OS
V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low V
IL
0.2 x
V
Digital Input Voltage High V
IH
0.8 x
V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay t
PDL
Figure 4 1.5 ns
CLK to DCLK Propagation Delay
t
CPDL
Figure 4
ns
Data Valid to DCLK Rising Edge
t
CPDL
-
t
PDL
Figure 4 (Note 2)
ns
LVDS Output Rise-Time t
RISE
20% to 80%, CL = 5pF
ps
LVDS Output Fall-Time t
FALL
20% to 80%, CL = 5pF
ps
Output Data Pipeline Delay
8
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AV
CC
V
Digital Supply Voltage Range OV
CC
V
Analog Supply Current
I
AVCCfIN
= 100MHz
mA
Digital Supply Current I
OVCCfIN
= 100MHz 45 75 mA
Analog Power Dissipation P
DISSfIN
= 100MHz
mW
Offset 1.6
mV/V
Power-Supply Rejection Ratio
(Note 3)
PSRR
Gain 1.9
%FS/V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
SYMBOL
MIN TYP MAX
1.125 1.310
AV
CC
AV
CC
2.85
0.92 1.35 1.86
460
460
t
LATENCY
1.70 1.80 1.90
1.70 1.80 1.90
220 290
477 657
Page 5
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 5
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1121 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
040608020 100 140120
f
SAMPLE
= 250.0057MHz
f
IN
= 11.5054MHz
A
IN
= -0.4885MHz
SNR = 48.9dB
SFDR = 71.5dBc
HD2 = -79.2dBc
HD3 = -74.6dBc
HD2
HD3
-90
-80
-60
-70
-40
-50
-30
-10
-20
0
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1121 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
040608020 100 140120
f
SAMPLE
= 250.0057MHz
f
IN
= 60.0294MHz
A
IN
= -0.4885MHz
SNR = 49dB
SFDR = 71.1dBc
HD2 = -79.5dBc
HD3 = -71.9dBc
HD2
HD3
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
040608020 100 140120
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1121 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f
SAMPLE
= 250.0057MHz
f
IN
= 183.5064MHz
A
IN
= -0.5245MHz
SNR = 48.8dB
SFDR = 69.1dBc
HD2 = -77.2dBc
HD3 = -69.1dBc
HD2
HD3
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1121 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
040608020 100 140120
HD3
HD2
f
SAMLE
= 250.0057MHz
f
IN
= 500.516MHz
A
IN
= -0.5235MHz
SNR = 48.8dB
SFDR = 63.8dBc
HD2 = -70.8dBc
HD3 = -63.8dBc
FUNDAMENTAL
SNR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250.0057MHz, AIN = -0.5dBFS)
MAX1121 toc05
f
IN
(MHz)
SNR (dB)
400300200100
46
49
47
48
50
45
0500
SFDR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250.0057MHz, AIN = -0.5dBFS)
MAX1121 toc06
f
IN
(MHz)
SFDR (dBc)
400300200100
62
56
68
74
80
50
0500
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250.0057MHz, AIN = -0.5dBFS)
MAX1121 toc07
f
IN
(MHz)
HD2/HD3 (dBc)
400300200100
-90
-80
-70
-60
-50
-100
0500
HD3
HD2
20
30
25
40
35
45
50
-30 -15 -10-25 -20 -5 0
SNR vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 250.0057MHz, fIN = 60.0294MHz)
MAX1121 toc08
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB)
30
50
40
45
35
65
60
55
70
75
-30 -15 -10-25 -20 -5 0
SFDR vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 250.0057MHz, fIN = 60.0294MHz)
MAX1121 toc09
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)
Typical Operating Characteristics
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
Page 6
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
6 _______________________________________________________________________________________
-90
-65
-75
-85
-70
-80
-50
-55
-60
-40
-45
-35
-30
-30 -20 -15-25 -10 -5 0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 250.0057MHz, fIN = 60.0294MHz)
MAX1121 toc10
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
HD3
HD2
SNR vs. f
SAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1121 toc11
f
SAMPLE
(MHz)
SNR (dB)
60
47.0
47.5
48.0
48.5
49.0
46.5
20 260180140100 220
SFDR vs. f
SAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1121 toc12
f
SAMPLE
(MHz)
SFDR (dBc)
22014010060
50
60
70
80
90
40
20 260180
HD2/HD3 vs. f
SAMPLE
(fIN = 60.03294MHz, AIN = -0.5dBFS)
MAX1121 toc13
f
SAMPLE
(MHz)
HD2/HD3 (dBc)
22018014010060
-92
-84
-76
-68
-60
-100
20 260
HD3
HD2
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
MAX1121 toc14
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
040608020 100 140120
f
SAMPLE
= 250.0057MHz
f
IN1
= 99.0318MHz
f
IN2
= 101.046MHz
A
IN1
= A
IN2
= -7dBFS
IMD = -70dBc
2f
IN1
- f
IN2
2f
IN2
-
f
IN1
f
IN1
f
IN2
-0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
64 96320 128 160 192 224 256
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1121 toc15
DIGITAL OUTPUT CODE
INL (LSB)
-0.5
-0.4
-0.2
0.1
0.3
0.5
0.4
0
-0.3
-0.1
0.2
64 96320128160 192 224 256
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1121 toc16
DIGITAL OUTPUT CODE
DNL (LSB)
2
0
-2
-4
-6
-8
-10
-12
10 100 1000
GAIN BANDWIDTH PLOT
(f
SAMPLE
= 250.0057MHz, AIN = -0.5dBFS)
MAX1121 toc17
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
SNR vs. TEMPERATURE (fIN = 65.0108MHz,
f
SAMPLE
= 249.856MHz, AIN = -0.5dBFS)
MAX1121 toc18
TEMPERATURE (°C)
SNR (dB)
603510-15
47.0
46.5
48.0
47.5
49.0
48.5
49.5
50.0
46.0
-40 85
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
Page 7
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 7
SINAD vs. TEMPERATURE (fIN = 65.0108MHz,
f
SAMPLE
= 249.856MHz, AIN = -0.5dBFS)
TEMPERATURE (°C)
SINAD (dB)
603510-15
50.0
49.5
49.0
48.5
48.0
47.5
47.0
46.5
46.0
-40 85
MAX1121 toc19
SFDR vs. TEMPERATURE (fIN = 65.0108MHz,
f
SAMPLE
= 249.856MHz, AIN = -0.5dBFS)
TEMPERATURE (°C)
SFDR (dBc)
603510-15
55
60
65
70
MAX1121 toc20
75
50
-40 85
POWER DISSIPATION vs. f
SAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
f
SAMPLE
(MHz)
P
DISS
(mW)
18014010060
420
410
440
430
460
450
470
480
490
400
20 260220
MAX1121 toc21
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
FIGURE 6
FS VOLTAGE vs. FS ADJUST RESISTOR
MAX1121 toc22
FS ADJUST RESISTOR (Ω)
V
FS
(V)
900800600 700200 300 400 500100
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.16
0 1000
SNR vs. SUPPLY VOLTAGE
(f
IN
= 60.0294MHz, AIN = -0.5dBFS)
SUPPLY VOLTAGE (V)
SNR
(dB)
2.01.91.81.71.6
MAX1121 toc23
50
49
48
47
46
45
44
43
1.5 2.1
AVCC = OV
CC
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(f
SAMPLE
= 250.0057MHz)
MAX1121 toc24
SUPPLY VOLTAGE (V)
V
REFIO
(V)
2.01.91.81.71.6
1.2310
1.2320
1.2330
1.2340
1.2350
1.2300
1.5 2.1
MEASURED AT THE REFIO PIN
REFADJ = AV
CC
= OV
CC
0.0E+00
4.0E+04
1.2E+05
8.0E+04
1.6E+05
2.0E+05
126 127 128
NOISE HISTOGRAM
(DC INPUT, 256k-POINT DATA RECORD)
DIGITAL OUTPUT NOISE
CODE COUNTS
0
0
MAX1121 toc25
f
SAMPLE
= 250MHz
131072
t
CPDL
t
PDL
PROPAGATION DELAY TIMES
vs. TEMPERATURE
MAX1121 toc26
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
603510-15
1
2
3
4
5
6
0
-40 85
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
46.0
49.5
48.5
48.0
49.0
47.0
46.5
47.5
50.0
10 40 5020 30 60 70 80 90
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.8148MHz,
f
SAMPLE
= 249.856MHz, AIN = -0.5dBFS)
CLOCK DUTY CYCLE (%)
SINAD (dB)
MAX1121 toc27
Page 8
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
AV
CC
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
AGND Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND.
3 REFIO
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
an external reference source to be connected to the MAX1121. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
4 REFADJ
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AV
CC
through a 1kΩ resistor, the
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
8 INP Positive Analog Input Terminal
9INN Negative Analog Input Terminal
17 CLKDIV
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
22 CLKP
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
23 CLKN
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60
OV
CC
Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
29–36 N.C. No Connection. Do not connect to these pins.
37 D0N Complementary Output Bit 0 (LSB)
38 D0P True Output Bit 0 (LSB)
39 D1N Complementary Output Bit 1
40 D1P True Output Bit 1
42 DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKN and DCLKN.
43 DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP
and DCLKP.
46 D2N Complementary Output Bit 2
47 D2P True Output Bit 2
48 D3N Complementary Output Bit 3
49 D3P True Output Bit 3
Page 9
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
50 D4N Complementary Output Bit 4
51 D4P True Output Bit 4
52 D5N Complementary Output Bit 5
53 D5P True Output Bit 5
54 D6N Complementary Output Bit 6
55 D6P True Output Bit 6
56 D7N Complementary Output Bit 7
57 D7P True Output Bit 7
58 ORN
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59 ORP
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.
68 T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1121. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
T/B = 1: Binary output format
Figure 1. MAX1121 Block Diagram
CLKDIV
CLKP
CLKN
INP
INN
COMMON-MODE
BUFFER
2.2kΩ2.2kΩ
CLOCKDIVIDER
CONTROL
INPUT
BUFFER
CLOCK
MANAGEMENT
T/H
REFERENCE
REFIO
REFADJ
8-BIT PIPELINE
QUANTIZER CORE
MAX1121
LVD S
DATA PORT
DCLKP
DCLKN
D0P/N–D7P/N
8
ORP
ORN
Page 10
MAX1121
Detailed Description—
Theory of Operation
The MAX1121 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a commonmode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typical differential full-scale signal swing of 1.25V
P-P
.
INP and INN are buffered prior to entering each trackand-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 8-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital correction logic to generate the final output code. The result
is a 8-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDScompatible output levels. See Figure 1 for a more
detailed view of the MAX1121 architecture.
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1121. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1121 analog inputs are self-
biased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25V
P-P
. Both inputs
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recommended to drive the analog inputs of the MAX1121 in
AC-coupled configuration to achieve best dynamic performance. See the AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
On-Chip Reference Circuit
The MAX1121 features an internal 1.23V bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the fullscale range of the MAX1121. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1121
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2V
P-P
to 1.0V
P-P
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
10 ______________________________________________________________________________________
AV
CC
AGND
INN
INP
TO COMMON-MODE INPUT
2.2kΩ
TO COMMON-MODE INPUT
2.2kΩ
Figure 2. Simplified Analog Input Architecture
REFERENCE
BUFFER
REFIO
REFADJ
AV
CC
AV
CC
/ 2
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
ADC FULL-SCALE = REFT - REFB
G
1V
1kΩ
0.1µF
REFERENCE
SCALING
AMPLIFIER
REFT
REFB
Figure 3. Simplified Reference Architecture
Page 11
and are usually driven in AC-coupled configuration.
See the Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1121 also features an internal clock management circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications.
Clock Outputs (DCLKP, DCLKN)
The MAX1121 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
______________________________________________________________________________________ 11
INP
INN
D0P/N–D7P/N
ORP/N
CLKP
CLKN
t
CH
t
CL
DCLKP
DCLKN
N - 8 N - 7 N N + 1
t
PDL
N - 7N - 8 N N + 1
NN + 1 N + 8 N + 9
t
CPDL
t
LATENCY
t
AD
N - 1
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
t
CPDL
- t
PDL
t
CPDL
- t
PDL
~ 0.4 x t
SAMPLE
with t
SAMPLE
= 1 / f
SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
OV
CC
OGND
2.2kΩ 2.2kΩ
V
OP
V
ON
Figure 5. Simplified LVDS Output Architecture
Page 12
MAX1121
Divide-by-2 Clock Control (CLKDIV)
The MAX1121 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the converter’s sampling rate. Connecting CLKDIV to OV
CC
allows data to be updated at the speed of the ADC input
clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1121 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of nine clock cycles.
Digital Outputs (D0P/N–D7P/N, DCLKP/N,
ORP/N) and Control Input
T
/B
The digital outputs D0P/N–D7P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D7P/N is presented in either binary or two’s complement format (Table
1). The T/B control line is an LVCMOS-compatible input,
which allows the user to select the desired output format. Pulling T/B low outputs data in two’s complement
and pulling it high presents data in offset binary format
on the 10-bit parallel bus. T/B has an internal pulldown
resistor and may be left unconnected in applications
using only two’s complement output format. All LVDS
outputs provide a typical voltage swing of 0.4V around
a common-mode voltage of approximately 1.2V, and
must be terminated at the far end of each transmission
line pair (true and complementary) with 100Ω. The
LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V.
The MAX1121 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
12 ______________________________________________________________________________________
INP ANALOG
VOLTAGE LEVEL
INN ANALOG
VOLTAGE LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY
DIGITAL OUTPUT CODE
(D7–D0)
TWO’S COMPLEMENT
DIGITAL OUTPUT CODE
(D7–D0)
> VCM + 0.3125V < VCM - 0.3125V 1 (0)
1111 1111
(exceeds positive full scale,
OR set)
0111 1111
(exceeds positive full scale,
OR set)
VCM + 0.3125V VCM - 0.3125V 0 (1)
1111 1111
(represents positive full
scale)
0111 1111
(represents positive full
scale)
V
CM
V
CM
0 (1)
1000 0000 or
0111 1111
(represents midscale)
0000 0000 or
1111 1111
(represents midscale)
V
CM
- 0.3125V VCM + 0.3125V 0 (1)
0000 0000
(represents negative full
scale)
1000 0000
(represents negative full
scale)
< VCM - 0.3125V > V
CM
+ 0.3125V 1 (0)
0000 0000
(exceeds negative full scale,
OR set)
1000 0000
(exceeds negative full scale,
OR set)
Table 1. MAX1121 Digital Output Coding
Page 13
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1121 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or
predetermined resistor value between REFADJ and
REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations
and their impact on the overall full-scale range adjustment of the MAX1121. Do not use resistor values of less
than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference.
Differential, AC-Coupled, PECL-Compatible
Clock Input
The preferred method of clocking the MAX1121 is differentially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 7).
The receiver produces the necessary PECL output levels
to drive the clock inputs of the data converter.
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________ 13
REFERENCE
BUFFER
REFIO
REFADJ
AV
CCAVCC
/ 2
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
ADC FULL-SCALE = REFT - REFB
G
1V
0.1µF
REFERENCE-
SCALING
AMPLIFIER
REFT
REFB
13kΩ
TO 1MΩ
13kΩ
TO 1MΩ
MAX1121
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
MAX1121
50Ω
CLKPCLKN
SINGLE-ENDED
INPUT TERMINAL
MC100LVEL16
510Ω510Ω
150Ω
150Ω
V
CLK
VGND
2
3
45
6
7
8
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
8
D0P/N–D7P/N
AV
CCOVCC
AGND OGND
INP
INN
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
Page 14
MAX1121
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differential signal, required by the MAX1121 for optimum
dynamic performance. In general, the MAX1121 provides the best SFDR and THD with fully differential
input signals and it is not recommended to drive the
ADC inputs in single-ended configuration. In differential
input mode, even-order harmonics are usually lower
since INP and INN are balanced, and each of the ADC
inputs only requires half the signal swing compared to
a single-ended configuration.
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating
the transformer in this fashion reduces the potential
effects of transformer parasitics. The source impedance
combined with the shunt capacitance provided by a PC
board and the ADC’s parasitic capacitance reduce the
combined bandwidth to approximately 550MHz.
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1121 can be
used in single-ended mode (Figure 9). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 50Ω resistor to
AGND. The negative input should be 25Ω reverse-terminated and AC grounded with a 0.1µF capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX1121 requires board layout design techniques
suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switching currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AV
CC
and
OVCC) where they enter the PC board with separate
networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1121.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
14 ______________________________________________________________________________________
MAX1121
8
D0P/N–D7P/N
AV
CC
OV
CC
AGND OGND
INP
INN
25Ω
25Ω
15Ω
15Ω
ADT1–1WT
0.1µF
0.1µF
SINGLE-ENDED
INPUT TERMINAL
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
MAX1121
8
D0P/N–D7P/N
AV
CC
OV
CC
AGND OGND
0.1µF
SINGLE-ENDED
INPUT TERMINAL
0.1µF
INP
INN
50Ω
25Ω
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
Page 15
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long distances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sections of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1121 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1121 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PC
board’s analog ground layer.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading (less
than 5pF) on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________ 15
MAX1121
8
D0P/N–D7P/N
AV
CC
OV
CC
AGND OGND
OGNDAGND
ANALOG POWERSUPPLY SOURCE
DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE
BYPASSING—ADC LEVEL
BYPASSING—BOARD LEVEL
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC.
1µF10µF47µF
AV
CC
0.1µF 0.1µF
1µF10µF47µF
OV
CC
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1121
Page 16
MAX1121
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1121 are measured using the histogram method with an input frequency of 10MHz.
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1121’s DNL specification is measured with the histogram method based on a 10MHz input tone.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02dBx N + 1.76
dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1121, SINAD
is computed from a curve fit.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -7dB full scale.
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
16 ______________________________________________________________________________________
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLKN
CLKP
Figure 11. Aperture Jitter/Delay Specifications
PART
RESOLUTION
(Bits)
SPEED GRADE
(Msps)
MAX1122 10 170
MAX1123 10 210
MAX1124 10 250
Pin-Compatible Higher
Resolution Versions
Page 17
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
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