Rainbow Electronics MAX11043 User Manual
General Description
The MAX11043 features 4 single-ended or differential
channels of simultaneous-sampling ADCs with 16-bit
resolution. The MAX11043 contains a versatile filter
block and programmable-gain amplifier (PGA) per
channel. The filter consists of seven cascaded 2ndorder filter sections for each channel, allowing the construction of a 14th-order filter. The filter coefficients are
user-programmable. Configure each 2nd-order filter as
lowpass (LP), highpass (HP), or bandpass (BP) with
optional rectification. Gain and phase mismatch of the
analog signal path is better than -50dB.
The ADC can sample up to 800ksps per channel. A
40MHz serial interface provides communication to and
from the device. The SPI™ interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or
2 channels at 800ksps per channel. A software-selectable scan mode allows reading the ADC results while
simultaneously updating the DAC. Other features of the
MAX11043 include an internal (+2.5V) or external
(+2.0V to +2.8V) reference, power-saving modes, and
a PGA with gains of 1 to 64. The PGA includes an
equalizer (EQ) function that automatically boosts lowamplitude, high-frequency signals for applications such
as CW-chirp radar.
The MAX11043 includes two 8-bit coarse DACs that set
the high and low references for a second-stage 12-bit
fine DAC, typically used for VCO control. Use software
controls to write to the DAC or step the DAC up and
down under hardware control in programmable steps.
The device operates from a +3.0V to +3.6V supply. The
MAX11043 is available in a 40-pin, 6mm x 6mm TQFN
package and operates over the extended -40°C to
+125°C temperature range.
Applications
Automotive Radar Systems
Data Acquisition Systems
Industrial Controls
Power-Grid Monitoring
Features
♦ 4 Single-Ended or Differential Channels of
Simultaneous-Sampling, 16-Bit ADCs
♦ ±10 LSB INL, ±1 LSB DNL, No Missing Codes
♦ 90dB SFDR, -86dB THD, 76dB SINAD,
77dB SNR at 100kHz Input
♦ PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for
Each Channel
♦ EQ Function Automatically Boosts
High-Frequency, Low-Amplitude Signals
♦ Seven-Stage Internal Programmable Biquad
Filters per Channel
♦ High Throughput, 400ksps per Channel for 4
Channels or 800ksps per Channel for 2 Channels
♦ Dual-Stage DAC
Two 8-Bit Coarse Reference DACs
12-Bit Fine DAC
♦ +2.5V Internal Reference or +2.0V to +2.8V
External Reference
♦ Single +3.3V Operation
♦ Shutdown and Power-Saving Modes
♦ 40-Pin, 6mm x 6mm TQFN Package
♦ -40°C to +125°C Operating Temperature
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
Ordering Information
19-4250; Rev 0; 8/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX11043ATL+
40 TQFN-EP*
+
Denotes a lead-free/RoHS-compliant package.
*
EP = Exposed pad.
SPI is a trademark of Motorola, Inc.
-40°C to +125°C
TOP VIEW
REFDACL
AOUT
AVDD
25
AGND
DGND
*EP
8910
DVDD
21
SHDN
20
19
18
17
16
15
14
13
12
11
OSCOUT
OSCIN
EOC
I.C.
SCLK
DIN
DOUT
CS
CONVRUN
DACSTEP
AINDN
AINDP
AGND
REFBP
AINCN
AINCP
REFC
REFB
AINBP
REFDACH
REFDAC
REFD
27282930 26 24 23 22
31
32
33
34
35
I.C.
36
37
38
39
40
12
+
4567
3
MAX11043
*CONNECT EP TO AGND.
AINBN
REFA
AVDD
AGND
DVDD
AINAN
AINAP
TQFN
DGND
DVREG
UP/DWN
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ....................................................-0.3V to +4.0V
DVDD to DGND .....................................................-0.3V to +4.0V
DVREG to DGND...................................................-0.3V to +3.0V
AGND to DGND.....................................................-0.3V to +0.3V
Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD,
AOUT, REFDAC, REFBP to AGND......-0.3V to (AVDD + 0.3V)
UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O,
OSCIN, OSCOUT to DGND ....................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin except AVDD, DVDD, DVREG,
AGND, DGND...............................................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
TQFN Multilayer Board
(derate 37mW/°C above +70°C)................................2963mW
TQFN Single-Layer Board
(derate 26.3mW/°C above +70°C)..........................2105.3mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
SIGMA-DELTA ADC
Resolution N 16 Bits
Integral Nonlinearity INL -16 ±2 LSB
Differential Nonlinearity DNL Guaranteed monotonic -1 +1 LSB
Offset Error OE -35 +35 mV
Offset-Error Drift ±30 µV/°C
Gain Error GE Trimmed with 150Ω/330pF anti-alias filter -1 +1 %
Gain Temperature Coefficient ±50 ppm/°C
Channel Gain-Error Matching Complete analog signal path -0.25 +0.25 %
Channel Offset Matching Complete analog signal path -60 +60 mV
DYNAMIC PERFORMANCE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input ADC modulator gain = 1 1.2 V
Input-Referred Noise Spectral
Density
Second Harmonic to
Fundamental
Third Harmonic to Fundamental -80 -110 dB
Spurious-Free Dynamic Range SFDR 77 102 dB
Channel-to-Channel Isolation
Channel Phase Matching
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
100kHz 85 nV/√Hz
Unused channels are shorted and
unconnected
Between all channels, including complete
analog signal path
-80 -93 dB
85 108 dB
-0.05 +0.05 Degrees
P-P
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
((V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 8 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input ADC modulator gain = 1 150 mV
Input-Referred Noise Spectral
Density
Second Harmonic to
Fundamental
Third Harmonic to Fundamental -94 dB
Spurious-Free Dynamic Range SFDR 100 dB
Channel-to-Channel Isolation
Channel Phase Matching
DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 16 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input ADC modulator gain = 1 75 mV
Input-Referred Noise Spectral
Density
Second Harmonic to
Fundamental
Third Harmonic to Fundamental -93 dB
Spurious-Free Dynamic Range SFDR 97 dB
Channel-to-Channel Isolation
Channel Phase Matching
DYNAMIC PERFORMANCE (EQ Mode (5kHz -1dB Full-Scale Signal, CONFIG_ Register Bit 3 = 1))
Maximum Full-Scale Input ADC modulator gain = 1 (Note 2) 800 mV
Input-Referred Noise Spectral
Density
Second Harmonic to
Fundamental
Third Harmonic to Fundamental -77 -98 dB
Spurious-Free Dynamic Range SFDR Input referred (Note 3) 80 89 dB
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
100kHz 20 nV/√Hz
Unused channels are shorted and
unconnected
Between all channels, including complete
analog signal path
100kHz 15 nV/√Hz
Unused channels are shorted and
unconnected
Between all channels, including complete
analog signal path
100kHz 6 nV/√Hz
-92 dB
110 dB
-0.05 +0.05 Degrees
-99 dB
106 dB
-0.075 +0.075 Degrees
-80 -90 dB
P-P
P-P
P-P
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
((V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
Channel-to-Channel Isolation
Channel Phase Matching
DYNAMIC PERFORMANCE (All Modes)
Conversion Rate
Minimum Throughput 5 ksps
Power-Supply Rejection Ratio DCPSRR 50 dB
ANALOG INPUTS (AINAP/AINAN, AINBP/AINBN, AINCP/AINCN, AINDP/AINDN)
Absolute Voltage Any Input (Note 4) 0 AVDD V
Input Impedance (Note 5)
Input Capacitance EQ mode only 50 pF
EQ FILTER (Analog and Digital)
Unity-Gain Frequency Default 5 kHz
Lower Transition Frequency Default, from 40dB/decade to 0dB/decade 190 kHz
Upper Transition Frequency Default, from 0dB/decade to -80dB/decade 205 kHz
LP FILTER
-3dB Corner Frequency Default 205 kHz
REFERENCE INPUT
REF_ Input Voltage Range V
Input Current 150 µA
REFBP Input Voltage Range V
Input Current 700 µA
REFDAC Input Voltage Range V
Input Resistance 17 kΩ
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFBP
REFDAC
REF_
Unused channels are shorted and
unconnected
Between all channels, including complete
analog signal path
All 4 channels 400
2 channels only 800
Direct input to ADC,
gain = 1
Direct input to ADC, gain = 2 7
Direct input to ADC, gain = 4 or 8 7
PGA gain = 16 5.5
DIFF = 1 25
DIFF = 0 100
80 104 dB
-0.12 +0.12 Degrees
2 2.5 2.8 V
2 2.5 2.8 V
1 1.25 1.4 V
ksps
kΩ
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
((V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFDAC_ Input Voltage Range V
REFDAC_
0 1.4 V
Input Resistance 150 kΩ
INTERNAL REFERENCE
Reference Voltage V
Reference Temperature
Coefficient
REFBP
2.45 2.5 2.55 V
100 ppm/°C
CRYSTAL OSCILLATOR (Max ESR 100Ω, 22pF Load Capacitors to DGND)
Maximum Crystal Operating
Frequency
External Clock Input Frequency
Range
Epson Electronics MA-505 (16MHz) 16 MHz
External clock applied to OSCIN 4 40 MHz
Stability Excluding crystal 25 ppm
Startup Time Epson Electronics MA-505 (16MHz) 10 ms
OSCIN Input Low Voltage When driven with external clock source
OSCIN Input High Voltage When driven with external clock source
0.7 x
DVDD
0.3 x
DVDD
OSCIN Leakage Current -5 +5 µA
DIGITAL INPUTS
Input High Voltage V
Input Low Voltage V
IH
IL
0.7 x
DVDD
0.3 x
DVDD
Input Hysterisis 15 mV
Input Leakage Current I
Input Capacitance C
IN
V
= 0 or DVDD -1 +1 µA
IN
IN
15 pF
DIGITAL OUTPUTS
DVDD
-
Output-Voltage High V
Output-Voltage Low V
OH
OL
I
I
= 0.8mA
SOURCE
= 1.6mA 0.4 V
SINK
0.6
Three-State Leakage Current DOUT only -1 +1 µA
Three-State Output Capacitance DOUT only 15 pF
VOLTAGE REGULATOR
Regulated Digital Supply Voltage DV
REG
Internal use only 2.5 V
POWER REQUIREMENTS
Analog Supply Voltage 3.0 3.6 V
Digital Supply Voltage 3.0 3.6 V
V
V
V
V
V
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
((V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
Analog Supply Current I
Digital Supply Current I
Shutdown Current
STATIC ACCURACY—FINE DAC (CL = 200pF, RL = 10kΩ)
Resolution 12 Bits
Integral Nonlinearity INL -5 +5 LSB
Differential Nonlinearity DNL Guaranteed monotonic -1 +1 LSB
Offset Error -70 +70 mV
Offset-Error Temperature
Coefficient
Gain Error -2 0 %
Gain-Error Temperature
Coefficient
DYNAMIC PERFORMANCE—FINE DAC (CL = 200pF, RL = 10kΩ)
Output Noise f = 0.1Hz to 1MHz 200 µV
DAC Glitch Impulse Major carry transition 12 nV•s
Voltage-Output Settling Time
Voltage-Output Slew Rate 0.6 V/µs
STATIC ACCURACY—REFDACH AND REFDACL
Resolution 8 Bits
Integral Nonlinearity INL -0.5 +0.5 LSB
Differential Nonlinearity DNL -0.2 +0.2 LSB
Offset Error -30 +30 mV
Offset-Error Temperature
Coefficient
Gain Error -5 +5 LSB
Gain-Error Temperature
Coefficient
FLASH MEMORY
Programming Endurance 10,000 Cycles
Data Retention TA = +85°C 15 Years
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AVDD
DVDD
I
AVDD
I
DVDD
All channels selected
25% to 75% FS 3
1% FS 1.5
PGA disabled 60 80
PGA enabled 120 140
26 40 mA
±50 µV/°C
±20
±50 µV/°C
5
5
±20
mA
mA
ppm of
FS/°C
RMS
µs
ppm of
FS/°C
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
_______________________________________________________________________________________ 7
Note 1: Devices 100% production tested at TA= +125°C. Guaranteed by design and characterization to TA= -40°C.
Note 2: Full scale in analog EQ mode decreases with increasing frequency at a rate of 20dB/decade from 5kHz. If digital EQ is also
used, full scale decreases with increasing frequency at 40dB/decade from 5kHz.
Note 3: SFDR in the EQ mode is normalized to the input by subtracting the analog EQ gain at each frequency (20dB/decade) from
the FFT results.
Note 4: The absolute input voltage range is 0 to AVDD. For optimal performance, use a common-mode voltage of AVDD/2.
Note 5: Switched capacitor input impedance is proportional to 1/fC. Where f is the sampling frequency and C is the input capacitance.
ELECTRICAL CHARACTERISTICS (continued)
((V
AVDD
= +3.0V to +3.6V, V
DVDD
= +3.0V, C
DVREG
= 10µF, V
AGND
= V
DGND
= 0, common-mode input voltage = AVDD/2, V
REFBP
=
V
REFA
= V
REFB
= V
REFC
= V
REFD
= +2.5V (external reference), V
REFDAC
= V
REFDACH
= +1.25V (external reference), V
REFDACL
= 0,
C
REFBP
= C
REFA
= C
REFB
= C
REFC
= C
REFD
= C
REFDAC
= 1µF, f
SCLK
= 38.4MHz, f
EXCLK
= 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. T
A
= T
MIN
to T
MAX
, unless otherwise noted (Note 1).
Typical values are at T
A
= +25°C.)
Typical Operating Characteristics
(V
AVDD
= +3.3V, V
DVDD
= +3.0V, f
SCLK
= f
EXCLK
= 19.2MHz, V
REFBP
, V
REF_
= +2.5V, common-mode input voltage = AVDD/2,
TA = +25°C, unless otherwise noted.)
INL vs. CODE
MAX11043 toc01
CODE (LSB)
INL (LSB)
491523276816384
-4
-3
-2
-1
0
1
2
3
4
5
-5
0 65536
LP MODE
GAIN = 1
400ksps FFT
LP MODE
MAX11043 toc02
FREQUENCY (kHz)
AMPLITUDE (dBFS)
18016014012010080604020
-100
-80
-60
-40
-20
0
-120
0 200
fIN = 50kHz
GAIN = 1
800ksps FFT
LP MODE
MAX11043 toc03
FREQUENCY (kHz)
AMPLITUDE (dBFS)
35030025020015010050
-120
-100
-80
-60
-40
-20
0
-140
0400
fIN = 50kHz
GAIN = 1
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI INTERFACE
SCLK Clock Period t
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
SCLK Rise to DOUT Transition t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Setup Time t
DIN to SCLK Rise Setup Time t
DIN to SCLK Rise Hold Time t
CS Pulse-Width High t
CS Rise to DOUT Disable t
CS Fall to DOUT Enable t
EOC Fall to CS Fall t
CP
CH
CL
DOT
CSS
CSH
DS
DH
CSPWH
DOD
DOE
RDS
C
= 20pF 1 15 ns
LOAD
= 20pF 20 ns
C
LOAD
C
= 20pF 1 ns
LOAD
25 ns
10 ns
10 ns
10 ns
5ns
10 ns
0ns
10 ns
10 ns
FINE DAC SETTLING
75% TO 25% FS STEP
MAX11043 toc10
500mV/div
0V
FINE DAC SETTLING
1% STEP-UP
MAX11043 toc11
1μs/div
20mV/div
1200mV
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= +3.3V, V
DVDD
= +3.0V, f
SCLK
= f
EXCLK
= 19.2MHz, V
REFBP
, V
REF_
= +2.5V, common-mode input voltage = AVDD/2,
T
A
= +25°C, unless otherwise noted.)
400ksps FFT
EQ MODE
0
fIN = 5kHz
V
= 560mV
-20
-40
-60
AMPLITUDE (dBFS)
-80
-100
-120
0200
FREQUENCY (kHz)
INP-P
MAX11043 toc04
18016014012010080604020
0
-20
-40
-60
-80
AMPLITUDE (dBFS)
-100
-120
-140
0 400200
800ksps FFT
EQ MODE
FREQUENCY (kHz)
SINAD vs. INPUT AMPLITUDE
80
fIN = 100kHz
V
INP-P
= 1.4mV
MAX11043 toc05
70
60
50
40
30
SINAD (dB)
20
1kHz
10
0
-10
-20
-90 0
10kHz
INPUT AMPLITUDE (dBFS)
MAX11043 toc06
50kHz
-10-30-70 -50 -20-40-80 -60
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 4096
FINE DAC DNL
vs. CODE
CODE (LSB)
FINE DAC INL
vs. CODE
5
4
MAX11043 toc07
307220481024
3
2
1
0
INL (LSB)
-1
-2
-3
-4
-5
0 4096
CODE (LSB)
307220481024
MAX11043 toc08
FINE DAC SETTLING
25% TO 75% FS STEP
MAX11043 toc09
500mV/div
0V
MAX11043
FINE DAC SETTLING
1% STEP-DOWN
MAX11043 toc12
1μs/div
20mV/div
1200mV
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
_______________________________________________________________________________________ 9
COARS
Typical Operating Characteristics (continued)
(V
AVDD
= +3.3V, V
DVDD
= +3.0V, f
SCLK
= f
EXCLK
= 19.2MHz, V
REFBP
, V
REF_
= +2.5V, common-mode input voltage = AVDD/2,
T
A
= +25°C, unless otherwise noted.)
POWER-ON RESET
vs. TEMPERATURE
MAX11043 toc19
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
12010060 8002040-20
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
-40
ANALOG SUPPLY
DIGITAL SUPPLY
E DAC INL
vs. CODE
0.5
CODES 3 TO 255
0.4
0.3
0.2
0.1
0
INL (LSB)
-0.1
-0.2
-0.3
-0.4
-0.5
0 256
DACL
CODE (LSB)
DACH
MAX11043 toc15
19212864
FINE DAC NOISE FLOOR
0
FREQUENCY (kHz)
COARSE DAC SETTLING TIME,
POSITIVE STEP
2ms/div
1401201004020 1801608060 200
COARSE DAC DNL
MAX11043 toc13
0dBm
20dBm/div
1.0
CODES 3 TO 255
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0256
vs. CODE
DACH
DACL
CODE (LSB)
COARSE DAC SETTLING TIME,
MAX11043 toc16
200mV/div
NEGATIVE STEP
2ms/div
MAX11043 toc14
19212864
MAX11043 toc17
200mV/div
DVREG VOLTAGE vs. TEMPERATURE
2.369
2.368
2.367
2.366
2.365
DVREG VOLTAGE (V)
2.364
2.363
2.362
-40
TEMPERATURE (°C)
MAX11043 toc18
120100806040200-20
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 AINBN Channel B Analog Negative Input
2 REFA Channel A Reference Bypass. Bypass REFA with a nominal 1µF capacitor to AGND.
3 AINAN Channel A Analog Negative Input
4 AINAP Channel A Analog Positive Input
5, 26 AVDD Analog Supply. Bypass each AVDD with a nominal 1µF capacitor to AGND.
6, 24, 33 AGND Analog Ground. Connect AGND inputs together.
7, 23 DGND Digital Ground. Connect DGND inputs together.
8, 22 DVDD Digital Supply. Bypass each DVDD with a nominal 1µF capacitor to DGND.
9 DVREG Regulated Digital Core Supply. Bypass DVREG to DGND with a 10µF capacitor.
10 UP/DWN DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
11 DACSTEP
12 CONVRUN
13 CS Active-Low Serial-Interface Chip Select
14 DOUT Serial-Interface Data Out. Data transitions on the rising edge of SCLK.
15 DIN Serial-Interface Data In. Data is sampled on the rising edge of SCLK.
16 SCLK Serial-Interface Clock
17, 35 I.C. Internally Connected. Connect to either AGND or DGND.
18 EOC Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
19 OSCIN Crystal Oscillator/External Clock Input
20 OSCOUT Crystal-Oscillator Output. Leave unconnected when using external clock.
21 SHDN Active-High Shutdown Input. Drive high to shut down the MAX11043.
25 AOUT Buffered 12-Bit Fine DAC Output
27 REFDACL Fine DAC Low Reference Bypass. Bypass REFDACL with a nominal 1µF capacitor to AGND.
28 REFDACH Fine DAC High Reference Bypass. Bypass REFDACH with a nominal 1µF capacitor to AGND.
29 REFDAC Coarse DAC Reference Bypass. Bypass REFDAC with a nominal 1µF capacitor to AGND.
30 REFD Channel D Reference Bypass. Bypass REFD with a nominal 1µF capacitor to AGND.
31 AINDN Channel D Analog Negative Input
32 AINDP Channel D Analog Positive Input
34 REFBP Main Reference Bypass. Bypass REFBP with a nominal 1µF capacitor to AGND.
36 AINCN Channel C Analog Negative Input
37 AINCP Channel C Analog Positive Input
38 REFC Channel C Reference Bypass. Bypass REFC with a nominal 1µF capacitor to AGND.
39 REFB Channel B Reference Bypass. Bypass REFB with a nominal 1µF capacitor to AGND.
40 AINBP Channel B Analog Positive Input
—EP
DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
edge of the system clock.
Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
CONVRUN is low.
Exposed Pad. Connect EP to a ground plane on the PCB to enhance thermal dissipation. Internally
connected to AGND. Not intended as an electrical connection point.
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