Rainbow Electronics MAX11008 User Manual

General Description

The MAX11008 controller biases RF LDMOS power devices found in cellular base stations and other wireless infrastructure equipment. Each controller includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor the LDMOS drain current over a range of 20mA to 5A. The MAX11008 supports up to two external diode-connected transistors to monitor the LDMOS temperatures while an internal temperature sensor measures the local die temperature. A 12-bit successive-approximation register (SAR) analogto-digital converter (ADC) converts the analog signals from the programmable-gain amplifiers (PGAs), external temperature sensors, internal temperature measurement, and two additional auxiliary inputs. The MAX11008 automatically adjusts the LDMOS bias voltages by applying temperature, AIN, and/or drain current samples to data stored in lookup tables (LUTs).

The MAX11008 includes two gate-drive channels, each consisting of a 12-bit DAC to generate the positive gate voltage for biasing the LDMOS devices. Each gatedrive output supplies up to ±2mA of gate current. The gate-drive amplifier is current-limited to ±25mA and features a fast clamp to AGND.

The MAX11008 contains 4Kb of on-chip, nonvolatile EEPROM organized as 256 bits x 16 bits to store LUTs and register information. The device operates from either a 4-wire 16MHz SPI™-/MICROWIRE™-compatible or an I2C-compatible serial interface.

The MAX11008 operates from a +4.75V to +5.25V analog supply with a typical supply current of 2mA, and a +2.7V to +5.25V digital supply with a typical supply of 3mA. The device is packaged in a 48-pin, 7mm x 7mm, thin QFN package and operates over the extended (-40°C to +85°C) temperature range.

Applications

Cellular Base Stations

Microwave Radio Links

Feed-Forward Power Amps

Transmitters

Industrial Process Control

Features

♦ On-Chip 4Kb EEPROM for Storing LDMOS Bias

Characteristics

♦ Integrated High-Side Current-Sense PGA with

Gain of 2, 10, or 25

♦ ±0.75% Accuracy for Sense Voltage Between

+75mV and +1250mV

♦ Full-Scale Sense Voltage

+100mV with a Gain of 25 +250mV with a Gain of 10 +1250mV with a Gain of 2

♦ Common-Mode Range, LDMOS Drain Voltage:

+5V to +32V

♦ Adjustable Low-Noise 0 to AV

Output Gate

Bias Voltage Range

♦ Fast Clamp to AGND for LDMOS Protection

♦ 12-Bit DAC Control of Gate with Temperature

♦ Internal Die Temperature Measurement

♦ 2-Channel External Temperature Measurement

through Remote Diodes

♦ Internal 12-Bit ADC Measurement for

Temperature, Current, and Voltage Monitoring

♦ User-Selectable Serial Interface

400kHz/1.7MHz/3.4MHz I

C-Compatible Interface

16MHz SPI-/MICROWIRE-Compatible Interface

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

________________________________________________________________

Maxim Integrated Products

19-4371; Rev 0; 11/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

SPI is a trademark of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Ordering Information

Denotes a lead-free/RoHS-compliant package.

EP = Exposed pad.

Note: The device is specified over the -40°C to +85°C operating temperature range.

PART PIN-PACKAGE

MAX11008BETM+ 48 TQFN-EP* ±3

TEMP

ERROR (°C)

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

CS_+

= +32V, AVDD= DVDD= +5V ±5%, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V, C

REF

= 0.1µF, C

GATE_

= 0.1nF,

SENSE

= V

CS_+

- V

CS_-

, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto AGND .........................................................-0.3V to +6V

to DGND.........................................................-0.3V to +6V

AGND to DGND.....................................................-0.3V to +0.3V

CS_+, CS_- to AGND .............................................-0.3V to +34V

CS_+ to CS_-

If CS_+ > 6V .........................................................-0.3V to +6V

If CS_+ ≤ 6V .......................................................-0.3V to V

CS_-

Analog Inputs/Outputs to AGND ..................................................

...........................-0.3V to the lower of (AV

+ 0.3V) and +6V

Digital Inputs/Outputs to DGND

(except SDA/DIN and SCL/SCLK)............................................

............................-0.3V to the lower of (DV

+ 0.3V) and +6V

SDA/DIN and SCL/SCLK to DGND ..........................-0.3V to +6V

Continuous Input Current (all terminals)...........................±50mA

Continuous Power Dissipation (T

= +70°C) 48-Pin, 7mm x 7mm, TQFN (derate 27.8mW/°C above

+70°C).....................................................................2222.2mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

HIGH-SIDE CURRENT-SENSE PGA

Common-Mode Input Voltage Range

Common-Mode Rejection Ratio CMRR 5V < V

CS_+ Input Bias Current I

CS_- Input Bias Current I

Minimum Sense Voltage Range for ±0.75% V

Minimum Sense Voltage Range for ±2.5% V

Total PGAOUT Voltage Error V

PGAOUT Capacitive Load C

PGAOUT Settling Time t

Saturation Recovery Time

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SENSE

CS1+

CS2+

CS_+

CS_-

SENSE

Accuracy

PGAOUT

HSCS

CS_+

< 100mV over the common-mode

SENSE

range

< 100mV over the common-mode

SENSE

range

Gain = 25 0 100

Gain = 10 0 250Full-Scale Sense Voltage Range V

Gain = 2 0 1250

Gain = 25 75 100

Gain = 10 75 250

Gain = 2 75 1250

Gain = 25 20 100

Gain = 10 20 250

Gain = 2 20 1250

= 75mV ±0.1 ±0.75 %

SENSE

(Note 1) < 25 µs

Settles to within ±0.5% accuracy from V

= 3 x full scale

SENSE

< 32V 110 dB

532V

135 195 µA

< 45 µs

±1 µA

50 pF

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

CS_+

= +32V, AVDD= DVDD= +5V ±5%, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V, C

REF

= 0.1µF, C

GATE_

= 0.1nF,

SENSE

= V

CS_+

- V

CS_-

, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LDMOS GATE DRIVER (Gain = 2)

GATE_

Output Gate-Drive Voltage Range V

Output Impedance R

GATE_ Settling Time t

Output Capacitive Load C

GATE_

Measured at DC 0.1 Ω

0.5V to 4.5V (Note 1)

GATE_ Noise 1kHz to 1MHz 1000 µV

Maximum Power-On Transient ±100 mV

Output Short-Circuit Current Limit I

Total Unadjusted Error TUE

Total Unadjusted Error without Offset

TUE

NO_OFFSET

1s, sinking or sourcing ±25 mA

Worst case at CODE = 4063, use external reference (Note 2)

CalCODE = 2457, MaxCODE = 2867, use external reference, T (Note 2)

Drift Gain = 2, MaxCODE = 2867 (Note 2) ±15 µV/°C

Clamp to Zero Delay C

Output-Safe Switch OnResistance

OPSW

MONITOR ADC (DC characteristics)

Resolution N

Differential Nonlinearity DNL

Integral Nonlinearity INL

ADC

(Note 5) -2 +2 LSB

Offset Error ±2 ±4 LSB

Gain Error (Note 6) ±2 ±4 LSB

Gain Temperature Coefficient ±0.4 ppm/°C

Offset Temperature Coefficient ±0.4 ppm/°C

MONITOR ADC DYNAMIC CHARACTERISTICS (1kHz sine-wave input, 2.5V

Signal-to-Noise Plus Distortion SINAD 70 dB

Total Harmonic Distortion THD Up to 5th harmonic -82 dBc

Spurious-Free Dynamic Range SFDR 86 dBc

Intermodulation Distortion IMD f

IN1

Full-Power Bandwidth -3dB 1 MHz

Full-Linear Bandwidth SINAD > 68dB 100 kHz

= ±0.1mA 0.1

= ±2mA 0.75

= 500Ω, C

= 0Ω 0 0.5

SERIES

= 500Ω 0 15,000

SERIES

GATE_

= 15µF, V

GATE_

45 ms

±7 ±25 mV

= +25°C

= 0.5nF (Note 3) 1 µs

GATE_

clamped to AGND (Note 4) 300 Ω

GATE_

12 Bits

, up to 94.4ksps)

P-P

= 0.99kHz, f

= 1.02kHz 76 dBc

IN2

0.1

0.75

±8 mV

±2 LSB

P-P

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

CS_+

= +32V, AVDD= DVDD= +5V ±5%, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V, C

REF

= 0.1µF, C

GATE_

= 0.1nF,

SENSE

= V

CS_+

- V

CS_-

, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MONITOR ADC CONVERSION RATE

Power-Up Time (External Reference)

Power-Up Time (Internal Reference)

Acquisition Time t

Conversion Time t

Aperture Delay t

PUEXT

PUINT

ACQ

CONV

Internally clocked, T

MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)

Input Voltage Range V

ADCIN

Relative to AGND (Note 7) 0 V

Input Leakage Current VIN = 0 and VIN = V

Input Capacitance C

ADCIN

TEMPERATURE MEASUREMENTS

Internal Sensor Measurement Error

External Sensor Measurement Error (Note 9)

TA = +25°C ±0.25

= T

TA = +25°C ±1

= T

Relative Temperature Accuracy TA = T

Temperature Resolution 1/8 °C/LSB

E xter nal D i od e D r i ve C ur r ent ( Low ) 3.25 4 µA

E xter nal D i od e D r i ve C ur r ent ( H i g h) 68 75 µA

INTERNAL REFERENCE

REFADC/REFDAC Output Voltage

REFADC/REFDAC Temperature Coefficient

REFADC

REFDAC

REFADC

REFDAC

TA = +25°C 2.49 2.50 2.51 V

REFADC/REFDAC Output Impedance

Capacitive Bypass at REFADC/REFDAC

Power-Supply Rejection Ratio PSRR AVDD = 5V ± 5% 64 dB

EXTERNAL REFERENCE

REFADC Input Voltage Range V

REFADC Input Current I

REFDAC Input Voltage Range V

REFADC

REFDAC

REFADC

Acquisition/between conversions ±0.01

REFDAC Input Current S tati c cur r ent w hen the D AC i s not cal i b r ated 0.1 µA

to T

MIN

MAX

to T

MIN

MAX

to T

MIN

MAX

= 2.5V, f

1.1 µs

70 µs

0.5 µs

= +25°C 10 µs

20 ns

REFADC

±0.01 µA

34 pF

(Note 8) ±1.5 ±3

±3

(Note 9) ±0.4 °C

±15 ppm/°C

6.5 kΩ

270 pF

1.0 AV

= 100ksps 60 80

SAMPLE

0.7 2.5 V

°C

µA

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

CS_+

= +32V, AVDD= DVDD= +5V ±5%, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V, C

REF

= 0.1µF, C

GATE_

= 0.1nF,

SENSE

= V

CS_+

- V

CS_-

, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)

GATE-DRIVER DAC DC ACCURACY

Resolution N

Integral Nonlinearity INL

Differential Nonlinearity DNL

DIGITAL INPUTS (SCL/SCLK, SDA/DIN, A0/CS, A1/DOUT, A2/N.C., CNVST, OPSAFE1, OPSAFE2)

Input High Voltage V

Input Low Voltage V

Input Hysteresis V

Input Leakage Current Digital inputs at 0 or V

Input Capacitance C

DIGITAL OUTPUTS (SDA/DIN, ALARM, BUSY, DOUT)

Output High Voltage V

Output Low Voltage V

Three-State Leakage I

Three-State Capacitance 5pF

POWER SUPPLIES (Note 12)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DAC

HYS

Measured at GATE_ ±2 ±4 LSB

Guaranteed monotonic (Note 10) ±1 LSB

SDA/DIN and SCL/SCLK only

A0/CS, A1/DOUT, A2/N.C., CNVST, OPSAFE1, OPSAFE2 only

SDA/DIN and SCL/SCLK only

A0/CS, A1/DOUT, A2/N.C., CNVST, OPSAFE1, OPSAFE2 only

SDA/DIN and SCL/SCLK only

ALARM and BUSY only, I

SDA/DIN and A1/DOUT, I (Note 11)

ALARM and BUSY only, I

Digital inputs at 0 or DV

DVDD

SOURCE

= 3mA,

SINK

= 0.3mA 0.3

SINK

= 0.2mA

0.7 x

2.3

0.08 x DV

- 0.4V

12 Bits

±0.1 ±1 µA

5pF

±0.1 ±1 µA

0.3 x

0.7

0.4

Analog Supply Voltage Range AV

Digital Supply Voltage Range DV

Analog Supply Current I

Digital Supply Current I

AVDD

DVDD

AVDD = 5V 2 4 mA

Shutdown (Note 13) 0.4 2 µA

DVDD = 5V 3 6 mA

Shutdown 2 32 µA

4.75 5.25 V

2.7

+ 0.3

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

6 _______________________________________________________________________________________

SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1)

(DVDD= +2.7V to +5.25V, AVDD= +4.75V to +5.25V, V

DGND

= V

AGND

= 0, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V,

REF

= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)

I2C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)

(DVDD= +2.7V to +5.25V, AVDD= +4.75V to +5.25V, V

DGND

= V

AGND

= 0, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V,

REF

= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Clock Period t

SCLK High Time t

SCLK Low Time t

DIN to SCLK Rise Setup Time t

DIN to SCLK Rise Hold Time t

SCLK Fall to DOUT Transition t

CS Fall to DOUT Enable t CS Rise to DOUT Disable t CS Rise or Fall to SCLK Rise t CS Pulse-Width High t

Last SCLK Rise to CS Rise t

CSS

CSW

CSH

CL = 30pF 20 ns

CL = 30pF 50 ns

CL = 30pF (Note 16) 50 ns

SCL Clock Frequency f

Bus Free Time Between a STOP and START Condition

Hold Time (Repeated) for START Condition

Setup Time for a Repeated START Condition

SCL Pulse-Width Low t

SCL Pulse-Width High t

Data Setup Time t

Data Hold Time t

SDA, SCL Rise Time t

SDA, SCL Fall Time t

SDA Fall Time t

Setup Time for STOP Condition t

Capacitive Load for Each Bus Line

Pulse Width of Spikes Suppressed by the Input Filter

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL

BUF

HD:STA

SU:STA

LOW

HIGH

SU:DAT

HD:DAT

SU:STO

After this period, the first clock pulse is generated

(Note 17) 0.004 0.9 µs

Receiving (Note 18) 0 300 ns

Transmitting (Notes 18, 19)

(Note 20) 400 pF

(Note 21) 50 ns

62.5 ns

25 ns

15 ns

0ns

12.5 ns

50 ns

0ns

0 400 kHz

1.3 µs

0.6 µs

1.3 µs

0.6 µs

100 ns

20 + 0.1

x C

0.6 µs

250 ns

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

_______________________________________________________________________________________ 7

I2C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)

(DVDD= +2.7V to +5.25V, AVDD= +4.75V to +5.25V, V

DGND

= V

AGND

= 0, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V,

REF

= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)

MISCELLANEOUS TIMING CHARACTERISTICS (Note 15)

(DVDD= +2.7V to +5.25V, AVDD= +4.75V to +5.25V, V

DGND

= V

AGND

= 0, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V,

REF

= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS

Serial Clock Frequency f Setup Time (Repeated) START

Condition Hold Time (Repeated) START Condition

SCL Pulse-Width Low t

SCL Pulse-Width High t

Data Setup Time t

Data Hold Time t

SCL Rise Time t

SCL Fall Time t SDA Rise Time t

SDA Fall Time t

Setup Time for STOP Condition t

Capacitive Load for Each Bus Line C

Pulse Width of Spikes Suppressed by the Input Filter

SCL

SU:STA

HD:STA

LOW

HIGH

SU:DAT

HD:DAT

RCL

RCL1

FCL

RDA

FDA

SU:STO

(Note 17) 4 70 4 150 ns

After a repeated START condition and after an acknowledge bit

(Note 20) 100 400 ns

(Note 21) 0 10 0 10 ns

CB = 100pF max CB = 400pF

MIN MAX MIN MAX

0 3.4 0 1.7 MHz

160 160 ns

160 320 ns

80 120 ns

10 10 ns

10 40 20 80 ns

10 80 20 160 ns

10 40 20 80 ns 10 80 20 160 ns

10 80 20 160 ns

160 160 ns

UNITS

Minimum Time to Wait After a Write Command Before Reading Back Data from the Same Location

CNVST Active-Low Pulse Width in ADC Clock Mode 01

CNVST Active-Low Pulse Width in ADC Clock Mode 11 to Initiate a Temperature Conversion

CNVST Active-Low Pulse Width in ADC Clock Mode 11 for ADCIN1/2 Acquisition

ADC Power-Up Time (External Reference)

ADC Power-Up Time (Internal Reference)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RDBK

CNV01

CNV11

ACQ11A

APUEXT

APUINT

(Note 22) 1 µs

20 ns

1.5 µs

1.1 µs

70 µs

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

8 _______________________________________________________________________________________

MISCELLANEOUS TIMING CHARACTERISTICS (Note 15) (continued)

(DVDD= +2.7V to +5.25V, AVDD= +4.75V to +5.25V, V

DGND

= V

AGND

= 0, external V

REFADC

= +2.5V, external V

REFDAC

= +2.5V,

REF

= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)

Note 1: Output settles to within ±0.5% of final value. Note 2: Total unadjusted errors are for the entire gate-drive channel including the 12-bit DAC, and the gate driver is measured at

the GATE1 and GATE2 outputs.

Note 3: V

GATE_

= VDD- 0.1. Measured from when OPSAFE1 or OPSAFE2 is set high.

Note 4: During power-on-reset, the output safe switch is closed. The output safe switch is opened under user software control. Note 5: Guaranteed to be 11 bits linearly accurate. Note 6: Offset nulled. Note 7: The absolute range for analog inputs is from 0 to V

AVDD

Note 8: Internal temperature-sensor performance is guaranteed by design. Note 9: The MAX11008 and the external sensor are at the same ambient temperature. External sensor measurement error is tested

with a diode-connected 2N3904.

Note 10: Guaranteed monotonicity. Accuracy is degraded at lower V

REFDAC

Note 11: SDA/DIN is an open-drain output only when in I

C mode. A1/DOUT is an open-drain output only when in SPI mode.

Note 12: Supply-current limits are valid only when digital inputs are set to DGND or supply voltage. Timing specifications are only

guaranteed when inputs are driven rail-to-rail.

Note 13: Shutdown supply currents are typically 0.4µA for AV

; maximum specification is limited by automated test equipment.

Note 14: All times are referred to the 50% point between V

and VILlevels.

Note 15: Guaranteed by design. Not production tested. Note 16: DOUT will go into three-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled

before it goes to three-state.

Note 17: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 18: t

and tFmeasured between 0.3 x DVDDand 0.7 x DVDD.

Note 19: C

= total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be

linearly interpolated.

Note 20: An appropriate bus pullup resistance must be selected depending on board capacitance. Note 21: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 22: When a command is written to the serial interface, the command is passed by the internal oscillator clock and executed.

There is a small synchronization delay before the new value is written to the appropriate register. If the serial interface attempts to read the new value back before t

RDBK

, the new data is not corrupted; however, the result of the read command

may not reflect the new value.

Note 23: This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from

the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of the wrong ADC channel).

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DAC Power-Up Time (External Reference)

DAC Power-Up Time (Internal Reference)

Acquisition Time (Internally Timed in ADC Clock Modes 00 or 01)

Conversion Time (Internally Clocked)

Delay to Start of Conversion Time t

Temperature Conversion Time (Internally Clocked)

DPUEXT

DPUINT

ACQ

CONV

CONVW

CONVT

Internally clocked, TA = +25°C 10 µs

(Note 23) 1.3 µs

2µs

70 µs

0.6 µs

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

_______________________________________________________________________________________ 9

Typical Operating Characteristics

(AVDD= DVDD= 5V, external V

REFADC

= 2.5V, external V

REFDAC

= 2.5V, V

CS_-

= V

CS_+

= 32V, C

REF

= 0.1µF, TA= +25°C, unless oth-

erwise noted.)

2.06

2.07

2.08

2.09

2.10

4.7 4.94.8 5.0 5.1 5.2 5.3

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX11008 toc01

AVDD (V)

AVDD

(mA)

DVDD = 5V INT REF AND DACS TURNED ON

1.0

1.5

2.5

2.0

3.0

3.5

2.70 3.743.22 4.26 4.78 5.30

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX11008 toc02

DVDD (V)

DVDD

(mA)

AVDD = 5V WD OSC TURNED ON

-0.8

-0.6

-0.2

-0.4

0.2

-40 20-10 50 80 110

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. TEMPERATURE (G = 2)

MAX11008 toc03

TEMPERATURE (°C)

PGAOUT_ ERROR (%)

AFTER CALIBRATION

BEFORE CALIBRATION

-0.8

-0.4

-0.6

-0.2

0.2

0.4

-40 20-10 50 80 110

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. TEMPERATURE (G = 10)

MAX11008 toc04

TEMPERATURE (°C)

PGAOUT_ ERROR (%)

AFTER

CALIBRATION

BEFORE

CALIBRATION

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. TEMPERATURE (G = 25)

MAX11008 toc05

TEMPERATURE (°C)

PGAOUT_ ERROR (%)

805020-10

-0.6

-0.3

0.3

-0.9

-40 110

AFTER

CALIBRATION

BEFORE

CALIBRATION

0.2

0.6

0.4

0.8

1.0

0500250 750 1000 1250

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. SENSE VOLTAGE (G = 2)

MAX11008 toc06

SENSE

(mV)

OUTPUT ERROR (%)

OUTPUT AT PGAOUT_ CMV = 32V

0.2

0.6

0.4

0.8

1.0

0 10050 150 200 250

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. SENSE VOLTAGE (G = 10)

MAX11008 toc07

SENSE

(mV)

OUTPUT ERROR (%)

OUTPUT AT PGAOUT_ CMV = 32V

04020 60 80 100

CURRENT-SENSE AMPLIFIER OUTPUT

ERROR vs. SENSE VOLTAGE (G = 25)

MAX11008 toc08

SENSE

(mV)

OUTPUT ERROR (%)

OUTPUT AT PGAOUT_ CMV = 32V

0.10

0.05

0.20

0.15

0.25

0.30

5152010 25 30 35

CURRENT-SENSE AMPLIFIER

OUTPUT ERROR vs. CMV

MAX11008 toc09

COMMON-MODE VOLTAGE (V)

OUTPUT ERROR (%)

SENSE

= 75mV

G = 2

G = 25

G = 10

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= 5V, external V

REFADC

= 2.5V, external V

REFDAC

= 2.5V, V

CS_-

= V

CS_+

= 32V, C

REF

= 0.1µF, TA= +25°C, unless oth-

erwise noted.)

2µs/div

CURRENT-SENSE TRANSIENT

RESPONSE (G = 2)

SENSE1

1V/div

PGAOUT1

1V/div

MAX11008 toc10

1µs/div

CURRENT-SENSE TRANSIENT

RESPONSE (G = 10)

SENSE1

200mV/div

PGAOUT1

1V/div

MAX11008 toc11

1µs/div

CURRENT-SENSE TRANSIENT

RESPONSE (G = 25)

SENSE1

100mV/div

PGAOUT1

1V/div

MAX11008 toc12

-4.50

-4.35

-4.05

-4.20

-3.90

-3.75

-40 18-11 47 76 105

GATE VOLTAGE TOTAL UNADJUSTED

ERROR vs. TEMPERATURE

MAX11008 toc13

TEMPERATURE (°C)

GATE_

ERROR (mV)

1µs/div

GATE POWER-UP TIME

SCL

5V/div

SDA

5V/div

GATE1

1V/div

MAX11008 toc14

0.5

1.5

1.0

2.0

2.5

0200100 300 400 500

GATE_ SETTLING TIME vs. C

GATE

MAX11008 toc16

GATE_

(pF)

GATE_ SETTLING TIME (µs)

RS = 500Ω 50% OF SDA STOP EDGE TO

0.5% OF FINAL V

GATE_

4V TRANS ON GATE_ (IODAC_)

10µs/div

MAJOR CARRY TRANSITION GLITCH

GATE_

1mV/div

MAX11008 toc17

CODE 7FF TO 800 C

GATE_

= 100pF

-1.0

-0.4

-0.6

-0.8

-0.2

0.2

0.4

0.6

0.8

1.0

0 1024 2048 3072 4096

DAC INTEGRAL NONLINEARITY

vs. INPUT CODE

MAX11008 toc18

INPUT CODE

INL (LSB)

-1.0

-0.4

-0.6

-0.8

-0.2

0.2

0.4

0.6

0.8

1.0

0 1024 2048 3072 4096

DAC DIFFERENTIAL NONLINEARITY

vs. INPUT CODE

MAX11008 toc19

INPUT CODE

DNL (LSB)

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= 5V, external V

REFADC

= 2.5V, external V

REFDAC

= 2.5V, V

CS_-

= V

CS_+

= 32V, C

REF

= 0.1µF, TA= +25°C, unless oth-

erwise noted.)

ADC INTEGRAL NONLINEARITY

vs. OUTPUT CODE

1.00

0.75

0.50

0.25

ADC INL (LSB)

-0.25

-0.50

-0.75

-1.00 0 1024 2048 3072 4096

OUTPUT CODE

ADC SFDR vs. FREQUENCY

100

SFDR (dB)

1.00

MAX11008 toc20

MAX11008 toc23

0.75

0.50

0.25

ADC DNL (LSB)

-0.25

-0.50

-0.75

-1.00 0 1024 2048 3072 4096

AVDD = DVDD = 5V

SUPPLY CURRENT (mA)

ADC DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

OUTPUT CODE

DIGITAL SUPPLY CURRENT

vs. SAMPLING RATE

MAX11008 toc21

SINAD (dB)

0.1 101 100 1000

ADC INTERNAL REFERENCE VOLTAGE

2.5026

MAX11008 toc24

2.5024

2.5022

2.5020

ADC REFERENCE VOLTAGE (V)

ADC SINAD vs. FREQUENCY

FREQUENCY (kHz)

vs. SUPPLY VOLTAGE

AVDD = DV

MAX11008 toc22

MAX11008 toc25

0.1 101 100 1000 FREQUENCY (kHz)

0.1 101 100 1000 SAMPLING RATE (ksps)

2.5018

4.750 5.0004.875 5.125 5.250 SUPPLY VOLTAGE (V)

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= 5V, external V

REFADC

= 2.5V, external V

REFDAC

= 2.5V, V

CS_-

= V

CS_+

= 32V, C

REF

= 0.1µF, TA= +25°C, unless oth-

erwise noted.)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.52

2.0

ADC OFFSET ERROR

vs. ANALOG SUPPLY VOLTAGE

ADC OFFSET ERROR vs. TEMPERATURE

2.51 V

REFADC

2.50

REFERENCE VOLTAGE (V)

2.49

2.48

-50 25 50-25 0 75 100 125 TEMPERATURE (°C)

ADC GAIN ERROR

vs. ANALOG SUPPLY VOLTAGE

3.0

2.5

2.0

1.5

1.0

ADC GAIN ERROR (LSB)

0.5

4.750 5.0004.875 5.125 5.250 AVDD (V)

REFDAC

MAX11008 toc26

1.5

1.0

ADC OFFSET ERROR (LSB)

0.5

4.750 5.0004.875 5.125 5.250

MAX11008 toc29

ADC GAIN ERROR (LSB)

-1

-2

-3

-50 0 25-25 50 75 100 125

AVDD (V)

ADC GAIN EROR vs. TEMPERATURE

TEMPERATURE (°C)

MAX11008 toc27

ADC OFFSET ERROR (LSB)

-50 25 50-25 0 75 100 125

0.8

0.6

MAX11008 toc30

0.4

0.2

-0.2

EXTERNAL TEMP

-0.4 SENSOR

-0.6

RELATIVE TEMPERATURE ERROR

-0.8

-1.0

-40 18-11 47 76 105

TEMPERATURE (°C)

RELATIVE TEMPERATURE

ERROR vs. TEMPERATURE

INTERNAL TEMP SENSOR

TEMPERATURE (°C)

MAX11008 toc28

MAX11008 toc31

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________ 13

______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1, 31 DGND Digital Ground. Connect both DGND inputs to the same potential.

2 OPSAFE1

3 A0/CS

4 CNVST

5 SPI/I2C Interface-Select Input. Connect to DGND for I2C interface. Connect to DVDD for SPI interface.

6 ALARM Alarm Output

7 OPSAFE2

8 REFDAC DAC Reference Input/Output

9 REFADC ADC Reference Input/Output

10 DXP1 Temperature Diode Positive Input 1. Connect DXP1 to the anode of the external diode.

11 DXN1 Temperature Diode Negative Input 1. Connect DXN1 to the cathode of the external diode.

12 DXP2 Temperature Diode Positive Input 2. Connect DXP2 to the anode of the external diode.

13 DXN2 Temperature Diode Negative Input 2. Connect DXN2 to the cathode of the external diode.

14 ADCIN1 ADC Auxiliary Input 1

15 ADCIN2 ADC Auxiliary Input 2

16 PGAOUT2 Programmable-Gain Amplifier Output 2

17 GATE2 Gate-Drive Amplifier Output 2

18 GATE1 Gate-Drive Amplifier Output 1

19, 25, 30,

34–39, 42, 48

20, 24 AV

21, 22, 23 AGND Analog Ground. Connect all AGND inputs to the same potential.

26 CS2+ C ur r ent- S ense P osi ti ve Inp ut 2. C S 2+ i s the exter nal sense- r esi stor connecti on to the LD M OS 2 sup p l y.

27 CS2- Current-Sense Negative Input 2. CS2- is the external sense-resistor connection to the LDMOS 2 drain.

28 CS1- Current-Sense Negative Input 1. CS1- is the external sense-resistor connection to the LDMOS 1 drain.

29 CS1+ C ur r ent- S ense P osi ti ve Inp ut 1. C S 1+ i s the exter nal sense- r esi stor connecti on to the LD M OS 1 sup p l y.

32, 33, 47 DV

40 PGAOUT1 Programmable-Gain Amplifier Output 1

41 A2/N.C.

43 SCL/SCLK Serial-Clock Input. SCL is the I2C-compatible clock input. SCLK is the SPI-compatible clock input.

44 SDA/DIN S er i al - D ata Inp ut/Outp ut. S D A i s the I2C- com p ati b l e i np ut/outp ut. D IN i s the S P I- com p ati b l e d ata i np ut.

45 A1/DOUT

46 BUSY Busy Output. BUSY goes high to indicate activity.

— EP Exposed Pad. Connect EP to AGND. Internally connected to AGND.

N.C. No Connection. Not internally connected. Leave unconnected.

Output Safe Switch Logic Input 1. Drive OPSAFE1 high to close the output safe switch and clamp GATE1 to AGND. Drive OPSAFE1 low to open the switch.

Address-Select Input 0/Chip-Select Input. In I

1. In SPI mode, this is the chip-select input.

Active-Low Conversion Start Input. Drive CNVST low to begin a conversion when in clock modes 01 and 11.

Output Safe Switch Logic Input 2. Drive OPSAFE2 high to close the output safe switch and clamp GATE2 to AGND. Drive OPSAFE2 low to open the switch.

Analog-Supply Input. Connect both AVDD inputs to the same potential.

Digital-Supply Input. Connect all DVDD inputs to the same potential. Connect a 0.1µF capacitor to

Address-Select Input 2/N.C. In I mode, this is a no connection pin.

Address-Select Input 1/Data Out. In I mode, this is the serial-data output. Data is clocked out on the falling edge of SCLK. DOUT is a highimpedance output when CS is driven high.

C mode, this pin is the address-select input 2. See Table 1. In SPI

C mode, this is the address-select input 0. See Table

C mode, this is the address-select input 1. See Table 1. In SPI

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

14 ______________________________________________________________________________________14 ______________________________________________________________________________________

Functional Diagram

A1/DOUTA2/N.C.

A0/CS

PGAOUT1

SCL/SCLK

SDA/DIN

SPI/I2C

ALARM

BUSY

FIFO

EEPROM

SERIAL INTERFACE

AND DIGITAL

CONTROL

MAX11008

12-BIT DAC1

12-BIT DAC 2

CS1+

PGA 1

CS1-

= 2

PGA 2

= 2

GATE1

OPSAFE1

CS2+

CS2-

PGAOUT2

GATE2

OPSAFE2

REFDAC

REFADC

2.5V

REFERENCE

12-BIT ADC

CNVST

INTERNAL

TEMPERATURE

SENSOR

MUX

AGNDDGND

EXTERNAL

TEMPERATURE

SENSOR

PROCESSING

DXP1

DXN1

DXP2

DXN2

ADCIN1

ADCIN2

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________ 15______________________________________________________________________________________ 15

Typical Application Circuits—I2C Interface

0.1µF

4.7kΩ

SCL/SCLK

SDA/DIN

A0/CS

A1/DOUT

A2/N.C.

µC

OPSAFE1

OPSAFE2

ALARM

BUSY

CNVST

SPI/I2C

MAX11008

0.1µF

CS1+

CS1-

CS2+

CS2-

GATE2

RF IN

DXP2

32V

SENSE

LDMOS 1

RF OUT

EXTERNAL

2.5V

REFERENCE

REFADC

DXN2

GATE1

DXP1

DXN1

I2C SERIAL INTERFACE

= 1/(2 π RFCF).

CUTOFF

SECTION.

RF IN

RF OUT

LDMOS 2

0.1µF 0.1µF

*SDA RESISTOR VALUE VARIES WITH LOAD AND SCL FREQUENCY. SEE THE

*SELECT RF AND CF BASED ON DESIRED FILTER CUTOFF FREQUENCY WHERE f

LIMIT R

REFDAC

PGAOUT1

PGAOUT2

ADCIN1

ADCIN2

DGND AGND

TO 100Ω TO MINIMIZE OFFSET ERRORS.

MAX11008

Dual RF LDMOS Bias Controller with Nonvolatile Memory

16 ______________________________________________________________________________________

Typical Application Circuits—SPI Interface

µC

0.1µF

SCL/SCLK

SDA/DIN

A0/CS

A1/DOUT

OPSAFE1

OPSAFE2

ALARM

BUSY

CNVST

SPI/I2C

MAX11008

0.1µF

CS1+

CS1-

CS2+

CS2-

GATE2

RF IN

DXP2

32V

RF*

SENSE

LDMOS 1

RF OUT

EXTERNAL

2.5V

REFERENCE

0.1µF

*SELECT RF AND CF BASED ON DESIRED FILTER CUTOFF FREQUENCY WHERE f

LIMIT R

REFADC

REFDAC

PGAOUT1

PGAOUT2

ADCIN1

ADCIN2

DGND AGND

TO 100Ω TO MINIMIZE OFFSET ERRORS.

GATE1

CUTOFF

DXN2

DXP1

DXN1

= 1/(2 π RFCF).

RF IN

RF OUT

LDMOS 2

Detailed Description

The MAX11008 sets and controls the bias conditions for dual RF LDMOS power devices found in cellular base-station power amps. Each device includes two high-side current-sense amplifiers with programmable gains of 2, 10, and 25 to monitor the LDMOS transistor drain current over the 20mA to 5A range. Two external diode-connected transistors monitor the LDMOS transistor temperatures while an internal temperature sensor measures the local die temperature of the MAX11008. The 12-bit ADC is interfaced to a 7:1 multiplexer and converts the signals from the PGA outputs, internal and external temperature readings, or the two auxiliary analog inputs into digital data results that can be stored in the FIFO.

On the control side, two gate-drive channels, driven from two 12-bit DACs and a gain stage of 2, generate a positive gate voltage bias for the LDMOS. Each gatedrive output supports up to ±2mA of gate current. The gate-drive amplifier is current-limited to ±25mA and features a fast clamp to analog ground that operates independently of the serial interface.

The MAX11008 includes an on-chip, nonvolatile EEPROM that stores LUTs and register information. The LUTs are designed to store gate voltage vs. temperature curves for the LDMOS FET. The data is used for temperature compensation of the LDMOS FET’s bias point. The LUTs can also contain compensation data for another independent parameter: either sense voltage or AIN voltage.

Digital Serial Interface

The MAX11008 features both an I2C and an SPI-compatible serial interface. Connect SPI/I2C to DGND to select the I2C serial-interface operation, or to DVDDto select the SPI serial-interface operation. Do not alter interface mode during operation.

SPI Serial Interface

Connect SPI/I2C to DVDDto select the SPI interface. The SPI serial interface consists of a serial data input (DIN), a serial clock line (SCLK), a chip select (CS), and a serial data output (DOUT). The use of serial data output (DOUT) is optional and is only required when data is to be read back by the master device. The MAX11008 is SPI compatible within the range of VDD= +2.7V to +5.25V. DIN, SCLK, CS, and DOUT facilitate bidirectional communication between the MAX11008 and the master at rates up to 20MHz.

Figure 1 illustrates the 4-wire interface timing diagram. The MAX11008 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master initiates data transfer on the bus and generates the SCLK signal to permit data transfer.

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________ 17

Figure 1. SPI Serial-Interface Timing

CSS

SCLK

DIN

DOUT

D23

D22 D1 D0

CSW

CSH

CSS

MAX11008

The SPI bus cycles are 24 bits long. Data can be supplied as three 8-bit bytes or as a continuous 24-bit stream. CS must remain low throughout the 24-bit sequence. The first 8-bit byte is a command byte C[7:0]. The next 16 bits are data bits D[15:0]. Clock signal SCLK can idle low or high, but data is always clocked in on the rising edge of SCLK (CPOL = CPHA).

SPI data transfers begin with the falling edge of CS. Data is clocked into the device on the rising edges of SCLK and clocked out of the device on the falling edges of SCLK. For correct bus cycles, CS should frame the data and should not return to a 1 until after the last active rising clock edge. See Figure 2 for timing details. A rising edge of CS causes DOUT to threestate and data reads should be performed accordingly. See Figures 1 and 3.

When writing instructions to the MAX11008, 24 clock cycles must be completed before CS is driven high. The MAX11008 executes the instruction only after the 24th clock cycle has been received and CS is driven high. To abort unwanted instructions, CS can be driven high at any time before the 23rd rising clock edge.

When reading data from the MAX11008, 24 clock cycles must be completed before CS is driven high. If CS is driven high before the completion of the 24th falling edge, DOUT immediately three-states, the interface resets in preparation for the next command, and the data being read is lost.

Write Format

Use the following sequence to write 16 bits of data to a MAX11008 register (see Figure 2):

1) Drive CS low to select the device.

2) Send the appropriate write command byte (see Table 6 for the register address map). The command byte is clocked in on the rising edge of SCLK.

3) Send 16 bits of data D[15:0] starting with the most significant bit (MSB). Data is clocked in on the rising edges of SCLK.

4) Drive CS high to conclude the command.

Dual RF LDMOS Bias Controller with Nonvolatile Memory

18 ______________________________________________________________________________________

Figure 2. SPI Write Sequence

A RISING EDGE OF CS

DURING THIS PERIOD

COMPLETES A VALID WRITE

COMMAND

SCLK

DIN

C6CR/W- C4C5 C2C3 C0C1

D15D14D13D12D11D10D9D8 D7D6D5D4D3D2D1D0

Read Format

Use the following sequence to read 16 bits of data from a MAX11008 register (see Figure 3):

1) Drive CS low to select the device.

2) Send the appropriate read command byte (see Table 6 for the register address map). The command byte is clocked in on the rising edges of SCLK.

3) Receive 16 bits of data. The first 4 bits of data are always high. Data is clocked out on the falling edges of SCLK.

4) Drive CS high.

I2C Serial Interface

Connect SPI/I2C to DGND to select the I2C interface. The I2C serial interface consists of a serial data line (SDA) and a serial clock line (SCL). The MAX11008 is I2C compatible within the DV

= 2.7V to 5.25V range. SDA and SCL facilitate bidirectional communication between the MAX11008 and the master at rates up to 400kHz for fast mode and up to 3.4MHz for high-speed mode (HS mode). See the

Bus Timing

and

HS I2C Mode

sections

for more information on data-rate configurations.

Figure 4 shows the 2-wire interface timing diagram. The MAX11008 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfers on the bus and generates the SCL signal to permit data transfer.

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________ 19

Figure 3. SPI Read Sequence

Figure 4. I2C Serial-Interface Timing Diagram

SCLK

DIN

DOUT

C6R/W C4C5 C2C3 C0C1

a) F/S-MODE I

SDA

C SERIAL INTERFACE TIMING

SU, DAT

LOW

XXXXXXXXXXXX XXXXX

D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1D15 D7 D0

HD, DAT

SU, STA

HD, STA

SU, ST0

BUF

SCL

HD, STA

b) HS-MODE I

SDA

PARAMETERS ARE MEASURED FROM 30% TO 70%.

C SERIAL INTERFACE TIMING

SU, DAT

LOW

SCL

HD, STA

S Sr A

RCL

HIGH

Sr A

HD, DAT

RCL

SU, STA

HD, STA

SU, ST0

RCL

RDA

BUF

F/S MODEHS MODE

MAX11008

A master device communicates to the MAX11008 by transmitting the proper slave address followed by a command and/or data words. Each transmit sequence is framed by a START (S) or repeated START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.

The MAX11008 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor (750Ω or greater) to generate a logic-high voltage (see the

Typical

Application Circuits

). Series resistors are optional for noise filtering. These series resistors protect the input stages of the MAX11008 from high-voltage spikes on the bus line, and minimize crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the

START

and STOP Conditions

section). Both SDA and SCL idle

high when the I2C bus is not busy.

START and STOP Conditions

The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while

SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (see Figure 5). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the mode unchanged (see the

HS I2C Mode

section).

Acknowledge Bits and Not-Acknowledge Conditions

Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX11008 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth clock pulse) and keep it low during the high period of the clock pulse (see Figure 6).

To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master reattempts communication at a later time.

Dual RF LDMOS Bias Controller with Nonvolatile Memory

20 ______________________________________________________________________________________

Figure 5. START and STOP Conditions

Figure 6. Acknowledge Bits

SSrP

SDA

SCL

S = START. Sr = REPEATED START. P = STOP.

SDA

SCL

12 8

NOT ACKNOWLEDGE

ACKNOWLEDGE

Slave Address

A bus master initiates communication with a slave device by issuing a START condition followed by the 7bit slave address and a read/write (R/W) bit (see Figure

7). When the device recognizes its slave address, it is ready to accept or send data depending on the R/W bit. When the MAX11008 recognizes its slave address, it issues an ACK by pulling SDA low for one clock cycle and is ready to accept or send data depending on the R/W bit that was sent.

The MAX11008 has eight user-selectable slave addresses, which are set through inputs A0, A1, and A2 (see Table 1). This feature allows up to eight MAX11008 devices to share the same bus inputs. The 4 MSBs D[7:4] are factory set, and the 3 LSBs are user-selectable.

Bus Timing

At power-up, the bus timing is set for I2C fast-mode (F/S mode), which allows I2C clock rates up to 400kHz. The MAX11008 can also operate in high-speed mode (HS mode) to achieve I

C clock rates up to 3.4MHz.

See Figure 4 for I2C bus timing.

HS I2C Mode

Select HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the MAX11008 issues a NACK, allowing SDA to be pulled high for one clock cycle (see Figure 8). After the NACK, the MAX11008 operates in HS mode. The master must then send a repeated START (Sr) followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition, the

MAX11008

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________ 21

Figure 7. Slave Address Bits

Figure 8. F/S-Mode to HS-Mode Transfer

Table 1. Slave Address Select

A2 A1 A0 ADDRESS

0 0 0 0101000

0 0 1 0101001

0 1 0 0101010

0 1 1 0101011

1 0 0 0101100

1 0 1 0101101

1 1 0 0101110

1 1 1 0101111

SDA

SCL

SDA

0 0 A2 A1 A0

0000

1234

34 5 67 89

1XXX9A

5678

F/S MODE

R/W A

HS MODE

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