Rainbow Electronics MAX109 User Manual

General Description

The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a highperformance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time.

The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (10

clock

cycles). This design guarantees no missing codes.

The analog input is designed for both differential and single-ended use with a 500mV

P-P

input-voltage range. The output data is in standard LVDS format, and is demultiplexed by an internal 1:4 demultiplexer. The LVDS outputs operate from a supply-voltage range of 3V to 3.6V for compatibility with single 3V-reference systems. Control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate.

The MAX109 is offered in a 256-pin Super Ball-Grid Array (SBGA) package and is specified over the extended industrial temperature range (-40°C to +85°C).

Applications

Radar Warning Receivers (RWR)

Light Detection and Ranging (LIDAR)

Digital RF/IF Signal Processing

Electronic Warfare (EW) Systems

High-Speed Data-Acquisition Systems

Digital Oscilloscopes

High-Energy Physics Instrumentation

ATE Systems

Features

♦ Ultra-High-Speed, 8-Bit, 2.2Gsps ADC

♦ 2.8GHz Full-Power Analog Input Bandwidth

♦ Excellent Signal-to-Noise Performance

44.6dB SNR at f

= 300MHz

44dB SNR at fIN= 1600MHz

♦ Superior Dynamic Range at High-IF

61.7dBc SFDR at f

= 300MHz

50.3dBc SFDR at f

= 1600MHz

-60dBc IM3 at f

IN1

= 1590MHz and f

IN2

= 1610MHz

♦ 500mV

P-P

Differential Analog Inputs

♦ 6.8W Typical Power Including the Demultiplexer

♦ Adjustable Range for Offset, Full-Scale, and

Sampling Instance

♦ 50Ω Differential Analog Inputs

♦ 1:4 Demultiplexed LVDS Outputs

♦ Interfaces Directly to Common FPGAs with DDR

and QDR Modes

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-0795; Rev 0; 4/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

D = Dry pack.

EVALUATION KIT

AVAILABLE

Pin Configuration

PART TEMP RANGE

MAX109EHF-D -40°C to +85°C 256 SBGA H256-1

TOP VIEW

1234567891011121314151617181920

PINPACKAGE

MAX109

256-PIN

SBGA PACKAGE

256-PIN SUPER BALL-GRID ARRAY

PKG

CODE

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

2 _______________________________________________________________________________________

Figure 1. Functional Diagram of the MAX109

RSTOUTA[0:7] B[0:7] C[0:7] D[0:7] DOR DCO

DEMUX

PORTA

PORTB

PORTC

PORTD

DOR

DCO

RESET

OUTPUT

REFIN

REFOUT

REFERENCE AMPLIFIER

BANDGAP

REFERENCE

8-BIT

ADC

CORE

T/H AMPLIFIER

DEMUX CLOCK

GENERATOR

DEMUX CLOCK DRIVER

LOGIC CLOCK DRIVER

QUANTIZER CLOCK DRIVER

DELAYED RESET

RESET

PIPELINE

RESET INPUT

DUAL

LATCH

QDR

DDR

RSTINN RSTINP

INPUT CLOCK BUFFER

50Ω50Ω 50Ω

VOSADJ CLKP CLKCOM

SAMPADJINP INN

50Ω

TEMPERATURE

MONITOR

CLKN

GNDI

TEMPMON

MAX109

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ =

open, digital output pins differential R

= 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by

design and characterization. Typical values are at T

= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VCCA to GNDA ....................................................... -0.3V to +6V

D to GNDD ....................................................... -0.3V to +6V

I to GNDI........................................................... -0.3V to +6V

O to GNDO ................................................... -0.3V to +3.9V

to GNDI ............................................................ -6V to +0.3V

Between Grounds (GNDA, GNDI, GNDO,

GNDD, GNDR) ................................................ -0.3V to +0.3V

A to VCCD ..................................................... -0.3V to +0.3V

A to VCCI ....................................................... -0.3V to +0.3V

Differential Voltage between INP and INN ........................... ±1V

INP, INN to GNDI ................................................................. ±1V

Differential Voltage between CLKP and CLKN..................... ±3V

CLKP, CLKN, CLKCOM to GNDI ............................... -3V to +1V

Digital LVDS Outputs to GNDO .............. -0.3V to (V

O - 0.3V)

REFIN, REFOUT to GNDR ........................-0.3V to (V

I + 0.3V)

REFOUT Current ...............................................-100µA to +5mA

RSTINP, RSTINN to GNDA .....................-0.3V to (V

O + 0.3V)

RSTOUTP, RSTOUTN to GNDO .............-0.3V to (V

O + 0.3V)

VOSADJ, SAMPADJ,

TEMPMON to GNDI...............................-0.3V to (V

I + 0.3V)

PRN, DDR, QDR to GNDD.......................-0.3V to (V

D + 0.3V)

DELGATE0, DELGATE1 to GNDA ...........-0.3V to (V

A + 0.3V)

Continuous Power Dissipation (T

= +70°C) 256-Ball SBGA (derate 74.1mW/°C above +70°C for

a multilayer board) ................................................. 5925.9mW

Operating Temperature Range

MAX109EHF ...................................................-40°C to +85°C

Thermal Resistance θ

(Note 1) .......................................3°C/W

Operating Junction Temperature.....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

_______________________________________________________________________________________ 3

Note 1: Thermal resistance is based on a 5in x 5in multilayer board. The data sheet assumes a thermal environment of 3°C/W.

Thermal resistance may be different depending on airflow and heatsink cooling capabilities.

DC ACCURACY

Resolution RES 8 Bits

Integral Nonlinearity (Note 2) INL (Note 8) -0.8 ±0.25 +0.8 LSB

Differential Nonlinearity (Note 2) DNL

Transfer Curve Offset (Note 2) V

ANALOG INPUTS (INN, INP)

Common-Mode Input-Voltage Range

Common-Mode Rejection Ratio (Note 3)

Full-Scale Input Range (Note 2) V

Input Resistance R

Input Resistance Temperature Coefficient

VOS ADJUST CONTROL INPUT (VOSADJ)

Input Resistance (Note 4) R

Input Offset Voltage V

SAMPLE ADJUST CONTROL INPUT (SAMPADJ)

Input Resistance R

Aperture Time Adjust Range t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SAMPADJ

Guaranteed no missing codes, T (Note 8)

CMRR 50 dB

VOSADJ

VOSADJ control input open (Note 8) -5.5 0 +5.5 LSB

Signal and offset with respect to GNDI ±1 V

= 2.5V 470 500 535 mV

REFIN

VOSADJ = 0V -20 mV

VOSADJ = 2.5V 20 mV

SAMPADJ = 0 to 2.5V 30 ps

= +25°C

-0.8 ±0.25 +0.8 LSB

45 50 55 Ω

150 ppm/°C

25 50 75 kΩ

P-P

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

4 _______________________________________________________________________________________

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ =

open, digital output pins differential R

= 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by

design and characterization. Typical values are at T

= +25°C, unless otherwise noted.)

REFERENCE INPUT AND OUTPUT (REFIN, REFOUT)

Reference Output Voltage REFOUT 2.460 2.500 2.525 V

Reference Output Load Regulation

Reference Input Voltage REFIN

Reference Input Resistance R

CLOCK INPUTS (CLKP, CLKN)

Clock Input Amplitude Peak-to-peak differential (Figure 13b)

Clock Input Common-Mode Range

Clock Input Resistance R

Input Resistance Temperature Coefficient

CMOS CONTROL INPUTS (DDR, QDR, PRN, DELGATE0, DELGATE1)

High-Level Input Voltage V

Low-Level Input Voltage V

High-Level Input Current I

Low-Level Input Current I

LVDS INPUTS (RSTINP, RSTINN)

Differential Input High Voltage 0.2 V

Differential Input Low Voltage -0.2 V

Minimum Common-Mode Input Voltage

Maximum Common-Mode Input Voltage

TEMPERATURE MEASUREMENT OUTPUT (TEMPMON)

Temperature Measurement Accuracy

Output Resistance Measured between TEMPMON and GNDI 0.725 kΩ

LVDS OUTPUTS (PortA, PortB, PortC, PortD, DORP, DORN, DCOP, DCON, RSTOUTP, RSTOUTN) (Note 9)

Differential Output Voltage V

Output Offset Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

∆REFOUT 0 < I

< 2.5mA < 7.5 mV

SOURCE

REFIN

CLK

Signal and offset referenced to CLKCOM -2 to +2 V

CLKP and CLKN to CLKCOM 45 50 55 Ω

Threshold voltage = 1.2V 1.4 3.3 V

Threshold voltage = 1.2V 0.8 V

= 3.3V 50 µA

= 0V -50 µA

T (°C) = [(V 371

LOAD

TEMPMON

= 100Ω 250 400 mV

= 100Ω 1.10 1.28 V

- V

GNDI

) x 1303.5] -

45 kΩ

2.500 ± 0.25

200 to

2000

150 ppm/°C

O -

C C

0.15

±7 °C

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

_______________________________________________________________________________________ 5

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ =

open, digital output pins differential R

= 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by

design and characterization. Typical values are at T

= +25°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.2Gsps, analog input

amplitude at -1dBFS differential, clock input amplitude 400mV

P-P

differential, digital output pins differential RL= 100Ω. Typical values

are at T

= +25°C, unless otherwise noted.)

POWER REQUIREMENTS

Analog Supply Current IVCCA 556 744 mA

Positive Input Supply Current IVCCI 125 168 mA Negative Input Supply Current IIV

Digital Supply Current IVCCD 291 408 mA

Output Supply Current IVCCO 222 300 mA

Power Dissipation P

Positive Power-Supply Rejection Ratio

Negative Power-Supply Rejection Ratio

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PSRRP (Note 5) 50 dB

PSRRN V

I 181 240 mA

DISS

= -5.25V to -4.75V 50 dB

6.50 8.79 W

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT

Analog Input Full-Power Bandwidth (Note 6)

Gain Flatness GF 1100MHz to 2200MHz ±0.3 dB

DYNAMIC SPECIFICATIONS

Signal-to-Noise Ratio

Total H ar m oni c D i st or ti on ( N ote 7)

SNR

THD

-3dB

300fIN

1000fIN

1600fIN

2500fIN

500fIN

1600fIN

300fIN

1000fIN

1600fIN

2500fIN

500fIN

1600fIN

= 300MHz, f

= 1000MHz, f

= 1600MHz, f

= 2500MHz, f

= 500MHz, f

= 1600MHz, f

= 300MHz, f

= 1000MHz, f

= 1600MHz, f

= 2500MHz, f

= 500MHz, f

= 1600MHz, f

= 2.2Gsps 44.6

CLK

= 2.2Gsps (Note 8) 43.6 44.5

CLK

= 2.2Gsps (Note 8) 42.2 44.0

CLK

= 2.2Gsps 42.9

CLK

= 2.5Gsps 44.4

CLK

= 2.5Gsps 44.0

CLK

= 2.2Gsps -55.6

CLK

= 2.2Gsps (Note 8) -48.5 -42.5

CLK

= 2.2Gsps (Note 8) -46.6 -39.6

CLK

= 2.2Gsps -43.7

CLK

= 2.5Gsps -49.0

CLK

= 2.5Gsps -43.1

CLK

2.8 GHz

dBc

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

6 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.2Gsps, analog input

amplitude at -1dBFS differential, clock input amplitude 400mV

P-P

differential, digital output pins differential RL= 100Ω. Typical values

are at T

= +25°C, unless otherwise noted.)

)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Spurious Free Dynamic Range

Signal-to-Noise-Plus-Distortion Ratio

SFDR

SINAD

300fIN

1000fIN

1600fIN

2500fIN

500fIN

1600fIN

300fIN

1000fIN

1600fIN

2500fIN

500fIN

1600fIN

Third-Order Intermodulation IM3 f

= 300MHz, f

= 1000MHz, f

= 1600MHz, f

= 2500MHz, f

= 500MHz, f

= 1600MHz, f

= 300MHz, f

= 1000MHz, f

= 1600MHz, f

= 2500MHz, f

= 500MHz, f

= 1600MHz, f

= 1590MHz, f

IN1

= 2.2Gsps 61.7

CLK

= 2.2Gsps (Note 8) 44.4 51.1

CLK

= 2.2Gsps (Note 8) 43.7 50.3

CLK

= 2.2Gsps 45.0

CLK

= 2.5Gsps 53.7

CLK

= 2.5Gsps 44.6

CLK

= 2.2Gsps 44.1

CLK

= 2.2Gsps (Note 8) 40.4 43.1

CLK

= 2.2Gsps (Note 8) 37.9 42.1

CLK

= 2.2Gsps 40.1

CLK

= 2.5Gsps 43.1

CLK

= 2.5Gsps 40.5

CLK

= 1610MHz at -7dBFS -60 dBc

IN2

Metastability Probability 10

TIMING CHARACTERISTICS

Maximum Sample Rate f

Clock Pulse-Width Low t

Clock Pulse-Width High t

Aperture Delay t

Aperture Jitter t

Reset Input Data Setup Time t

Reset Input Data Hold Time t

CLK-to-DCO Propagation Delay

DCO-to-Data Propagation Delay

CLK(MAX

PWL

PWH

PD1

PD1DDR

PD1QDR

PD2

PD2DDR

PD2QDR

= t

+ t

CLK

= t

PWL

(Note 8) 180 ps

PWH

+ t

(Note 8) 180 ps

PWH

(Note 8) 300 ps

(Note 8) 250 ps

DCO = f

/ 4, CLK fall to DCO rise time 1.6

CLK

/ 8, DDR mode, CLK fall to

CLK

DCO rise time

DCO = f

/ 16, QDR mode, CLK fall to

CLK

DCO rise time

DCO = f

/ 4, DCO rise to data transition

CLK

(Note 8)

DCO = f

/ 8, DDR mode, DCO rise to

CLK

data transition (Note 8)

DCO = f

/ 16, QDR mode, DCO rise to

CLK

data transition (Note 8)

DCO Duty Cycle Clock mode independent

2.2 Gsps

-520 +520

-520 + 2t

CLK

-520 + 2t

CLK

dBc

-14

200 ps

0.2 ps

1.6 ns

1.6

CLK

520 + 2t

CLK

520 + 2t

CLK

45 to

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

_______________________________________________________________________________________ 7

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.2Gsps, analog input

amplitude at -1dBFS differential, clock input amplitude 400mV

P-P

differential, digital output pins differential RL= 100Ω. Typical values

are at T

= +25°C, unless otherwise noted.)

Note 2: Static linearity and offset parameters are computed from a

best-fit

straight line through the code transition points. The fullscale range (FSR) is defined as 255 x slope of the line where the slope of the line is determined by the end-point code transitions. When the analog input voltage exceeds positive FSR, the output code is 11111111; when the analog input voltage is beyond the negative FSR, the output code is 00000000.

Note 3: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the

common-mode voltage, expressed in dB.

Note 4: The offset-adjust control input is tied to an internal 1.25V reference level through a resistor. Note 5: Measured with the positive supplies tied to the same potential, V

A = VCCD = VCCI. VCCvaries from 4.75V to 5.25V.

Note 6: To achieve 2.8GHz full-power bandwidth, careful board layout techniques are required. Note 7: The total harmonic distortion (THD) is computed from the second through the 15th harmonics. Note 8: Guaranteed by design and characterization. Note 9: RSTOUTP/RSTOUTN are tested for functionality.

Typical Operating Characteristics

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.21184Gsps, analog

input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential R

= 100Ω. Typical

values are at T

= +105°C, unless otherwise noted.)

-90

-70

-80

-40

-50

-60

-10

-20

-30

FFT PLOT (16,384-POINT DATA RECORD)

MAX109 toc02

AMPLITUDE (dB)

CLK

= 2.21184GHz

= 300.105MHz

= -1.034dBFS SNR = 45.1dB SINAD = 44.8dB THD = -56.2dBc SFDR = 62.4dBc HD2 = -64.4dBc HD3 = -62.7dBc

0 552.96276.48 829.44 1105.92

414.72138.24 691.20 967.68

ANALOG INPUT FREQUENCY (MHz)

-90

-70

-80

-40

-50

-60

-10

-20

-30

0 552.96276.48 829.44 1105.92

414.72138.24 691.20 967.68

FFT PLOT (16,384-POINT DATA RECORD)

MAX109 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CLK

= 2.21184GHz

= 98.145MHz

= -0.975dBFS SNR = 45.2dB SINAD = 44.8dB THD = -55.7dBc SFDR = 57.2dBc HD2 = -69.6dBc HD3 = -57.2dBc

-90

-70

-80

-40

-50

-60

-10

-20

-30

FFT PLOT (16,384-POINT DATA RECORD)

MAX109 toc03

AMPLITUDE (dB)

CLK

= 2.21184GHz

= 999.135MHz

= -1.059dBFS SNR = 44.5dB SINAD = 43.3dB THD = -49.5dBc SFDR = 52.1dBc HD2 = -57.3dBc HD3 = -52.1dBc

0 552.96276.48 829.44 1105.92

414.72138.24 691.20 967.68

ANALOG INPUT FREQUENCY (MHz)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LVDS Output Rise Time t

LVDS Output Fall Time t

LVDS Differential Skew t

PortD Data Pipeline Delay t

PortC Data Pipeline Delay t

PortB Data Pipeline Delay t

PortA Data Pipeline Delay t

RDATA

FDATA

SKEW1

PDD

PDC

PDB

PDA

20% to 80%, CL < 2pF 500 ps

Any two LVDS output signals, except DCO <100 ps

7.5

8.5

9.5

10.5

Clock

Cycles

Clock

Cycles

Clock

Cycles

Clock

Cycles

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

8 _______________________________________________________________________________________

HD2

HD3

(dB

)

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.21184Gsps, analog

input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential R

= 100Ω. Typical

values are at TJ = +105°C, unless otherwise noted.)

-90

-70

-80

-40

-50

-60

-10

-20

-30

FFT PLOT (16,384-POINT DATA RECORD)

MAX109 toc04

AMPLITUDE (dB)

CLK

= 2.21184GHz fIN = 1600.155MHz A

= -0.992dBFS SNR = 44.2dB SINAD = 42.6dB THD = -47.5dBc SFDR = 51.1dBc HD2 = -51.1dBc HD3 = -52.1dBc

0 552.96276.48 829.44 1105.92

414.72138.24 691.20 967.68

ANALOG INPUT FREQUENCY (MHz)

SNR, SINAD vs. ANALOG INPUT FREQUENCY

= 2.21184Gsps, AIN = -1dBFS)

CLK

FFT PLOT (16,384-POINT DATA RECORD)

-10

-20

-30

-40

-50

AMPLITUDE (dB)

-60

-70

-80

-90

= 2.49856GHz

CLK

= 1599.268MHz

AIN = -1.059dBFS SNR = 44.1dB SINAD = 41.2dB THD = -44.4dBc SFDR = 46.1dBc HD2 = -50.1dBc HD3 = -46.1dBc

0 624.64312.32 936.96 1249.28

468.48156.16 780.8 1098.12

ANALOG INPUT FREQUENCY (MHz)

MAX109 toc05

AMPLITUDE (dB)

ENOB vs. ANALOG INPUT FREQUENCY

= 2.21184Gsps, AIN = -1dBFS)

CLK

8.0

TTIMD PLOT (16,384-POINT DATA RECORD)

= 2.21184GHz

CLK

-10 = 1590.165MHz

IN1

= 1610.415MHz

IN2

-20

-30

-40

-50

-60

-70

-80

-90

= A

IN1

IN2

IM3 = -60.8dBc

0 552.96276.48 829.44 1105.92

ANALOG INPUT FREQUENCY (MHz)

-THD, SFDR vs. ANALOG INPUT FREQUENCY = 2.21184Gsps, AIN = -1dBFS)

CLK

= -7.13dBFS

- f

IN2

IN1

414.72138.24 691.20 967.68

- f

IN1

IN2

MAX109 toc06

SNR, SINAD (dB)

0 500 1000 1500 2000 2500

HD2, HD3 vs. ANALOG INPUT FREQUENCY

= 2.21184Gsps, AIN = -1dBFS)

CLK

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80 0 500 1000 1500 2000 2500

SINAD

fIN (MHz)

HD3

fIN (MHz)

HD2

SNR

MAX109 toc07

MAX109 toc10

7.5

7.0

6.5

ENOB (Bits)

6.0

5.5

5.0 0 500 1000 1500 2000 2500

fIN (MHz)

SNR, SINAD vs. ANALOG INPUT FREQUENCY

= 2.49856Gsps, AIN = -1dBFS)

CLK

SNR

SNR, SINAD (dB)

0 500 1000 1500 2000 2500

SINAD

fIN (MHz)

MAX109 toc08

MAX109 toc11

-THD, SFDR (dBc)

0 500 1000 1500 2000 2500

SFDR

-THD

fIN (MHz)

ENOB vs. ANALOG INPUT FREQUENCY

= 2.49856Gsps, AIN = -1dBFS)

CLK

8.0

7.5

7.0

6.5

ENOB (Bits)

6.0

5.5

5.0 0 500 1000 1500 2000 2500

fIN (MHz)

MAX109 toc09

MAX109 toc12

MAX109

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, V

= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.21184Gsps, analog

input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential R

= 100Ω. Typical

values are at TJ = +105°C, unless otherwise noted.)

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

_______________________________________________________________________________________

-THD, SFDR vs. ANALOG INPUT FREQUENCY = 2.49856Gsps, AIN = -1dBFS)

CLK

-THD, SFDR (dBc)

0 500 1000 1500 2000 2500

SFDR

-THD

fIN (MHz)

ENOB vs. ANALOG INPUT AMPLITUDE

= 2.21184Gsps, fIN = 1600.1550MHz)

CLK

8.0

7.5

7.0

6.5

ENOB (Bits)

6.0

5.5

5.0

-45 -40 -35 -30 -25 -20 -15 -10 -5 0 AIN (dBFS)

HD2, HD3 vs. ANALOG INPUT FREQUENCY

= 2.49865Gsps, AIN = -1dBFS)

CLK

-30

MAX109 toc13

-35

-40

-45

-50

-55

-60

HD2, HD3 (dBc)

-65

-70

-75

-80 0 500 1000 1500 2000 2500

HD3

HD2

fIN (MHz)

MAX109 toc14

SNR, SINAD (dB)

-THD, SFDR vs. ANALOG INPUT AMPLITUDE = 2.21184Gsps, fIN = 1600.1550MHz)

CLK

MAX109 to16

-THD, SFDR (dBc)

-45 -40 -35 -30 -25 -20 -15 -10 -5 0

SFDR

-THD

AIN (dBFS)

MAX109 toc17

HD2, HD3 (dBc)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

= 2.21184Gsps, fIN = 1600.1550MHz)

CLK

-45 -40 -35 -30 -25 -20 -15 -10 -5 0

HD2, HD3 vs. ANALOG INPUT AMPLITUDE

= 2.21184Gsps, fIN = 1600.1550MHz)

CLK

-20

-25

-30

-35

-40

-45

-50

-55

-60

-65

-70

-45 -40 -35 -30 -25 -20 -15 -10 -5 0

AIN (dBFS)

HD3

HD2

AIN (dBFS)

SNR

MAX109 toc15

SINAD

MAX109 toc18

SNR, SINAD vs. CLOCK SPEED

= 1600MHz, AIN = -1dBFS)

SNR, SINAD (dB)

SNR

SINAD

500 750 1000 1250 1500 1750 2000 2250 2500

(MHz)

CLK

MAX109 toc19

ENOB vs. CLOCK SPEED = 1600MHz, AIN = -1dBFS)

8.0

7.5

7.0

6.5

ENOB (Bits)

6.0

5.5

5.0

500 750 1000 1250 1500 1750 2000 2250 2500

(MHz)

CLK

MAX109 toc20

-THD, SFDR vs. CLOCK SPEED = 1600MHz, AIN = -1dBFS)

-THD, SFDR (dBc)

SFDR

-THD

500 750 1000 1250 1500 1750 2000 2250 2500

(MHz)

CLK

MAX109 toc21

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