Rainbow Electronics MAX1081 User Manual

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General Description

The MAX1080/MAX1081 10-bit analog-to-digital convert­ers (ADCs) combine an 8-channel analog-input multiplex­er, high-bandwidth track/hold (T/H), and serial interface
with high conversion speed and low power consumption.
The MAX1080 operates from a single +4.5V to +5.5V sup­ply; the MAX1081 operates from a single +2.7V to +3.6V
supply. Both devices’ analog inputs are software config­urable for unipolar/bipolar and single-ended/pseudo-dif­ferential operation.

The 4-wire serial interface connects directly to
SPI™/QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1080/
MAX1081 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref­erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to V

DD1

range may

also be used.
The MAX1080/MAX1081 provide a hard-wired SHDN pin

and four software-selectable power modes (normal opera­tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn­on time allows them to be shut down between all conver­sions. This technique can cut supply current below 100mA
at lower sampling rates.

The MAX1080/MAX1081 are available in a 20-pin TSSOP
package. These devices are higher-speed versions of the
MAX148/MAX149. For more information, refer to the
respective data sheet.

Applications

Portable Data Logging

Data Acquisition

Medical Instruments

Battery-Powered Instruments

Pen Digitizers

Process Control

Features

♦ 8-Channel Single-Ended or 4-Channel

Pseudo-Differential Inputs

♦ Internal Multiplexer and Track/Hold

♦ Single-Supply Operation

+4.5V to +5.5V (MAX1080)

+2.7V to +3.6V (MAX1081)

♦ Internal +2.5V Reference

♦ 400ksps Sampling Rate (MAX1080)

♦ Low Power: 2.5mA (400ksps)

1.3mA (REDP)

0.9mA (FASTPD)

2µA (FULLPD)

♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire

Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs

♦ 20-Pin TSSOP Package

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

19-1685; Rev 0; 5/00

PART

MAX1080ACUP

MAX1080BCUP
MAX1080AEUP -40°C to +85°C

0°C to +70°C

0°C to +70°C

TEMP.

RANGE

PIN­PACKAGE

20 TSSOP

20 TSSOP
20 TSSOP

Typical Operating Circuit appears at end of data sheet.

Pin Configuration

INL

(LSB)

±1/2

±1

±1/2

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Ordering Information continued at end of data sheet.

Ordering Information

CH0

1

2

CH1

3

CH2

CH3

4

5

CH4

6

CH5

CH6

7

8

CH7

9

10

MAX1080
MAX1081

TSSOP

TOP VIEW

COM

SHDN

20

V

DD1

V

19

DD2

SCLK

18

CS

17

16

DIN

SSTRB

15

DOUT

14

13

GND

REFADJ

12

11

REF

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX1080

(V

DD1

= V

DD2

= +4.5V to +5.5V, COM = GND, f

SCLK

= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

V

DD_

to GND .............................................................. -0.3V to 6V

V

DD1

to V

DD2

......................................................... -0.3V to 0.3V

CH0–CH7, COM to GND.......................... -0.3V to (V

DD1

+ 0.3V)

REF, REFADJ to GND .............................. -0.3V to (V

DD1

+ 0.3V)

Digital Inputs to GND................................................. -0.3V to 6V

Digital Outputs to GND ............................ -0.3V to (V

DD2

+ 0.3V)

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (T

A

= +70°C)

20-Pin TSSOP (derate 7.0mW/°C above +70°C) ........ 559mW

Operating Temperature Ranges

MAX108_ _CUP ................................................. 0°C to +70°C

MAX108_ _EUP............................................... -40°C to +85°C

Storage Temperature Range ............................ -60°C to +150°C

Lead Temperature (soldering, 10s) ................................ +300°C

MAX1080A

SINAD > 58dB

-3dB point

f

IN

= 200kHz, VIN= 2.5Vp-p

f

IN1

= 99kHz, f

IN2

=102kHz

MAX1080B

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

MHz

0.5 6.4

f

SCLK

Serial Clock Frequency

ps

<50

Aperture Jitter

ns

10

Aperture Delay

ns

468

t

ACQ

Track/Hold Acquisition Time

µs

2.5

t

CONV

Conversion Time (Note 5)

kHz

350

Full-Linear Bandwidth

MHz

6

Full-Power Bandwidth

dB

-78

Channel-to-Channel Crosstalk
(Note 4)

dB

76

IMDIntermodulation Distortion

dB

70

SFDRSpurious-Free Dynamic Range

dB

-70

THDTotal Harmonic Distortion

LSB

±0.5

INLRelative Accuracy (Note 2)

Bits

10

Resolution

dB

60

SINAD

Signal-to-Noise plus Distortion
Ratio

LSB

±0.1

Channel-to-Channel Offset-Error
Matching

ppm/°C

±0.8

Gain-Error Temperature
Coefficient

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±3.0

Offset Error

LSB

±3.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

%

40 60

Duty Cycle

DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)

DC ACCURACY (Note 1)

CONVERSION RATE

mA

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX1080 (continued)

(V

DD1

= V

DD2

= +4.5V to +5.5V, COM = GND, f

SCLK

= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 1mA output load

On/off leakage current, V

CH_

= 0 or V

DD1

TA= +25°C

Bipolar, V

COM

or V

CH_

= V

REF

/2, referenced

to COM or CH_

Unipolar, V

COM

= 0

V/V

+2.05

Buffer Voltage Gain

V

1.4 V

DD1

- 1.0

REFADJ Buffer Disable
Threshold

mV

±100

REFADJ Input Range

V

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC V

REF

REF Output Temperature
Coefficient

mA

30

REF Short-Circuit Current

V

2.480 2.500 2.520

V

REF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±V

REF

/2

V

V

REF

V

CH_

Input Voltage Range, Single
Ended and Differential (Note 6)

VIN= 0 or V

DD2

In power-down mode, f

SCLK

= 0

V

REF

= 2.500V, f

SCLK

= 0

V

REF

= 2.500V, f

SCLK

= 6.4MHz

(Note 8)

pFC

IN

Input Capacitance

µA±1I

IN

Input Leakage

V0.2V

HYST

Input Hysteresis

V0.8V

INL

Input Low Voltage

V3.0V

INH

Input High Voltage

5

320

µA

200 350

REF Input Current

V

1.0 V

DD1

+

50mV

REF Input Voltage Range

I

SINK

= 5mA V0.4V

OL

Output Voltage Low

15

I

SOURCE

= 1mA V4V

OH

Output Voltage High

CS = 5V

µA±10I

L

Three-State Leakage Current

CS = 5V

pF15C

OUT

Three-State Output Capacitance

ANALOG INPUTS (CH7–CH0, COM)

EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)

INTERNAL REFERENCE

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

DIGITAL OUTPUTS (DOUT, SSTRB)

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

4 _______________________________________________________________________________________

V

DD1

=

V

DD2

=

5.5V

V

DD1

= V

DD2

= 5V ±10%, midscale input

CONDITIONS

mA

2.5 4.0

I

VDD1+

I

VDD2

Supply Current

V4.5 5.5

V

DD1,

V

DD2

Positive Supply Voltage
(Note 9)

1.3 2.0

0.9 1.5
µA

210

mV±0.5 ±2.0PSRPower-Supply Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

Normal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)

ELECTRICAL CHARACTERISTICS—MAX1080 (continued)

(V

DD1

= V

DD2

= +4.5V to +5.5V, COM = GND, f

SCLK

= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

ELECTRICAL CHARACTERISTICS—MAX1081

(V

DD1

= V

DD2

= +2.7V to +3.6V, COM = GND, f

SCLK

= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

MAX1081A

SINAD > 58dB

-3dB point

fIN= 150kHz, VIN= 2.5Vp-p

f

IN1

= 73kHz, f

IN2

= 77kHz

MAX1081B

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

kHz

250

Full-Linear Bandwidth

MHz

3

Full-Power Bandwidth

dB

-78

Channel-to-Channel Crosstalk
(Note 4)

dB

76

IMDIntermodulation Distortion

dB

70

SFDRSpurious-Free Dynamic Range

dB

-70

THDTotal Harmonic Distortion

LSB

±0.5

INLRelative Accuracy (Note 2)

Bits

10

Resolution

dB

60

SINAD

Signal-to-Noise plus Distortion
Ratio

LSB

±0.2

Channel-to-Channel Offset-Error
Matching

ppm/°C

±1.6

Gain-Error Temperature
Coefficient

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±3.0

Offset Error

LSB

±3.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

POWER SUPPLY

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS—MAX1081 (continued)

(V

DD1

= V

DD2

= +2.7V to +3.6V, COM = GND, f

SCLK

= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Normal operating mode

Normal operating mode

Normal operating mode

CONDITIONS

MHz

0.5 4.8

f

SCLK

Serial Clock Frequency

ps

<50

Aperture Jitter

ns

10

Aperture Delay

ns

625

t

ACQ

Track/Hold Acquisition Time

µs

3.3

t

CONV

Conversion Time (Note 5)

UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 0.75mA output load

On/off leakage current, V

CH_

= 0 or V

DD1

TA= +25°C

Bipolar, V

COM

or V

CH_

= V

REF

/2,

referenced to COM or CH_

Unipolar, V

COM

= 0

V/V

2.05

Buffer Voltage Gain

V

1.4 V

DD1

- 1

REFADJ Buffer Disable
Threshold

mV

±100

REFADJ Input Range

V

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC V

REF

REF Output Temperature
Coefficient

mA

15

REF Short-Circuit Current

V

2.480 2.500 2.520

V

REF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±V

REF

/2

%

40 60

Duty Cycle

V

V

REF

V

CH_

Input Voltage Range, Single
Ended and Differential (Note 6)

VIN= 0 or V

DD2

In power-down mode, f

SCLK

= 0

V

REF

= 2.500V, f

SCLK

= 0

V

REF

= 2.500V, f

SCLK

= 4.8MHz

(Note 8)

pF

15

C

IN

Input Capacitance

µA

±1

I

IN

Input Leakage

V

0.2

V

HYST

Input Hysteresis

V

0.8

V

INL

Input Low Voltage

V

2.0

V

INH

Input High Voltage

5

REF Input Current

320

µA

200 350

V

1.0 V

DD1

+

50mV

REF Input Voltage Range

V/V

+2.05

Buffer Voltage Gain

CONVERSION RATE

ANALOG INPUTS (CH7–CH0, COM)

INTERNAL REFERENCE

EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

6 _______________________________________________________________________________________

V

DD1

=

V

DD2

=

3.6V

I

SOURCE

= 0.5mA

V

DD1

= V

DD2

= 2.7V to 3.6V, midscale input

CONDITIONS

mA

2.5 3.5

I

VDD1

+

I

VDD2

Supply Current

V2.7 3.6

V

DD1,

V

DD2

VV

DD2

- 0.5VV

OH

Output Voltage High

Positive Supply Voltage
(Note 9)

1.3 2.0

Normal operating mode (Note 10)
Reduced-power mode (Note 11)

0.9 1.5

Fast power-down mode (Note 11)
Full power-down mode (Note 11) µA

210

mV±0.5 ±2.0PSRPower-Supply Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

I

SINK

= 5mA V0.4V

OL

Output Voltage Low

CS = 3V

µA±10I

L

Three-State Leakage Current

CS = 3V

pF15C

OUT

Three-State Output Capacitance

ELECTRICAL CHARACTERISTICS—MAX1081 (continued)

(V

DD1

= V

DD2

= +2.7V to +3.6V, COM = GND, f

SCLK

= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = V

DD1

, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

TIMING CHARACTERISTICS–MAX1080

(Figures 1, 2, 6, 7; V

DD1

= V

DD2

= +4.5V to +5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted.)

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

CONDITIONS

ns

100

t

CSW

CS Pulse Width High

ns

65

t

STE

CS Fall to SSTRB Enable

ns

65

t

DOE

CS Fall to DOUT Enable

ns

10 65

t

STD

CS Rise to SSTRB Disable

ns

10 65

t

DOD

CS Rise to DOUT Disable

ns

80

t

STV

SCLK Rise to SSTRB Valid

ns

80

t

DOV

SCLK Rise to DOUT Valid

ns

62

t

CL

SCLK Pulse Width Low

ns

62

t

CH

ns

156

t

CP

SCLK Period

SCLK Pulse Width High

ns

10 20

t

STH

SCLK Rise to SSTRB Hold

ns

10 20

t

DOH

SCLK Rise to DOUT Hold

ns

35

t

CS1

CS Rise to SCLK Rise Ignore

ns

35

t

CSO

SCLK Rise to CS Fall Ignore

ns

35

t

DS

DIN to SCLK Setup

ns

0

t

DH

DIN to SCLK Hold

ns

35

t

CSS

CS Fall to SCLK Rise Setup

ns

0

t

CSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER SUPPLY

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 7

TIMING CHARACTERISTICS—MAX1081

(Figures 1, 2, 6, 7; V

DD1

= V

DD2

= +2.7V to +3.6V, TA= T

MIN

to T

MAX

, unless otherwise noted.)

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

C

LOAD

= 20pF

CONDITIONS

ns

100

t

CSW

CS Pulse Width High

ns

85

t

STE

CS Fall to SSTRB Enable

ns

85

t

DOE

CS Fall to DOUT Enable

ns

13 85

t

STD

CS Rise to SSTRB Disable

ns

13 85

t

DOD

CS Rise to DOUT Disable

ns

100

t

STV

SCLK Rise to SSTRB Valid

ns

100

t

DOV

SCLK Rise to DOUT Valid

ns

83

t

CL

SCLK Pulse Width Low

ns

83

t

CH

ns

208

t

CP

SCLK Period

SCLK Pulse Width High

ns

13 20

t

STH

SCLK Rise to SSTRB Hold

ns

13 20

t

DOH

SCLK Rise to DOUT Hold

ns

45

t

CS1

CS Rise to SCLK Rise Ignore

ns

45

t

CSO

SCLK Rise to CS Fall ignore

ns

45

t

DS

DIN to SCLK Setup

ns

0

t

DH

DIN to SCLK Hold

ns

45

t

CSS

CS Fall to SCLK Rise Setup

ns

0

t

CSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

Note 1: Tested at V

DD1

= V

DD2

= V

DD(MIN)

, COM = GND, unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Offset nulled.
Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH7–CH0 and COM) is from GND to V

DD1

.

Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is the

result of production test limitations.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Electrical characteristics are guaranteed from V

DD1(MIN)

= V

DD2(MIN)

to V

DD1(MAX)

= V

DD2(MIN)

. For operations beyond

this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.

Note 10: AIN= midscale. Unipolar mode. MAX1080 tested with 20pF on DOUT, 20pF on SSTRB, and f

SCLK

= 6.4MHz, 0 to 5V.

MAX1081 tested with same loads, f

SCLK

= 4.8MHz, 0 to 3V.

Note 11: SCLK = DIN = GND, CS = V

DD1

.

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

8 _______________________________________________________________________________________

Typical Operating Characteristics

(MAX1080: V

DD1

= V

DD2

= 5.0V, f

SCLK

= 6.4MHz; MAX1081: V

DD1

= V

DD2

= 3.0V, f

SCLK

= 4.8MHz; C

LOAD

= 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, T

A

= +25°C, unless otherwise noted.)

-0.04

-0.08

0

0.08

0.12

0

400200 600 800 1000

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1080/1-01

DIGITAL OUTPUT CODE

INL (LSB)

1200

0.04

-0.05

-0.10

0

0.05

0.10

0 400

200

600

800

1000

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1080/1-02

DIGITAL OUTPUT CODE

DNL (LSB)

1200

-0.15

0.15

3.5

3.0

2.5

2.0

1.5

2.5 4.03.0 3.5 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (CONVERTING)

MAX1080/1-03

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

2.0

2.4

2.2

2.8

2.6

3.0

3.2

-40 20 40-20 0 60 80 100

SUPPLY CURRENT vs. TEMPERATURE

MAX1080/1-04

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1081

MAX1080

NORMAL OPERATION (PD1 = PD0 = 1)

REDP (PD1 = 1, PD0 = 0)

FASTPD (PD1 = 0, PD0 = 1)

0

0.5

1.5

1.0

2.0

2.5

2.5 3.53.0 4.0 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (STATIC)

MAX1080/1-05

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0

0.5

1.5

1.0

2.0

2.5

-40 0-20 20 40 60 80 100

SUPPLY CURRENT vs. TEMPERATURE

(STATIC)

MAX1080/1-06

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1080 (PD1 = 1, PD0 = 1)

MAX1080 (PD1 = 1, PD0 = 0)

MAX1080 (PD1 = 0, PD0 = 1)

MAX1081 (PD1 = 1, PD0 = 1)

MAX1081 (PD1 = 1, PD0 = 0)

MAX1081 (PD1 = 0, PD0 = 1)

0

0.5

1.5

1.0

2.0

2.5

2.5 3.53.0 4.0 4.5 5.0 5.5

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1080/1-07

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

(PD1 = PD0 = 0)

0

0.5

1.5

1.0

2.0

2.5

-40 0-20 20 40 60 80 100

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX1080/1-08

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

MAX1081

MAX1080

(PD1 = PD0 = 0)

2.4995

2.4997

2.5001

2.4999

2.5003

2.5005

2.5 3.53.0 4.0 4.5 5.0 5.5

REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE

MAX1080/1-09

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(MAX1080: V

DD1

= V

DD2

= 5.0V, f

SCLK

= 6.4MHz; MAX1081: V

DD1

= V

DD2

= 3.0V, f

SCLK

= 4.8MHz; C

LOAD

= 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)

REFERENCE VOLTAGE vs. TEMPERATURE

2.5002

2.5000

2.4998

2.4996

2.4994

2.4992

REFERENCE VOLTAGE (V)

2.4990

2.4988

-40 0 20-20 40 60 80 100

MAX1080

MAX1081

TEMPERATURE (°C)

GAIN ERROR vs. SUPPLY VOLTAGE

0.25

0

MAX1080/1-10

-0.25

OFFSET ERROR (LSB)

-0.50

OFFSET ERROR vs. SUPPLY VOLTAGE

0

2.7 3.33.0 3.6
VDD (V)

MAX1080/1-13

OFFSET ERROR vs. TEMPERATURE

0

MAX1080/1-11

-0.25

OFFSET ERROR (LSB)

-0.50

-40 10-15 35 60 85

MAX1081

GAIN ERROR vs. TEMPERATURE

0

MAX1080/1-12

TEMPERATURE (°C)

MAX1080/1-14

-0.25

GAIN ERROR (LSB)

-0.50

-0.75

2.7 3.33.0 3.6
VDD (V)

-0.25

GAIN ERROR (LSB)

-0.50

-40 10-15 35 60 85

TEMPERATURE (°C)

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

Pin Description

Positive Supply VoltageV

DD2

19

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
V

DD1

.

REFADJ12

Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped­ance when CS is high.

SSTRB15

Serial Data Input. Data is clocked in at SCLK’s rising edge.DIN16

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.

CS

17

Serial Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)

SCLK18

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a 2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
V

DD1

.

REF11

Analog and Digital GroundGND13

Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.

DOUT14

Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).

SHDN

10

Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.

COM9

PIN

Sampling Analog InputsCH0–CH71–8

FUNCTIONNAME

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

Positive Supply VoltageV

DD1

20

DOUT

6k

a) High-Z to V

GND

and VOL to V

OH

V

DD2

DOUT

C

LOAD

20pF

OH

b) High-Z to VOL and VOH to V

6k

C

LOAD

20pF

GND

OL

DOUT

DOUT

C

6k

GND

a) V

to High-Z b) VOL to High-Z

OH

LOAD

20pF

V

DD2

6k

C

LOAD

20pF

GND

Detailed Description

The MAX1080/MAX1081 ADCs use a successive­approximation conversion technique and input T/H cir­cuitry to convert an analog signal to a 10-bit digital out­put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia­gram of the MAX1080/MAX1081.

Pseudo-Differential Input

The equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched­capacitor DAC, and reference.

In single-ended mode, the positive input (IN+) is con­nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.

The MAX1080/MAX1081 input configuration is pseudo­differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.

If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation­ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a

sinusoidal signal at IN-, the input voltage is determined
by:

The maximum voltage variation is determined by:

A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a

2.5µs conversion time (15 / f

SCLK

). When a DC refer­ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C

HOLD

. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
C

HOLD

as a sample of the signal at IN+. The conver­sion interval begins with the input multiplexer switching
C

HOLD

from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V

DD1

/2 within the limits of 10-bit resolu­tion. This action is equivalent to transferring a
12pF ✕[(VIN+ - VIN-)] charge from C

HOLD

to the binary­weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Figure 3. Functional Diagram

Figure 4. Equivalent Input Circuit

()

17

CS

18

SCLK

DIN

SHDN

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

COM

REFADJ

REF

INPUT

16

SHIFT

REGISTER

10

1
2
3
4

ANALOG

INPUT

5

MUX

6
7
8

9

12

11

+1.22V

REFERENCE

CONTROL

LOGIC

T/H

17k

IN

≈

A

+2.500V

INT

CLOCK

CLOCK

10 + 2-BIT

SAR ADC

REF

2.05

OUTPUT

REGISTER

OUT

MAX1080
MAX1081

SHIFT

14

DOUT

15

SSTRB

20

V

DD1

19

V

DD2

13

GND

νπ

max

ν

d

IN

−

=

dt

V sin(2 ft)

=

IN IN

−−

1LSB

π

V2f

()

IN

≤=

−

t

CONV

V

REF

10

2t

CONV

GND

CAPACITIVE

6pF

C

HOLD

12pF

HOLD

DAC

ZERO

R

IN

800Ω

TRACK

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.

V

DD1

COMPARATOR

/2

REF

INPUT
MUX

CH0
CH1

CH2
CH3
CH4
CH5

CH6
CH7

COM

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

*INCLUDES ALL INPUT PARASITICS

C

SWITCH

*

Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

00 0 + –

00 1 + –

01 0 + –

01 1 +–

10 0 + –

10 1 + –

11 0 + –

11 1 + –

Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

00 0 + –

00 1 + –

01 0 + –

01 1 +–

10 0 – +

10 1 – +

11 0 – +

11 1 –+

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

Track/Hold

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter con­verts the “+” input. If the converter is set up for differen­tial inputs, the difference of [(IN+) - (IN-)]is converted.
At the end of the conversion, the positive input con­nects back to IN+ and C

HOLD

charges to the input sig-

nal.
The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t

ACQ

, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa­tion:

t

ACQ

= 7 ✕(RS+ RIN) ✕12pF

where RIN= 800Ω, RS= the source impedance of the

input signal, and t

ACQ

is never less than 468ns

(MAX1080) or 625ns (MAX1081). Note that source
impedances below 4kΩ do not significantly affect the
ADC’s AC performance.

Input Bandwidth

The ADC’s input tracking circuitry has a 6MHz
(MAX1080) or 3MHz (MAX1081) small-signal band­width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under­sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti­alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog input
to V

DD1

and GND, allow the channel input pins to swing

from GND - 0.3V to V

DD1

+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed V

DD1

by more than 50mV or be

lower than GND by 50mV.

If the analog input exceeds 50mV beyond the sup­plies, do not allow the input current to exceed 2mA.

Quick Look

To quickly evaluate the MAX1080/MAX1081s’ analog per­formance, use the circuit of Figure 5. The devices require
a control byte to be written to DIN before each conver­sion. Connecting DIN to V

DD2

feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver­sions on CH7 without powering down between conver­sions. The SSTRB output pulses high for one clock
period before the MSB of the conversion result is shift­ed out of DOUT. Varying the analog input to CH7 will
alter the sequence of bits from DOUT. A total of 16
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs typically occur 20ns
after the rising edge of SCLK.

Starting a Conversion

Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1080/MAX1081s’ internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.

The MAX1080/MAX1081 are compatible with SPI/
QSPI and MICROWIRE devices. For SPI, select the cor­rect clock polarity and sampling edge in the SPI control
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit

transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 17 for MAX1080/
MAX1081 QSPI connections.

Simple Software Interface

Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1080) or

4.8MHz (MAX1081):

1) Set up the control byte and call it TB1. TB1 should
be of the format: 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.

2) Use a general-purpose I/O line on the CPU to pull
CS low.

3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and simulta­neously receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and simulta­neously receive byte RB3.

6) Pull CS high.

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 13

Figure 5. Quick-Look Circuit

OSCILLOSCOPE

V

DD1

V

DD2

GND

COM

CS

SCLK

DIN

DOUT

SSTRB

SHDN

V

DD2

V

DD2

0 TO

+2.500V

ANALOG

0.01µF

INPUT

0.01µF

2.5V

4.7µF

MAX1080
MAX1081

CH7

REFADJ

REF

+3V OR +5V

10µF0.1µF

EXTERNAL CLOCK

CH1 CH2

*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $3FF (HEX)

CH3 CH4

SCLK

SSTRB

DOUT*

MAX1080/MAX1081

Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, two sub-LSB bits, and one
trailing zero. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.

Digital Output

In unipolar input mode, the output is straight binary
(Figure 14). For bipolar input mode, the output is two’s
complement (Figure 15). Data is clocked out on the ris­ing edge of SCLK in MSB-first format.

Serial Clock

The external clock not only shifts data in and out but
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci­sions are made and appear at DOUT on each of the
next 12 SCLK rising edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 7 shows the detailed serial-interface
timings.

The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.

Data Framing

The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:

The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V

DD1

and V

DD2

are applied.

OR

The first high bit clocked into DIN after bit 4 of a con­version in progress is clocked onto the DOUT pin.

Once a start bit has been recognized, the current conver­sion may only be terminated by pulling SHDN low.

The fastest the MAX1080/MAX1081 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 8 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

14 ______________________________________________________________________________________

BIT NAME DESCRIPTION

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
5 SEL1
4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0 to V

REF

can be converted; in bipolar mode, the differential signal can

range from -V

REF

/2 to +V

REF

/2.

2 SGL/DIF 1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-

sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).

1 PD1 Select operating mode.
0(LSB) PD0 PD1 PD0 Mode

0 0 Full power-down
0 1 Fast power-down
1 0 Reduced power
1 1 Normal operation

Table 3. Control-Byte Format

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 15

___________Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1080/MAX1081 in normal operating mode, ready to
convert with SSTRB = low. The MAX1080/MAX1081
require 10µs to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logical 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.

Power Modes

You can save power by placing the converter in one of
two low-current operating modes or in full power-down
between conversions. Select the power mode through
bit 1 and bit 0 of the DIN control byte (Tables 3 and 4),
or force the converter into hardware shutdown by dri­ving SHDN to GND.

The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes into
the programmed power mode until a new control byte
is written.

The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode, or when exiting hardware shutdown, the device
goes immediately into full-power mode and is ready to
convert after 2µs when using an external reference.
When using the internal reference, wait for the typical
power-up delay from a full power-down (software or
hardware) as shown in Figure 9.

Software Power-Down

Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-qui­escent-current state (2µA, 0.9mA, or 1.3mA).

The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1080/MAX1081 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1,
a 0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corre­sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing.

Figure 6. Single-Conversion Timing

CS

t

ACQ

SCLK

1

START

SEL

2

DIN

HIGH-Z

SSTRB

HIGH-Z

DOUT

4 891216 2024

SGL/

UNI/

SEL1SEL

IDLE

0

BIP

RB1

PD1 PD0

DIF

ACQUISITION

B9 B8 B7 B6 B5

HIGH-Z

RB3RB2

B4

B3 B2 B1 B0 S1 S0

IDLECONVERSION

HIGH-Z

MAX1080/MAX1081

Hardware Power-Down

Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer­ence, the MAX1080/MAX1081 can be considered fully
powered up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time is dependent on the external bypass
capacitors and shutdown duration.

Power-Down Sequencing

The MAX1080/MAX1081 automatic power-down modes
can save considerable power when operating at less
than maximum sample rates. Figures 10 and 11 show

the average supply current as a function of the sam­pling rate.

Using Full Power-Down Mode

Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan­nel per second. Figure 10a shows the MAX1081’s
power consumption for one- or eight-channel conver­sions utilizing full power-down mode (PD1 = PD0 = 0),
with the internal reference and the maximum clock
speed. A 0.01µF bypass capacitor at REFADJ forms an
RC filter with the internal 17kΩ reference resistor, with a
200µs time constant. To achieve full 10-bit accuracy,
seven time constants or 1.4ms are required after
power-up if the bypass capacitor is fully discharged
between conversions. Waiting this 1.4ms duration in

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

16 ______________________________________________________________________________________

PD1/PD0 MODE

CONVERTING

(mA)

AFTER

CONVERSION

INPUT COMPARATOR REFERENCE

00

Full Power-Down
(FULLPD)

2.5 2µA Off Off

01

Fast Power-Down
(FASTPD)

2.5 0.9mA Reduced Power On

10

Reduced-Power
Mode (REDP)

2.5 1.3mA Reduced Power On

11 Normal Operating 2.5 2.0mA Full Power On

CIRCUIT SECTIONS*TOTAL SUPPLY CURRENT

Table 4. Software-Controlled Power Modes

*Circuit operation between conversions; during conversion all circuits are fully powered up.

Figure 7. Detailed Serial-Interface Timing

CS

t

CSS

t

CSO

SCLK

t

DS

tDH

DIN

t

DOE

DOUT

t

STE

SSTRB

t

CH

tCL

tCP t

t

DOH

t

DOV

t

STH

t

STV

t

CSW

CSH

t

CS1

t

DOD

t

STD

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 17

Figure 8. Continuous 16-Clock/Conversion Timing

Figure 9. Reference Power-Up Delay vs. Time in Shutdown

Figure 10a. Average Supply Current vs. Sampling Rate (sps)
Using FULLPD and Internal Reference

Figure 10b. Average Supply Current vs. Sampling Rate (sps)
Using FULLPD and External Reference

Figure 11. Average Supply Current vs. Sampling Rate (sps) Using
FASTPD, REDP, Normal Operation, and Internal Reference

CS

DIN

SCLK

HIGH-Z

DOUT

HIGH-Z

SSTRB

CONTROL BYTE 0SSSCONTROL BYTE 1

11 15885812 12 1216 16 1 516

1.50

1.25

1.00

0.75

0.50

REFERENCE POWER-UP DELAY (ms)

0.25

CONTROL BYTE 2 S ETC.

DD1 = VDD2 =

8 CHANNELS

B4B9S0B4B9S0

3.0V

1 CHANNEL

B4B9

CONVERSION RESULT 1CONVERSION RESULT 0

10,000

MAX1081, V

= 20pF

C

LOAD

CODE = 1010100000

1000

100

SUPPLY CURRENT (µA)

10

0

0.0001 0.010.001 0.1 1 10
TIME IN SHUTDOWN (s)

1000

MAX1081, V
C
CODE = 1010100000

100

10

SUPPLY CURRENT (µA)

1

0.1 101 100 1k 10k

= 20pF

LOAD

8 CHANNELS

DD1 = VDD2 =

SAMPLING RATE (sps)

3.0V

1 CHANNEL

1

1 10010 1k 10k 100k

SAMPLING RATE (sps)

2.5

NORMAL OPERATION

2.0

1.5

SUPPLY CURRENT (mA)

1.0

0.5

REDP

MAX1081, V

= 20pF

C

LOAD

CODE = 1010100000

50

0

100

FASTPD

= V

150

DD2 =

3.0V

200

DD1

SAMPLING RATE (sps)

250

300 350

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

18 ______________________________________________________________________________________

Figure 12a. Full Power-Down Timing

Figure 12b. FASTPD and REDP Timing

fast power-down (FASTPD) or reduced-power (REDP)
mode instead of in full power-up can further reduce
power consumption. This is achieved by using the
sequence shown in Figure 12a.

Figure 10b shows the MAX1081’s power consumption
for one- or eight-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), an external reference, and the
maximum clock speed. One dummy conversion to
power up the device is needed, but no wait time is nec­essary to start the second conversion, thereby achiev­ing lower power consumption at up to half the full
sampling rate.

Using Fast Power-Down and Reduced Power Modes

FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sam­pling rate. Figure 11 shows the MAX1081’s power con­sumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP
mode (PD1 = 1, PD0 = 0), and for comparison, normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
power consumption using the specified power-down
mode, with the internal reference and conversion con-

trolled at the maximum clock speed. The clock speed
in FASTPD or REDP should be limited to 4.8MHz for the
MAX1080/MAX1081. FULLPD mode may provide
increased power savings in applications where the
MAX1080/MAX1081 are inactive for long periods of
time, but intermittent bursts of high-speed conversions
are required. Figure 12b shows FASTPD and REDP tim­ing.

Internal and External References

The MAX1080/MAX1081 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.

An internal buffer is designed to provide 2.5V at
REF for the MAX1080/MAX1081. The internally trimmed

1.22V reference is buffered with a 2.05V/V gain.

Internal Reference

The MAX1080/MAX1081s’ full-scale range with the inter­nal reference is 2.5V with unipolar inputs and ±1.25V
with bipolar inputs. The internal reference voltage is
adjustable by ±100mV with the circuit in Figure 13.

0

1.22V

2.5V

0

11

0V

γ = RC = 17kΩ x 0.01µF

0V

DIN

REFADJ

REF

1

FULLPD

WAIT 1.4ms (7 x RC)

1

0

REDP

DUMMY CONVERSION

0

0

FULLPD

1.22V

2.5V

1

I

VDD1

+ I

VDD2

2.5mA

0V

2.5mA

1.3mA OR 0.9mA

2.5mA

0mA

0

1

1.3mA

I

VDD1

1

1

DIN

REF

+ I

VDD2

REDP

2.5V (ALWAYS ON)

2.5mA

0

0.9mA

11

1

0

REDP FASTPD

2.5mA

0.9mA

2.5mA

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 19

External Reference

An external reference can be placed at the input
(REFADJ) or the output (REF) of the internal reference­buffer amplifier. The REFADJ input impedance is typi­cally 17kΩ. At REF, the DC input resistance is a
minimum of 18kΩ. During conversion, an external refer­ence at REF must deliver up to 350µA DC load current
and have 10Ω or less output impedance. If the refer­ence has a higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.

Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct REF input,
disable the internal buffer by connecting REFADJ to
V

DD1

.

Transfer Function

Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 14 depicts the nominal,
unipolar input/output (I/O) transfer function, and Figure
15 shows the bipolar I/O transfer function. Code transi­tions occur halfway between successive-integer LSB
values. Output coding is binary, with 1LSB = 2.44mV
for unipolar and bipolar operation.

Layout, Grounding, and Bypassing

For best performance, use PC boards; wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.

Figure 16 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all other analog
grounds to the star ground. Connect the digital system
ground to this ground only at this point. For lowest­noise operation, the ground return to the star ground’s
power supply should be low impedance and as short
as possible.

High-frequency noise in the V

DD1

power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors close to pin 20 of the MAX1080/MAX1081.

Figure 13. MAX1081 Reference-Adjust Circuit

Figure 14. Unipolar Transfer Function, Full Scale (FS) = V

REF

+ V

COM

, Zero Scale (ZS) = V

COM

Figure 15. Bipolar Transfer Function, Full Scale (FS) =
V

REF

/ 2 + V

COM

, Zero Scale (ZS) = V

COM

+3.3V

24k

100k

510k

0.01µF

12

REFADJ

OUTPUT CODE

FULL-SCALE

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

0

(COM)

123

INPUT VOLTAGE (LSB)

TRANSITION

FS - 3/2LSB

MAX1081

FS = V

ZS = V

1LSB =

FS

REF

COM

V

1024

+ V

REF

COM

OUTPUT CODE

V

REF

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

*V

V

COM

≤

REF

FS

ZS = V

-FS = + V

1LSB =

- FS

/ 2

+ V

=

COM

2

COM

-V
2

REF

V

1024

REF

COM

COM*

INPUT VOLTAGE (LSB)

+FS - 1LSB

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

20 ______________________________________________________________________________________

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale

Positive Zero Negative

Full Scale Scale Full Scale

V

REF

+ V

COM

V

COM

V

REF

/ 2

V

COM

-V

REF

/ 2

+ V

COM

+ V

COM

Table 5. Full Scale and Zero Scale

Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ω resis-
tor can be connected as a lowpass filter (Figure 16).

High-Speed Digital Interfacing with QSPI

The MAX1080/MAX1081 can interface with QSPI using
the circuit in Figure 17 (f

SCLK

= 4.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.

TMS320LC3x Interface

Figure 18 shows an application circuit to interface the
MAX1080/MAX1081 to the TMS320 in external clock
mode. Figure 19 shows the timing diagram for this inter­face circuit.

Use the following steps to initiate a conversion in the
MAX1080/MAX1081 and to read the results:

1) The TMS320 should be configured with CLKX (trans-

mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input
clock. CLKX and CLKR on the TMS320 are connect­ed to the MAX1080/MAX1081’s SCLK input.

2) The MAX1080/MAX1081’s CS pin is driven low by

the TMS320’s XF_ I/O port to enable data to be
clocked into the MAX1080/MAX1081s’ DIN pin.

3) An 8-bit word (1XXXXX11) should be written to the
MAX1080/MAX1081 to initiate a conversion and
place the device into normal operating mode. See
Table 3 to select the proper XXXXX bit values for your
specific application.

4) The MAX1080/MAX1081s’ SSTRB output is moni­tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the con­version is in progress and data is ready to be
received from the device.

5) The TMS320 reads in 1 data bit on each of the next
16 rising edges of SCLK. These data bits represent
the 10 + 2-bit conversion result followed by 4 trailing
bits, which should be ignored.

6) Pull CS high to disable the MAX1080/MAX1081 until
the next conversion is initiated.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values
from a straight line on an actual transfer function. This
straight line can be a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1080/MAX1081
are measured using the best-straight-line fit method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.

Figure 16. Power-Supply Grounding Connection

SUPPLIES

V

DD1

*R = 10Ω

DD1

*OPTIONAL

GND

GNDV

MAX1080
MAX1081

COM

V

DD2

V

DD2

DD

DIGITAL

CIRCUITRY

DGNDV

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 21

Aperture Width

Aperture width (tAW) is the time the T/H circuit requires
to disconnect the hold capacitor from the input circuit
(for instance, to turn off the sampling bridge and put
the T/H unit in hold mode).

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the SNR is the ratio of the full-scale analog
input (RMS value) to the RMS quantization error (resid­ual error). The ideal, theoretical minimum analog-to-dig­ital noise is caused only by quantization error and
results directly from the ADC’s resolution (N bits):

SNR = (6.02

✕

N + 1.76)dB

In reality, there are other noise sources besides quanti­zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen­tal, the first five harmonics, and the DC offset.

Figure 17. QSPI Connections

Figure 18. MAX1080/MAX1081-to-TMS320 Serial Interface

ANALOG

INPUTS

V

DD1

+5V

+5V

OR

OR

+3V

+3V

V

1

CH0

2

CH1

CH2

3

4

CH3

MAX1080
MAX1081

5

CH4

6

CH5

7

CH6

8

CH7

9

COM

10

SHDN

DD1

V

DD2

SCLK

DIN

SSTRB

DOUT

GND

REFADJ

REF

20

19

18

CS

17

16

15

14

13

12

11

4.7µF

0.1µF

0.01µF

10µF

(POWER SUPPLIES)

SCK

PCS0

MOSI

MISO

MC683XX

(GND)

XF

CLKX

CS

SCLK

TMS320LC3x

CLKR

MAX1080
MAX1081

DX

DR

FSR

DIN

DOUT

SSTRB

Signal-to-Noise Plus Distortion (SINAD)

SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out­put signals:

SINAD (dB) = 20 ✕log (Signal

RMS

/ Noise

RMS

)

Effective Number of Bits (ENOB)

ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the ADC’s full-scale range, calcu­late ENOB as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the input signal’s
first five harmonics to the fundamental itself. This is
expressed as:

where V

1

is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the RMS amplitude of the funda­mental (maximum signal component) to the RMS value
of the next-largest distortion component.

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

22 ______________________________________________________________________________________

Figure 19. MAX1080/MAX1081-to-TMS320 Serial Interface

PART

TEMP.

RANGE

PIN­PACKAGE

MAX1080BEUP

MAX1081AEUP
MAX1081BEUP -40°C to +85°C

-40°C to +85°C

-40°C to +85°C 20 TSSOP

20 TSSOP
20 TSSOP

±1

±1/2

INL

(LSB)

±1

MAX1081ACUP

MAX1081BCUP 0°C to +70°C

0°C to +70°C 20 TSSOP

20 TSSOP

±1/2

±1

Ordering Information (continued)

Typical Operating Circuit

V

DD

I/O

SCK (SK)

MOSI (SO)

MISO (SI)

V

SS

SHDN

SSTRB

DOUT

DIN

SCLK

CS

COM

GND

V

DD1

V

DD2

CH7

4.7µF

0.1µF

CH0

0 TO

+2.5V

ANALOG

INPUTS

MAX1080
MAX1081

CPU

+5V OR
+3V

REF

0.01µF

REFADJ

V

DD2

Chip Information

TRANSISTOR COUNT: 4286

PROCESS: BiCMOS

CS

SCLK

DIN

SSTRB

DOUT

SEL2START SEL1 SEL0 PD1 PD0

UNI/BIP SGI/DIF

THD 20 log

=×



VVVVV

++++

2232424




V

252

1

HIGH IMPEDANCE

MSB

B8 S1

S0

HIGH IMPEDANCE






MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,

8-Channel, Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 23

________________________________________________________Package Information

Note: The MAX1080/MAX1081 do not have an exposed die pad.

TSSOP.EPS

MAX1080/MAX1081

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

NOTES