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General Description
The MAX108 PECL-compatible, 1.5Gsps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX108 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (typically 7.5 effective bits)
at the Nyquist frequency. A fully differential comparator
design and decoding circuitry reduce out-of-sequence
code errors (thermometer bubbles or sparkle codes)
and provide excellent metastable performance. Unlike
other ADCs that can have errors resulting in false fullor zero-scale outputs, the MAX108 limits the error magnitude to 1LSB.
The analog input is designed for either differential or
single-ended use with a ±250mV input voltage range.
Dual, differential, positive-referenced emitter-coupled
logic (PECL)-compatible output data paths ensure easy
interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V
or +5V referenced systems. Control inputs are provided
for interleaving additional MAX108 devices to increase
the effective system sampling rate.
The MAX108 is packaged in a 25mm x 25mm, 192-contact Enhanced Super Ball-Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) temperature range. For pin-compatible, lower speed versions of
the MAX108, see the MAX104 (1Gsps) and the MAX106
(600Msps) data sheets.
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems
Features
♦ 1.5Gsps Conversion Rate
♦ 2.2GHz Full-Power Analog Input Bandwidth
♦ 7.5 Effective Bits at f
IN
= 750MHz (Nyquist
Frequency)
♦ ±0.25LSB INL and DNL
♦ 50Ω Differential Analog Inputs
♦ ±250mV Input Signal Range
♦ On-Chip, +2.5V Precision Bandgap Voltage
Reference
♦ Latched, Differential PECL Digital Outputs
♦ Selectable 8:16 Demultiplexer
♦ Internal Demux Reset Input with Reset Output
♦ 192-Contact ESBGA Package
♦ Pin Compatible with MAX104 (1Gsps) and
MAX106 (600Msps)
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
________________________________________________________________
Maxim Integrated Products
1
19-1492; Rev 0; 9/99
PART
MAX108CHC 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
192 ESBGA
EVALUATION KIT
AVAILABLE
Ordering Information
ESBGA
TOP VIEW
MAX108
Typical Operating Circuit appears at end of data sheet.
192-Contact ESBGA
Ball Assignment Matrix
ESBGA is a trademark of Amkor/Anam.
PCB land pattern appears at end of data sheet.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCA to GNDA .........................................................-0.3V to +6V
V
CC
D to GNDD.........................................................-0.3V to +6V
V
CC
I to GNDI............................................................-0.3V to +6V
V
CC
O to GNDD........................................-0.3V to (VCCD + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (V
CC
D + 0.3V)
V
EE
to GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
V
CC
A to VCCD .......................................................-0.3V to +0.3V
V
CC
A to VCCI.........................................................-0.3V to +0.3V
PECL Digital Output Current...............................................50mA
REFIN to GNDR ........................................-0.3V to (V
CC
I + 0.3V)
REFOUT Current ................................................+100µA to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs
(DEMUXEN, DIVSELECT) ......................-0.3V to (V
CC
D + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V)
VOSADJ Adjust Input ................................-0.3V to (V
CC
I + 0.3V)
CLK+ to CLK- Voltage Difference..........................................±3V
CLK+, CLK-.....................................(V
EE
- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(V
EE
- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference............................................±2V
VIN+, VIN- to GNDI................................................................±2V
Continuous Power Dissipation (T
A
= +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C) ....4.88W
(with heatsink and 200 LFM airflow,
derate 106mW/°C above +70°C) .....................................8.48W
Operating Temperature Range
MAX108CHC.........................................................0°C to +70°C
Operating Junction Temperature.....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS
Missing Codes None Codes
Differential Nonlinearity (Note 1) DNL -0.5 ±0.25 0.5 LSB
Full-Scale Input Range V
FSR
475 500 525 mVp-p
Common-Mode Input Range V
CM
±0.8 V
Input Resistance R
IN
49 50 51 Ω
Input Resistance Temperature
Coefficient
TC
R
150 ppm/°C
Resolution RES 8 Bits
Integral Nonlinearity (Note 1) INL -0.5 ±0.25 0.5 LSB
Input Resistance (Note 2) R
VOS
14 25 kΩ
Input VOSAdjust Range ±4 ±5.5 LSB
Reference Output Voltage REFOUT 2.475 2.50 2.525 V
Reference Output Load
Regulation
∆REFOUT 5 mV
Reference Input Resistance R
REF
45 kΩ
CONDITIONS
No missing codes guaranteed
TA= +25°C
Note 1
Signal + offset w.r.t. GNDI
VOSADJ = 0 to 2.5V
VIN+ and VIN- to GNDI, TA= +25°C
Driving REFIN input only
0 < I
SOURCE
< 2.5mA
Referenced to GNDR
TA= +25°C
ACCURACY
ANALOG INPUTS
VOS ADJUST CONTROL INPUT
REFERENCE INPUT AND OUTPUT
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PECL DIGITAL OUTPUTS (Note 5)
Negative Power-Supply
Rejection Ratio (Note 8)
PSRR- 40 68 dB(Note 10)
Common-Mode Rejection Ratio
(Note 7)
CMRR 40 68 dB
Positive Power-Supply Rejection
Ratio (Note 8)
PSRR+ 40 73 dB
VIN+ = VIN- = ±0.1V
(Note 9)
Positive Analog Supply Current ICCA 480 780 mA
Positive Input Supply Current ICCI 108 150 mA
Negative Input Supply Current I
EE
-290 -210 mA
Digital Supply Current ICCD 205 340 mA
Output Supply Current (Note 6) ICCO 75 115 mA
Power Dissipation (Note 6) P
DISS
5.25 W
Digital Output High Voltage V
OH
-1.025 -0.880 V
Digital Output Low Voltage V
OL
-1.810 -1.620 V
PARAMETER SYMBOL MIN TYP MAX UNITS
High-Level Input Voltage V
IH
2.0 V
Low-Level Input Voltage V
IL
0.8 V
High-Level Input Current I
IH
50 µA
Clock Input Resistance R
CLK
48 50 52 Ω
Input Resistance Temperature
Coefficient
TC
R
150 ppm/°C
Low-Level Input Current I
IL
-1 1 µA
Digital Input High Voltage V
IH
-1.165 V
Digital Input Low Voltage V
IL
-1.475 V
CONDITIONS
VIL= 0
VIH= 2.4V
CLK+ and CLK- to CLKCOM, TA= +25°C
CLOCK INPUTS (Note 3)
TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)
DEMUX RESET INPUT (Note 4)
POWER REQUIREMENTS
PECL DIGITAL OUTPUTS (Note 5)
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)
Transfer Curve Offset V
OS
-2.0 0 +2.0 LSBVOSADJ control input open
Single-ended
Differential 45.7 48.2
Signal-to-Noise Ratio and
Distortion (Note 11)
SINAD
250
48.2
dB
fIN= 250MHz
Single-ended
Differential 44.5 47.0
Single-ended
Differential
SINAD
750
47.1
44.3
SINAD
1500
44.4
fIN= 1500MHz
fIN= 750MHz
Single-ended
Differential 55.0 61.6
Spurious-Free Dynamic Range
SFDR
250
61.7
dB
fIN= 250MHz
Single-ended
Differential 50.0 54.0
Single-ended
Differential
SFDR
750
54.1
44.6
SFDR
1500
45.5
fIN= 1500MHz
fIN= 750MHz
Single-ended
Differential -55.5 -60.2
Total Harmonic Distortion
(Note 12)
THD
250
-61.3
dB
fIN= 250MHz
Single-ended
Differential -49.0 -52.1
Single-ended
Differential
THD
750
-52.8
-44.5
THD
1500
-44.2
fIN= 1500MHz
fIN= 750MHz
Single-ended
Differential 44.2 47.4
Signal-to-Noise Ratio
(No Harmonics)
SNR
250
47.4
dB
fIN= 250MHz
Single-ended
Differential 43.3 46.8
SNR
750
46.9
fIN= 750MHz
Single-ended
Differential 7.3 7.71
Effective Number of Bits
(Note 11)
ENOB
250
7.71
Bits
Single-ended
Differential
fIN= 250MHz
44.8
SNR
1500
44.9
fIN= 1500MHz
Single-ended
Differential 7.1 7.51
ENOB
750
7.53
fIN= 750MHz
Single-ended
Differential
PARAMETER SYMBOL MIN TYP MAX UNITS
7.07
Analog Input VSWR VSWR 1.1:1 V/V
Analog Input Full-Power
Bandwidth
BW
-3dB
2.2 GHz
ENOB
1500
7.07
Two-Tone Intermodulation IMD -66.8 dB
CONDITIONS
fIN= 1500MHz
fIN= 500MHz
f
IN1
= 247MHz, f
IN2
= 253MHz,
at -7dB below full-scale
ANALOG INPUT
DYNAMIC SPECIFICATIONS
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)
DIV4 mode
DIV1, DIV2 modes
7.5DIV4 mode
DIV1, DIV2 modes
Figures 6, 7, 8t
PDP
Auxiliary Port Pipeline
Delay
t
PDA
9.5
Clock
Cycles
Figures 6, 7, 8
8.5
DREADY to DATA Propagation
Delay (Note 14)
t
PD2
-50 150 350 psFigure 17
CLK to DREADY Propagation
Delay
t
PD1
2.2 nsFigure 17
Reset Input Data Hold Time
(Note 13)
t
HD
0 psFigure 15
Clock Pulse Width High t
PWH
0.3 5 nsFigure 17
PARAMETER SYMBOL MIN TYP MAX UNITS
Aperture Jitter t
AJ
<0.5 ps
Aperture Delay t
AD
100 ps
Reset Input Data Setup Time
(Note 13)
t
SU
0 ps
DATA Rise Time t
RDATA
420 ps
Maximum Sample Rate f
MAX
1.5 Gsps
Clock Pulse Width Low t
PWL
0.3 ns
DATA Fall Time t
FDATA
360 ps
DREADY Rise Time t
RDREADY
220 ps
DREADY Fall Time t
FDREADY
180 ps
Primary Port Pipeline
Delay
7.5
Clock
Cycles
CONDITIONS
Figure 4
Figure 4
Figure 15
20% to 80%, CL= 3pF
20% to 80%, CL= 3pF
20% to 80%, CL= 3pF
20% to 80%, CL= 3pF
Figure 17
TIMING CHARACTERISTICS
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 times the slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5: All PECL digital outputs are loaded with 50Ωto V
CC
O - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6: The current in the V
CC
O power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7: Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the
change in the common-mode voltage, expressed in dB.
Note 8: Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change
in power-supply voltage, expressed in dB.
Note 9: Measured with the positive supplies tied to the same potential; V
CC
A = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.
Note 10: V
EE
varies from -5.25V to -4.75V.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
6 _______________________________________________________________________________________
Note 11: Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to
the theoretical full-scale range.
Note 12: Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse width one clock period long or greater.
Note 14: Guaranteed by design. The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the
DREADY signal (when the output data changes) to the 50% point on a data output bit. This places the falling edge of the
DREADY signal in the middle of the data output valid window, within the differences between the DREADY and DATA rise
and fall times, which gives maximum setup and hold time for latching external data latches.
Typical Operating Characteristics
(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)
6.25
100 20001000
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
6.75
6.50
7.00
7.25
7.50
7.75
8.00
MAX108 toc01
ANALOG INPUT FREQUENCY (MHz)
ENOB (Bits)
10
-1dBFS
-12dBFS
-6dBFS
6.25
100 20001000
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
6.75
6.50
7.00
7.25
7.50
7.75
8.00
MAX108 toc02
ANALOG INPUT FREQUENCY (MHz)
ENOB (Bits)
10
-1dBFS
-12dBFS
-6dBFS
40
100 20001000
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
42
41
43
44
45
46
47
48
49
50
MAX108 toc03
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
10
-6dBFS
-1dBFS
-12dBFS
40
100 20001000
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
42
41
43
44
45
46
47
48
49
50
MAX108 toc04
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
10
-1dBFS
-12dBFS
-6dBFS
30
100 20001000
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
42
38
34
46
50
MAX108 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
10
-1dBFS
-12dBFS
-6dBFS
30
100 20001000
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
42
38
34
46
50
MAX108 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
10
-1dBFS
-12dBFS
-6dBFS
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
70
65
60
55
SFDR (dB)
50
45
40
35
10
-6dBFS
-1dBFS
-12dBFS
ANALOG INPUT FREQUENCY (MHz)
100 20001000
EFFECTIVE NUMBER OF BITS vs.
CLOCK POWER
(f
= 250MHz, -1dBFS)
8.00
7.75
7.50
7.25
ENOB (Bits)
7.00
IN
DIFFERENTIAL CLOCK DRIVE
SINGLE-ENDED CLOCK DRIVE
MAX108 toc07
MAX108toc10
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
70
65
60
55
SFDR (dB)
50
45
40
35
10
-6dBFS
-1dBFS
-12dBFS
ANALOG INPUT FREQUENCY (MHz)
100 20001000
EFFECTIVE NUMBER OF BITS
vs. V
I = VCCA = VCCD
CC
(f
= 250MHz, -1dBFS)
8.00
7.75
7.50
7.25
ENOB (Bits)
7.00
IN
MAX108 toc08
MAX108-11
EFFECTIVE NUMBER OF BITS
vs. CLOCK FREQUENCY
(f
= 250MHz, 1dBFS)
8.00
7.75
7.50
7.25
ENOB (Bits)
7.00
6.75
6.50
100 1000 1500
IN
CLOCK FREQUENCY (MHz )
EFFECTIVE NUMBER OF BITS vs. V
(fIN = 250MHz, -1dBFS)
8.00
7.75
7.50
7.25
ENOB (Bits)
7.00
EE
MAX108 toc09
MAX108-12
6.75
6.50
-12 -10
-6
-2 2 6-8 -4 0 4 108
CLOCK POWER (dBm) PER SIDE
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK POWER
(f
= 250MHz, -1dBFS)
67
65
63
61
59
57
SFDR (dB)
55
53
51
49
47
-12 -10 -8 -6 -4 -2 0 2 4 8610
IN
SINGLE-ENDED CLOCK DRIVE
DIFFERENTIAL CLOCK DRIVE
CLOCK POWER (dBm) PER SIDE
MAX108toc13
6.75
6.50
4.5 4.94.7 5.1 5.3 5.5
VCC (V)
SPURIOUS-FREE DYNAMIC RANGE
vs. V
I = VCCA = VCCD
CC
(f
= 250MHz, -1dBFS)
67
66
65
64
63
62
SFDR (dB)
61
60
59
58
57
4.5 4.7 4.9 5.1 5.3 5.5
IN
VCC (V)
MAX108-14
6.75
6.50
-5.5 -5.1-5.3 -4.9 -4.7 -4.5
VEE (V)
SPURIOUS-FREE DYNAMIC RANGE vs. V
(fIN = 250MHz, -1dBFS)
67
66
65
64
63
62
SFDR (dB)
61
60
59
58
57
-5.5 -5.3 -5.1 -4.9 -4.7 -4.5
VEE (V)
EE
MAX108-15
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)
-64
-62
-63
-60
-61
-58
-59
-57
-55
-56
-54
4.5 4.7 4.9 5.1 5.3 5.5
TOTAL HARMONIC DISTORTION
vs. V
CC
I = VCCA = VCCD
(f
IN
= 250MHz, -1dBFS)
MAX108-16
V
CC
(V)
THD (dB)
-64
-62
-63
-60
-61
-58
-59
-57
-55
-56
-54
-5.5 -5.3 -5.1 -4.9 -4.7 -4.5
TOTAL HARMONIC DISTORTION vs. V
EE
(f
IN
= 250MHz, -1dBFS)
MAX108-17
V
EE
(V)
THD (dB)
-128.0
-102.4
-51.2
-76.8
-25.6
0
0 300150 450 600 750
FFT PLOT
(f
IN
= 250.9460449MHz,
RECORD LENGTH 16,384)
MAX108 toc18
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
ENOB = 7.73
SINAD = 48.3dB
SNR = 47.3dB
THD = -59.9dB
SFDR = 61.5dB
H3
H2
FUNDAMENTAL
-128.0
-102.4
-51.2
-76.8
-25.6
0
0 300150 450 600 750
FFT PLOT
(f
IN
= 747.1618562MHz,
RECORD LENGTH 16,384)
MAX108 toc19
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
ENOB = 7.61
SINAD = 47.6dB
SNR = 46.7dB
THD = -56.5dB
SFDR = 59.4dB
H3
H2
FUNDAMENTAL
-5
-6
-7
-8
-9
-10
500 1500 2500
ANALOG INPUT BANDWIDTH
-6dB BELOW FULL SCALE
MAX108toc22
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SMALL-SIGNAL BANDWIDTH = 2.4GHz
-128.0
-102.4
-51.2
-76.8
-25.6
0
0 300150 450 600 750
FFT PLOT
(f
IN
= 1503.021240MHz,
-1dBFS, RECORD LENGTH 16,384)
MAX108 toc20
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
ENOB = 7.12
SINAD = 44.6dB
SNR = 44.7dB
THD = -44.4dB
SFDR = 44.4dB
H3
H2
FUNDAMENTAL
-128.0
-102.4
-51.2
-76.8
-25.6
0
0 300150 450 600 750
FFT PLOT
(f
IN
= 1503.021240MHz,
-3dBFS, RECORD LENGTH 16,384)
MAX108 toc21
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
ENOB = 7.60
SINAD = 47.5dB
SNR = 42.0dB
THD = -51.3dB
SFDR = 51.3dB
H3
H2
FUNDAMENTAL
0
-1
-2
-3
-4
-5
500 1500 2500
ANALOG INPUT BANDWIDTH
FULL POWER
MAX108toc23
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
FULL-POWER BANDWIDTH = 2.2GHz
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
(LOW-FREQUENCY SERVO-LOOP DATA)
MAX108toc24
OUTPUT CODE
INL (LSB)
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
(LOW-FREQUENCY SERVO-LOOP DATA)
MAX108toc25
OUTPUT CODE
DNL (LSB)
DREADY
200mV/div
DATA
200mV/div
DREADY RISE/FALL TIME,
DATA-OUTPUT RISE/FALL TIME
MAX108 toc26
500ps/div
1.0
1.1
1.2
1.3
1.4
1.5
0 1000500 1500 2000 2500
VSWR vs. ANALOG INPUT FREQUENCY
MAX108toc27
ANALOG INPUT FREQUENCY (MHz)
VSWR
-128.0
-102.4
-51.2
-76.8
-25.6
0
0 300150 450 600 750
TWO-TONE INTERMODULATION FFT PLOT
(f
IN1
= 247.1008301MHz, f
IN2
= 253.3264160MHz,
7dB BELOW FULL SCALE, RECORD LENGTH 16,384)
MAX108 toc28
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN1
fIN2
Pin Description
NAME FUNCTION
A1–A4, A6, A7, B1, B2, C1, C2, D1–D3,
G1, H1, J2, J3, K1–K3, L2, L3, M1, N1,
T2, T3, U1, V1, V2, W1–W4
GNDI
Analog Ground. For T/H amplifier, clock distribution, bandgap
reference, and reference amplifier.
A5, B5, C5, H2, H3, M2, M3, U5, V5, W5 VCCI
Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distribution, bandgap reference, and reference amplifier.
CONTACT
A8, B8, C8, U6, V6, W6 GNDA Analog Ground. For comparator array.
A9, B9, C9, U7, V7, W7 VCCA Analog Supply Voltage, +5V. Supplies analog comparator array.
A11, B11, B16, B17, C11, C16, U9, U17,
V9, V17, V18, W9
GNDD Digital Ground
A10, E17, F2, P3, R17, R18 TESTPOINT (T.P.)
Test Point. Do not connect.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
10 ______________________________________________________________________________________
Pin Description (continued)
H18 P3+ Primary Output Data Bit 3
H17 P3- Complementary Primary Output Data Bit 3
F17 P2- Complementary Primary Output Data Bit 2
G17 A2- Complementary Auxiliary Output Data Bit 2
G18 A2+ Auxiliary Output Data Bit 2
F18 P2+ Primary Output Data Bit 2
E18 DEMUXEN
TTL/CMOS Demux Enable Control
1: Enable Demux
0: Disable Demux
F1 VOSADJ Offset Adjust Input
E2 IPTAT
Die Temperature Measurement Test Point. See
Die Temperature
Measurement
section.
C7 REFOUT Reference Output
C15 A1- Complementary Auxiliary Output Data Bit 1
D18 AUXEN2
Connect to VCCO to power the auxiliary port, or connect to GNDD
to power down.
E1 ICONST
Die Temperature Measurement Test Point. See
Die Temperature
Measurement
section.
D17 DIVSELECT
TTL/CMOS Demux Divide Selection Input
1: Decimation DIV4 mode
0: Demultiplexed DIV2 mode
C13 A0- Complementary Auxiliary Output Data Bit 0 (LSB)
C14 P1- Complementary Primary Output Data Bit 1
C12 P0- Complementary Primary Output Data Bit 0 (LSB)
B13 A0+ Auxiliary Output Data Bit 0 (LSB)
B15 A1+ Auxiliary Output Data Bit 1
C6 REFIN Reference Input
B14 P1+ Primary Output Data Bit 1
B10, B18, C10, C17, C18, T17, T18, U8,
U18, V8, W8
VCCD Digital Supply Voltage, +5V
B12 P0+ Primary Output Data Bit 0 (LSB)
B6, B7 GNDR
Reference Ground. Must be connected to GNDI.
NAME FUNCTION
A12–A19, B19, C19, D19, E19, F19,
G19, H19, J19, K19, L19, M19, N19,
P19, T19, U19, V19, W10–W19
VCCO PECL Supply Voltage, +3V to +5V
CONTACT
B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,
U2–U4, V3, V4
V
EE
Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribution, bandgap reference, and reference amplifier.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 11
Pin Description (continued)
K18 DREADY+ Data-Ready Clock
L1 VIN+ Differential Input Voltage (+)
K17 DREADY- Complementary Data-Ready Clock
V13 A7+ Auxiliary Output Data Bit 7 (MSB)
V15 A6+ Auxiliary Output Data Bit 6
V16 P6+ Primary Output Data Bit 6
V14 P7+ Primary Output Data Bit 7 (MSB)
V12 OR+ PECL Overrange Bit
V10 RSTIN+ PECL Demux Reset Input
V11 RSTOUT+ PECL Reset Output
U13 A7- Complementary Auxiliary Output Data Bit 7 (MSB)
U15 A6- Complementary Auxiliary Output Data Bit 6
U16 P6- Complementary Primary Output Data Bit 6
U14 P7- Complementary Primary Output Data Bit 7 (MSB)
U12 OR- Complementary PECL Overrange Bit
R19 AUXEN1
Connect to VCCO to power the auxiliary port, or connect to
GNDD to power down.
U10 RSTIN- Complementary PECL Demux Reset Input
U11 RSTOUT- Complementary PECL Reset Output
T1 CLK+ Sampling Clock Input
R1–R3 CLKCOM 50Ω Clock Termination Return
P18 A5+ Auxiliary Output Data Bit 5
M17 A4- Complementary Auxiliary Output Data Bit 4
P1 CLK- Complementary Sampling Clock Input
P2 TESTPOINT (T.P.)
This contact must be connected to GNDI.
NAME FUNCTION
P17 A5- Complementary Auxiliary Output Data Bit 5
CONTACT
N17 P5- Complementary Primary Output Data Bit 5
N18 P5+ Primary Output Data Bit 5
M18 A4+ Auxiliary Output Data Bit 4
J17 A3- Complementary Auxiliary Output Data Bit 3
L17 P4- Complementary Primary Output Data Bit 4
L18 P4+ Primary Output Data Bit 4
J18 A3+ Auxiliary Output Data Bit 3
J1 VIN- Differential Input Voltage (-)
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
12 ______________________________________________________________________________________
_______________Detailed Description
The MAX108 is an 8-bit, 1.5Gsps flash analog-to-digital
converter (ADC) with on-chip T/H amplifier and differential PECL-compatible outputs. The ADC (Figure 1)
employs a fully differential 8-bit quantizer and a unique
encoding scheme to limit metastable states, with no
error exceeding 1LSB max.
An integrated 8:16 output demultiplexer simplifies interfacing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
has internal reset capability that allows multiple
MAX108s to be time-interleaved to achieve higher
effective sampling rates.
When clocked at 1.5Gsps, the MAX108 provides a typical ENOB of 7.5 bits at an analog input frequency of
750MHz. The analog input of the MAX108 is designed
for differential or single-ended use with a ±250mV fullscale input range. In addition, this fast ADC features an
on-chip +2.5V precision bandgap reference. If desired,
an external reference can also be used.
Figure 1. Simplified Functional Diagram
REF
REF
OUT
BANDGAP
REFERENCE
IN
+2.5V
REFERENCE
AMPLIFIER
VOSADJ
50Ω
VIN+
VIN-
50Ω
GNDI
CLK+
50Ω
CLKCOM
50Ω
CLK-
RSTIN+
RSTIN-
GNDI
T/H
CLOCK
DRIVER
INPUT DUAL LATCH
GNDR
BIAS CURRENTS
T/H AMPLIFIER
RESET
ADC
CLOCK
DRIVER
RESET
PIPELINE
8-BIT
FLASH ADC
LOGIC
CLOCK
DRIVER
DELAYED
RESET
MAX108
DEMUXEN
2
16
DEMUX
CLOCK
GENERATOR
DIVSELECT
DEMUX
CLOCK
DRIVER
OVERRANGE
BIT
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DATA
READY CLOCK
DEMUX
RESET OUTPUT
DIFFERENTIAL
PECL OUTPUTS
OR
2
A0–A7
16
P0–P7
16
DREADY
2
RSTOUT
2
Principle of Operation
The MAX108’s flash or parallel architecture provides
the fastest multibit conversion of all common integrated
ADC designs. The key to this high-speed flash architecture is the use of an innovative, high-performance
comparator design. The flash converter and downstream logic translate the comparator outputs into a
parallel 8-bit output code and pass this binary code on
to the optional 8:16 demultiplexer, where primary and
auxiliary ports output PECL-compatible data at up to
750Msps per port (depending on how the demultiplexer section is set on the MAX108).
The ideal transfer function appears in Figure 2.
On-Chip Track/Hold Amplifier
As with all ADCs, if the input waveform is changing
rapidly during conversion, ENOB and signal-to-noise
ratio (SNR) specifications will degrade. The MAX108’s
on-chip, wide-bandwidth (2.2GHz) T/H amplifier
reduces this effect and increases the ENOB performance significantly, allowing precise capture of fast
analog data at high conversion rates.
The T/H amplifier buffers the input signal and allows a
full-scale signal input range of ±250mV. The T/H amplifier’s differential 50Ω input termination simplifies interfacing to the MAX108 with controlled impedance lines.
Figure 3 shows a simplified diagram of the T/H amplifier
stage internal to the MAX108.
Aperture width, delay, and jitter (or uncertainty) are
parameters that affect the dynamic performance of
high-speed converters. Aperture jitter, in particular,
directly influences SNR and limits the maximum slew
rate (dV/dt) that can be digitized without contributing
significant errors. The MAX108’s innovative T/H amplifier
design limits aperture jitter typically to less than 0.5ps.
Aperture Width
Aperture width (tAW) is the time the T/H circuit requires
(Figure 4) to disconnect the hold capacitor from the
input circuit (for instance, to turn off the sampling
bridge and put the T/H unit in hold mode).
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation
(Figure 4) in the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
Internal Reference
The MAX108 features an on-chip +2.5V precision
bandgap reference that can be used by connecting
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 13
Figure 2. Transfer Function
Figure 3. Internal Structure of the 2.2GHz T/H Amplifier
Figure 4. T/H Aperture Timing
OVERRANGE +
ALL INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
VIN+
VIN-
CLK+
CLK-
CLKCOM
255
255
254
129
128
127
126
DIGITAL OUTPUT
3
2
1
0
50Ω50Ω
GNDI
50Ω50Ω
(-FS + 1LSB)
INPUT
AMPLIFIER
CLOCK
SPLITTER
0
ANALOG INPUT
SAMPLING
BRIDGE
AMPLIFIER
GNDI
+FS
(+FS - 1LSB)
BUFFER
TO
COMPARATORS
C
HOLD
TO
COMPARATORS
CLK
CLK
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
TRACK TRACK
t
AW
t
AJ
HOLD
APERTURE DELAY (t
APERTURE WIDTH (t
APERTURE JITTER (t
)
AD
)
AW
)
AJ
MAX108
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally connected to GNDR. GNDR
must be connected to GNDI on the user’s application
board. If required, REFOUT can source up to 2.5mA to
supply external devices.
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external reference supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT must not be simultaneously
connected, to avoid conflicts between the two references. REFIN has a typical input resistance of 5kΩ and
accepts input voltages of +2.5V ±200mV. For best performance, Maxim recommends using the MAX108’s
internal reference.
Digital Outputs
The MAX108 provides data in offset binary format to
differential PECL outputs. A simplified circuit schematic
of the PECL output cell is shown in Figure 5. All PECL
outputs are powered from VCCO, which may be operated from any voltage between +3.0V to VCCD for flexible
interfacing with either +3.3V or +5V systems. The nominal VCCO supply voltage is +3.3V.
All PECL outputs on the MAX108 are open-emitter
types and must be terminated at the far end of each
transmission line with 50Ω to VCCO - 2V. Table 1 lists all
MAX108 PECL outputs and their functions.
Demultiplexer Operation
The MAX108 features an internal demultiplexer that
provides for three different modes of operation (see the
following sections on
Demultiplexed DIV2 Mode, Non-
Demultiplexed DIV1 Mode,
and
Decimation DIV4
Mode
) controlled by two TTL/CMOS-compatible inputs:
DEMUXEN and DIVSELECT.
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSELECT low selects demultiplexed DIV2 mode, and DIVSELECT high selects decimation DIV4 mode (Table 2).
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
14 ______________________________________________________________________________________
Figure 5. Simplified PECL Output Structure
Table 1. PECL Output Functions
FUNCTIONAL DESCRIPTION
P0+ to P7+, P0- to P7-
Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
PECL OUTPUT SIGNALS
RSTOUT+, RSTOUT- Reset Output True and Complementary Outputs
DREADY+, DREADY-
Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.
OR+, OR- Overrange True and Complementary Outputs
A0+ to A7+, A0- to A7-
Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
500Ω 500Ω
DIFF.
PAIR
1.8mA
GNDD GNDD
O
V
CC
A_+/P_+
GNDD
A_-/P_-
Non-Demultiplexed DIV1 Mode
The MAX108 may be operated at up to 750Msps in
non-demultiplexed DIV1 mode (Table 2). In this mode,
the internal demultiplexer is disabled and sampled
data is presented to the primary port only, with the
data repeated at the auxiliary port but delayed by one
clock cycle (Figure 6). Since the auxiliary output port
contains the same data stream as the primary output
port, the auxiliary port can be shut down to save
power by connecting AUXEN1 and AUXEN2 to digital
ground (GNDD). This powers down the internal bias
cells and causes both outputs (true and complementary) of the auxiliary port to pull up to a logic-high
level. To save additional power, the external 50Ω termination resistors connected to the PECL termination
power supply (V
CC
O - 2V) may be removed from all
auxiliary output ports.
Demultiplexed DIV2 Mode
The MAX108 features an internally selectable DIV2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two consecutive samples appearing in the primary and auxiliary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to VCCO to power up the auxiliary port
PECL output drives.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 15
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
Figure 7. Demuxed DIV2-Mode Timing Diagram
CLK
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
ADC SAMPLE NUMBER
CLK-
n n+1 n+2 n+3 n+4 n+5
CLK+
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n n+1 n+2 n+3 n+4
PRIMARY
DATA PORT
NOTE: THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA.
GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TO SAVE POWER.
CLK-
CLK
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
NOTE: THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES.
BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
ADC SAMPLE NUMBER
n n+1 n+2 n+3 n+4 n+5
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n n+2 n+4
n+1 n+2 n+3 n+4
n+1n-1 n+3
n+5
MAX108
Decimation DIV4 Mode
The MAX108 also offers a special decimated, demultiplexed output (Figure 8) that discards every other input
sample and outputs data at one-quarter the input sampling rate for system debugging at slower output data
rates. With an input clock of 1.5GHz, the effective output
data rate will be reduced to 375MHz per output port in
the DIV4 mode (Table 2). Since every other sample is
discarded, the effective sampling rate is 750Msps.
Overrange Operation
A single differential PECL overrange output bit (OR+,
OR-) is provided for both primary and auxiliary demultiplexed outputs. The operation of the overrange bit
depends on the status of the internal demultiplexer. In
demultiplexed DIV2 mode and decimation DIV4 mode,
the OR bit will flag an overrange condition if either the
primary or auxiliary port contains an overranged sample (Table 2). In non-demultiplexed DIV1 mode, the OR
port will flag an overrange condition only when the primary output port contains an overranged sample.
Applications Information
Single-Ended Analog Inputs
The MAX108 T/H amplifier is designed to work at full
speed for both single-ended and differential analog
inputs (Figure 9). Inputs VIN+ and VIN- feature on-chip,
laser-trimmed 50Ω termination resistors to provide
excellent voltage standing-wave ratio (VSWR) performance.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
16 ______________________________________________________________________________________
Table 2. Demultiplexer Operation
Figure 8. Decimation DIV4-Mode Timing Diagram
X = Don’t care
DIV4
375Msps/port
High
Flags overrange data appearing in either
the primary or auxiliary port.
High
DEMUX MODE
DIV2
750Msps/port
DIV1
750Msps (max)
DIVSELECT
Low
X
OVERRANGE BIT OPERATIONDEMUXEN
High
Low
Flags overrange data appearing in primary
port only.
CLK
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
ADC SAMPLE NUMBER
CLK-
n n+1 n+2 n+3 n+4 n+5
CLK+
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n-2 n+2
PRIMARY
DATA PORT
NOTE: THE LATENCY TO THE PRIMARY PORT REMAINS 7.5 CLOCK CYCLES, WHILE THE LATENCY OF THE AUXILIARY PORT INCREASES TO 9.5 CLOCK CYCLES.
THIS EFFECTIVELY DISCARDS EVERY OTHER SAMPLE AND REDUCES THE OUTPUT DATA RATE TO 1/4 THE SAMPLE CLOCK RATE.
n
n+4
In a typical single-ended configuration, the analog
input signal (Figure 10a) enters the T/H amplifier stage
at the in-phase input (VIN+), while the inverted phase
input (VIN-) is reverse-terminated to GNDI with an
external 50Ω resistor. Single-ended operation allows for
an input amplitude of ±250mV. Table 3 shows a selection of input voltages and their corresponding output
codes for single-ended operation.
Differential Analog Inputs
To obtain a full-scale digital output with differential input
drive (Figure 10b), 250mVp-p must be applied between
VIN+ and VIN- (VIN+ = +125mV, and VIN- = -125mV).
Midscale digital output codes (01111111 or 10000000)
occur when there is no voltage difference between
VIN+ and VIN-. For a zero-scale digital output code, the
in-phase (VIN+) input must see -125mV and the inverted input (VIN-) must see +125mV. A differential input
drive is recommended for best performance. Table 4
represents a selection of differential input voltages and
their corresponding output codes.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 17
Figure 9. Simplified Analog Input Structure (Single-Ended/
Differential)
Figure 10a. Single-Ended Analog Input Signals
Figure 10b. Differential Analog Input Signals
Table 3. Ideal Input Voltage and Output Code Results for Single-Ended Operation
0-250mV 00000000 (zero scale)0V
0-250mV + 1LSB 0000001
00V
01111111
toggles
10000000
0V
0V
0+250mV - 1LSB 111111110V
OUTPUT CODEVIN+ OVERRANGE BIT
1
VIN-
+250mV 11111111 (full scale)0V
ANALOG INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS SIMPLIFIED DRAWING).
+2.8V
VIN+
50Ω
GNDI
50Ω
VIN-
V
EE
V
+250mV
500mVp-p
FS ANALOG
INPUT RANGE
-250mV
500mV
= ±250mV
V
IN
IN+
0V
V
IN-
t
V
+125mV
±250mV
FS ANALOG
INPUT RANGE
-125mV
250mV
IN+
-250mV
V
IN-
0V
t
MAX108
Offset Adjust
The MAX108 provides a control input (VOSADJ) to compensate for system offsets. The offset adjust input is a
self-biased voltage divider from the internal +2.5V precision reference. The nominal open-circuit voltage is onehalf the reference voltage. With an input resistance of
typically 25kΩ, this pin may be driven by an external
10kΩ potentiometer (Figure 11) connected between
REFOUT and GNDI to correct for offset errors. This control provides a typical ±5.5LSB offset adjustment range.
Clock Operation
The MAX108 clock inputs are designed for either single-ended or differential operation (Figure 12) with flexible input drive requirements. Each clock input is
terminated with an on-chip, laser-trimmed 50Ω resistor
to CLKCOM (clock-termination return). The CLKCOM
termination voltage can be connected anywhere
between ground and -2V for compatibility with standard
ECL drive levels.
The clock inputs are internally buffered with a preamplifier to ensure proper operation of the data converter,
even with small-amplitude sine-wave sources. The
MAX108 was designed for single-ended, low-phasenoise sine-wave clock signals with as little as 100mV
amplitude (-10dBm). This eliminates the need for an
external ECL clock buffer and its added jitter.
Single-Ended Clock Inputs (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-coupling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 5). For proper DC balance, the undriven clock input should be externally
50Ω reverse-terminated to GNDI.
The dynamic performance of the data converter is
essentially unaffected by clock-drive power levels from
-10dBm (100mV clock signal amplitude) to +10dBm
(1V clock signal amplitude). The MAX108 dynamic per-
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
18 ______________________________________________________________________________________
Table 4. Ideal Input Voltage and Output Code Results for Differential Operation
OUTPUT CODEVIN+
0-125mV 00000000 (zero scale)+125mV
0-125mV + 0.5LSB 00000001
00V
01111111
toggles
10000000
+125mV - 0.5LSB
0V
OVERRANGE BIT
0+125mV - 0.5LSB 11111111
1
VIN-
+125mV 11111111 (full scale)
-125mV + 0.5LSB
-125mV
Figure 11. Offset Adjust with External 10kΩPotentiometer
Figure 12. Simplified Clock Input Structure (Single-Ended/
Differential)
REFOUT
POT
10k
GNDI
CLK+
50Ω
CLKCOM
50Ω
CLK-
MAX108
VOSADJ
GNDI
+0.8V
CLOCK INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
V
EE
formance specifications are determined by a singleended clock drive of +4dBm (500mV clock signal
amplitude). To avoid saturation of the input amplifier
stage, limit the clock power level to a maximum of
+10dBm.
Differential Clock Inputs (Sine-Wave Drive)
The advantages of differential clock drive (Figure 13b,
Table 5) can be obtained by using an appropriate
balun or transformer to convert single-ended sine-wave
sources into differential drives. The precision on-chip,
laser-trimmed 50Ω clock-termination resistors ensure
excellent amplitude matching. See
Single-Ended Clock
Inputs (Sine-Wave Drive)
for proper input amplitude
requirements.
Single-Ended Clock Inputs (ECL Drive)
Configure the MAX108 for single-ended ECL clock
drive by connecting the clock inputs as shown in Figure
13c (Table 5). A well-bypassed VBBsupply (-1.3V) is
essential to avoid coupling noise into the undriven
clock input, which would degrade dynamic performance.
Differential Clock Inputs (ECL Drive)
Drive the MAX108 from a standard differential (Figure
13d, Table 5) ECL clock source by setting the clock termination voltage at CLKCOM to -2V. Bypass the clocktermination return (CLKCOM) as close to the ADC as
possible with a 0.01µF capacitor connected to GNDI.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 19
Figure 13a. Single-Ended Clock Input Signals
Figure 13b. Differential Clock Input Signals
Figure 13c. Single-Ended ECL Clock Drive
Figure 13d. Differential ECL Clock Drive
+0.5V
CLK+
CLK- = 0V
CLK+
+0.5V
CLK-
-0.5V
NOTE: CLKCOM = 0V
-0.8V
-1.8V
NOTE: CLKCOM = -2V
CLK+
CLK- = -1.3V
t
t
-0.5V
NOTE: CLKCOM = 0V
CLK+
-0.8V
-1.8V
NOTE: CLKCOM = -2V
t
CLK-
t
MAX108
AC-Coupling Clock Inputs
The clock inputs CLK+ and CLK- can be driven with
PECL logic if the clock inputs are AC-coupled. Under
this condition, connect CLKCOM to GNDI. Singleended ECL/PECL/sine-wave drive is also possible if the
undriven clock input is reverse-terminated to GNDI
through a 50Ω resistor in series with a capacitor whose
value is identical to that used to couple the driven
input.
Demux Reset Operation
The MAX108 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to onehalf the sample clock rate. Demux reset is necessary
when interleaving multiple MAX108s and/or synchronizing external demultiplexers. The simplified block diagram of Figure 1 shows that the demux reset signal path
consists of four main circuit blocks. From input to output, they are the reset input dual latch, the reset
pipeline, the demux clock generator, and the reset output. The signals associated with the demux reset operation and the control of this section are listed in Table 6.
Reset Input Dual Latch
The reset input dual-latch circuit block accepts differential PECL reset inputs referenced to the same VCCO
power supply that powers the MAX108 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50kΩ
resistors and 20µA current source. This combination
creates a -1V difference between RSTIN+ and RSTINto disable the internal reset circuitry. When driven with
PECL logic levels terminated with 50Ω to (VCCO - 2V),
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.
To properly latch the reset input data, the setup time
(tSU) and the data-hold time (tHD) must be met with
respect to the rising edge of the sample clock. The timing diagram of Figure 15 shows the timing relationship
of the reset input and sampling clock.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
20 ______________________________________________________________________________________
Table 5. DC-Coupled Clock Drive Options
-2VDifferential ECL Figure 13d
ECL Drive
ECL Drive
-2VSingle-Ended ECL Figure 13c-1.3VECL Drive
GNDIDifferential Sine Wave Figure 13b-10dBm to +4dBm-10dBm to +4dBm
CLK-
External 50Ω to GNDI
REFERENCECLOCK DRIVE CLKCOM
GNDI
CLK+
Single-Ended Sine Wave Figure 13a-10dBm to +4dBm
Figure 14. Simplified Reset Input Structure
Figure 15. Reset Input Timing Definitions
RSTIN+
RSTIN-
RESET INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
50k50k
20µA
50% 50%
t
SU
GNDD
RSTIN+
RSTIN-
t
HD
CLK+
50%
CLK-
O
V
CC
Reset Pipeline
The next section in the reset signal path is the reset
pipeline. This block adds clock cycles of latency to the
reset signal to match the latency of the converted analog data through the ADC. In this way, when reset data
arrives at the RSTOUT+/RSTOUT- PECL output it will be
time-aligned with the analog data present in the primary and auxiliary ports at the time the reset input was
deasserted at RSTIN+/RSTIN-.
Demux Clock Generator
The demux clock generator creates the DIV1, DIV2, or
DIV4 clocks required for the different modes of demux
and non-demultiplexed operation. The TTL/CMOS control inputs DEMUXEN and DIVSELECT control the
demuxed mode selection, as described in Table 2. The
timing diagrams in Figures 16 and 17 show the output
timing and data alignment in DIV1, DIV2, and DIV4
modes, respectively.
The phase relationship between the sampling clock at
the CLK+/CLK- inputs and the data-ready clock at the
Dready+/Dready- outputs will be random at device
power-up. As with all divide-by-two circuits, two possible phase relationships exist between these clocks.
The difference between the phases is simply the inversion of the DIV2-Dready clock. The timing diagram in
Figure 16 shows this relationship.
Reset all MAX108 devices to a known DREADY phase
after initial power-up for applications such as interleaving, where two or more MAX108 devices are used to
achieve higher effective sampling rates. This synchronization is necessary to set the order of output samples
between the devices. Resetting the converters accomplishes this synchronization. The reset signal is used to
force the internal counter in the demux clock-generator
block to a known phase state.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 21
Table 6. Demux Operating and Reset Control Signals
Figure 16. CLK and DREADY Timing in Demuxed DIV2 Mode
Showing Two Possible DREADY Phases
Figure 17. Output Timing for All Modes (DIV1, DIV2, DIV4)
FUNCTIONSIGNAL NAME
RSTOUT+, RSTOUT- Reset outputs for resetting additional external demux devices.Differential PECL outputs
RSTIN+, RSTIN- Demux reset input signals. Resets the internal demux when asserted.Differential PECL inputs
DREADY+, DREADY-
Data-Ready PECL Output. Output data changes on the rising edge of
DREADY+.
Differential PECL outputs
TYPE
CLK+, CLK- Master ADC timing signal. The ADC samples on the rising edge of CLK+.Sampling clock inputs
CLK+
50%
t
DREADY-
DREADY+
PD1
"PHASE 1"
t
FDREADY
DREADY +
80% 80%
"PHASE 2"
DREADY -
CLK-
50%
20% 20%
t
RDREADY
t
PWH
CLK+
CLK-
AUXILIARY PORT DATA
PRIMARY PORT DATA
t
PWL
t
PD1
t
PD2
DREADY +
DREADY -
MAX108
Reset Output
Finally, the reset signal is presented in differential PECL
format to the last block of the reset signal path.
RSTOUT+/RSTOUT- output the time-aligned reset signal, used for resetting additional external demuxes in
applications that need further output data-rate reduction. Many demux devices require their reset signal to
be asserted for several clock cycles while they are
clocked. To accomplish this, the MAX108 DREADY
clock will continue to toggle while RSTOUT is asserted.
When a single MAX108 device is used, no synchronizing reset is required because the order of the samples
in the output ports is unchanged, regardless of the
phase of the DREADY clock. In DIV2 mode, the data in
the auxiliary port is delayed by 8.5 clock cycles, while
the data in the primary port is delayed by 7.5 clock
cycles. The older data is always in the auxiliary port,
regardless of the phase of the DREADY clock.
The reset output signal, RSTOUT, is delayed by one
fewer clock cycles (6.5 clock cycles) than the primary
port. The reduced latency of RSTOUT serves to mark
the start of synchronized data in the primary and auxiliary ports. When the RSTOUT signal returns to a zero,
the DREADY clock phase is reset.
Since there are two possible phases of the DREADY
clock with respect to the input clock, there are two possible timing diagrams to consider. The first timing diagram (Figure 18) shows the RSTOUT timing and data
alignment of the auxiliary and primary output ports
when the DREADY clock phase is already reset. For
this example, the RSTIN pulse is two clock cycles long.
Under this condition, the DREADY clock continues
uninterrupted, as does the data stream in the auxiliary
and primary ports.
The second timing diagram (Figure 19) shows the
results when the DREADY phase is opposite from the
reset phase. In this case, the DREADY clock “swallows”
a clock cycle of the sample clock, resynchronizing to
the reset phase. Note that the data stream in the auxiliary and primary ports has reversed. Before reset was
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
22 ______________________________________________________________________________________
Figure 18. Reset Output Timing in Demuxed DIV2 Mode (DREADY Aligned)
CLK
RESET
INPUT
DREADY
ADC SAMPLE NUMBER
CLK-
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
CLK+
RSTIN-
RSTIN+
DREADY-
DREADY+
t
SU
ADC SAMPLES ON THE RISING EDGE OF CLK+
t
HD
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
RESET OUT
DATA PORT
NOTE: THE LATENCY TO THE RESET OUTPUT IS 6.5 CLOCK CYCLES. THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND
THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. ALL DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
RSTOUT-
RSTOUT+
n n+2 n+4
n+1n-1 n+3
asserted, the auxiliary port contained “even” samples
while the primary port contained “odd” samples. After
the RSTOUT is deasserted (which marks the start of the
DREADY clock’s reset phase), note that the order of the
samples in the ports has been reversed. The auxiliary
port also contains an out-of-sequence sample. This is a
consequence of the “swallowed” clock cycle that was
needed to resynchronize DREADY to the reset phase.
Also note that the older sample data is always in the
auxiliary port, regardless of the DREADY phase.
These examples illustrate the combinations that result
with a reset input signal of two clock cycles. It is also
possible to reset the internal MAX108 demux successfully with a reset pulse of only one clock cycle, provided that the setup time and hold-time requirements are
met with respect to the sample clock. However, this is
not recommended when additional external demuxes
are used.
Note that many external demuxes require their reset
signals to be asserted while they are clocked, and may
require more than one clock cycle of reset. More importantly, if the phase of the DREADY clock is such that a
clock pulse will be “swallowed” to resynchronize, then
no reset output will occur at all. In effect, the RSTOUT
signal will be “swallowed” with the clock pulse. The
best method to ensure complete system reset is to
assert RSTIN for the appropriate number of DREADY
clock cycles required to complete reset of the external
demuxes.
Die Temperature Measurement
For applications that require monitoring of the die temperature, it is possible to determine the die temperature
of the MAX108 under normal operating conditions by
observing the currents I
CONST
and I
PTAT
, at contacts
ICONST and IPTAT. I
CONST
and I
PTAT
are two 100µA
(nominal) currents that are designed to be equal at
+27°C. These currents are derived from the MAX108’s
internal precision +2.5V bandgap reference. I
CONST
is
designed to be temperature independent, while I
PTAT
is
directly proportional to the absolute temperature. These
currents are derived from PNP current sources referenced from VCCI and driven into two series diodes connected to GNDI. The contacts ICONST and IPTAT may
be left open because internal catch diodes prevent saturation of the current sources. The simplest method of
determining the die temperature is to measure each
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 23
Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)
ADC SAMPLE NUMBER
CLK-
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
CLK
CLK+
RESET
INPUT
DREADY
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
RESET OUT
DATA PORT
NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.
THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.
t
SU t
RSTIN-
RSTIN+
DREADY+
DREADY-
RSTOUT-
RSTOUT+
ADC SAMPLES ON THE RISING EDGE OF CLK+
HD
n-2
n-1 n+1
CLOCK PULSE “SWALLOWED”
OUT-OF-SEQUENCE SAMPLE
n
n+2
n+4
MAX108
current with an ammeter (which shuts off the internal
catch diodes) referenced to GNDI. The die temperature
in °C is then calculated by the expression:
Another method of determining the die temperature
uses the operational amplifier circuit shown in Figure
20. The circuit produces a voltage that is proportional
to the die temperature. A possible application for this
signal is speed control for a cooling fan to maintain
constant MAX108 die temperature. The circuit operates
by converting the I
CONST
and I
PTAT
currents to volt-
ages V
CONST
and V
PTAT
, with appropriate scaling to
account for their equal values at +27°C. This voltage
difference is then amplified by two amplifiers in an
instrumentation-amplifier configuration with adjustable
gain. The nominal value of the circuit gain is 4.5092V/V.
The gain of the instrumentation amplifier is given by the
expression:
To calibrate the circuit, first connect pins 2 and 3 on
JU1 to zero the input of the PTAT path. With the
MAX108 powered up, adjust potentiometer R3 until the
voltage at the V
TEMP
output is -2.728V. Connecting
pins 1 and 2 on JU1 restores normal operation to the
circuit after the calibration is complete. The voltage at
the V
TEMP
node will then be proportional to the actual
MAX108 die temperature according to the equation:
T
DIE
(°C) = 100 V
TEMP
The overall accuracy of the die temperature measurement using the operational-amplifier scaling circuitry is
limited mainly by the accuracy and matching of the
resistors in the circuit.
Thermal Management
Depending on the application environment for the
ESBGA-packaged MAX108, the customer may have to
apply an external heatsink to the package after board
assembly. Existing open-tooled heatsinks are available
from standard heatsink suppliers (see
Heatsink
Manufacturers
). The heatsinks are available with preap-
plied adhesive for easy package mounting.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
24 ______________________________________________________________________________________
Figure 20. Die Temperature Acquisition Circuit with the MAX479
T
=
DIE
I
PTAT
I
CONST
−300 273
=
A
V
=+ +1
A
V
V
TEMP
−
VV
CONST PTAT
1
R
2
R
1
R
2
3
R
3.32k
6.65k
R1
I
PTAT
12.1k
6.65k
I
CONST
1/4 MAX479
12.1k
1/4 MAX479
6.05k
2
JU1
1
3
7.5k
V
PTAT
V
CONST
R2
15k
1/4 MAX479
5k
10-TURN
R2
15k
R1
7.5k
1/4 MAX479
V
TEMP
Thermal Performance
The MAX108 has been modeled to determine the thermal resistance from junction to ambient. Table 7 lists
the ADC’s thermal performance parameters:
Ambient Temperature: TA= +70°C
Heatsink Dimensions: 25mm x 25mm x 10mm
PC Board Size and Layout: 4 in. x 4 in.
2 Signal Layers
2 Power Layers
Heatsink Manufacturers
Aavid Engineering and IERC provide open-tooled, lowprofile heatsinks, fitting the 25mm x 25mm ESBGA
package.
Aavid Engineering, Inc.
Phone: 714-556-2665
Heatsink Catalog No.: 335224B00032
Heatsink Dimensions: 25mm x 25mm x 10mm
International Electronic Research Corporation (IERC)
Phone: 818-842-7277
Heatsink Catalog No.: BDN09-3CB/A01
Heatsink Dimensions: 23.1mm x 23.1mm x 9mm
Bypassing/Layout/Power Supply
Grounding and power-supply decoupling strongly influence the MAX108’s performance. At a 1.5GHz clock
frequency and 8-bit resolution, unwanted digital
crosstalk may couple through the input, reference,
power-supply, and ground connections and adversely
influence the dynamic performance of the ADC.
Therefore, closely follow the grounding and power-supply decoupling guidelines (Figure 22).
Maxim strongly recommends using a multilayer printed
circuit board (PCB) with separate ground and powersupply planes. Since the MAX108 has separate analog
and digital ground connections (GNDA, GNDI, GNDR,
and GNDD, respectively), the PCB should feature separate analog and digital ground sections connected at
only one point (star ground at the power supply). Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane. Keep digital signals far away from the sensitive
analog inputs, reference inputs, and clock inputs. Highspeed signals, including clocks, analog inputs, and
digital outputs, should be routed on 50Ω microstrip
lines, such as those employed on the MAX108 evaluation kit.
The MAX108 has separate analog and digital powersupply inputs: V
EE
(-5V analog and substrate supply)
and VCCI (+5V) to power the T/H amplifier, clock distribution, bandgap reference, and reference amplifier;
VCCA (+5V) to supply the ADC’s comparator array;
VCCO (+3V to VCCD) to establish power for all PECLbased circuit sections; and VCCD (+5V) to supply all
logic circuits of the data converter.
The MAX108 VEEsupply contacts must not be left
open while the part is being powered up. To avoid this
condition, add a high-speed Schottky diode (such as a
Motorola 1N5817) between VEEand GNDI. This diode
prevents the device substrate from forward biasing,
which could cause latchup.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 25
Figure 21. MAX108 Thermal Performance
Table 7. Thermal Performance for
MAX108 With or Without Heatsink
16.5 12.5
AIRFLOW
(linear ft/min)
0
MAX108 θJA(°C/W)
14.3 9.4200
13 8.3400
12.5 7.4800
WITHOUT
HEATSINK
WITH HEATSINK
THERMAL RESISTANCE vs. AIRFLOW
18
16
14
12
(°C/W)
JA
θ
10
8
6
0 200100 300 400 500 600 700 800
AIRFLOW (linear ft./min.)
WITHOUT
HEATSINK
WITH HEATSINK
MAX108
All supplies should be decoupled with large tantalum or
electrolytic capacitors at the point they enter the PCB.
For best performance, bypass all power supplies to the
appropriate ground with a 10µF tantalum capacitor to
filter power-supply noise, in parallel with a 0.1µF
capacitor and a high-quality 47pF ceramic chip capacitor located very close to the MAX108 device to filter
very high-frequency noise.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX108 are measured using the best-straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
26 ______________________________________________________________________________________
Figure 22. MAX108 Bypassing and Grounding
O
V
CC
10nF 10nF 47pF 47pF 47pF 47pF
GNDD
V
10µF
I
CC
NOTE:
LOCATE ALL 47pF CAPACITORS AS CLOSE
AS POSSIBLE TO THE MAX108 DEVICE.
GNDI
V
CC
GNDA
V
CC
GNDD
10µF 10nF 10nF 47pF 47pF 47pF 47pF
A
10µF 10nF 10nF 47pF 47pF
D
10µF 10nF 10nF 47pF 47pF 47pF 47pF
V
GNDI
EE
1N5817
10µF
10nF 10nF 47pF 47pF 47pF 47pF
VCCA = +4.75V TO +5.25V
VCCD = +4.75V TO +5.25V
VCCI = +4.75V TO +5.25V
VCCO = +3.0V TO VCCD
VEE = -4.75V TO -5.25V
Bit Error Rates
Errors resulting from metastable states may occur when
the analog input voltage (at the time the sample is
taken) falls close to the decision point of any one of the
input comparators. Here, the magnitude of the error
depends on the location of the comparator in the comparator network. If it is the comparator for the MSB, the
error will reach full scale. The MAX108’s unique encoding scheme solves this problem by limiting the magnitude of these errors to 1LSB.
Dynamic Parameter Definitions
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
(MAX)
= (6.02 N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is calculated by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Effective Number of Bits
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is calculated from a curve fit referenced to the theoretical full-scale range.
Signal-to-Noise Plus Distortion
Signal-to-Noise plus distortion (SINAD) is calculated
from the ENOB as follows:
SINAD = (6.02 ENOB) + 1.76
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio,
expressed in decibels, of the RMS amplitude of the fundamental (maximum signal component) to the RMS
value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion
The two-tone intermodulation distortion (IMD) is the
ratio, expressed in decibels, of either input tone to the
worst 3rd-order (or higher) intermodulation products.
The input tone levels are at -7dB full scale.
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 27
Chip Information
TRANSISTOR COUNT: 20,486
SUBSTRATE CONNECTED TO V
EE
THD 20 log V V V V / V
=+++
2232425
2
1
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
28 ______________________________________________________________________________________
Typical Operating Circuit
-5V ANALOG
V
DIVSELECT
+5V ANALOG
EEVCC
+5V DIGITAL
AVCCIVCCDV
+3.3V DIGITAL
OAUXEN1 AUXEN2
CC
OR+/OR-
2
Z
= 50Ω
0
ALL PECL OUTPUTS
MUST BE TERMINATED
LIKE THIS.
50Ω
V
O - 2V
CC
DIFFERENTIAL
ANALOG
INPUT
500mVp-p FS
SAMPLE
CLOCK
1.5GHz
+4dBm
+5V DIGITAL
Z
Z
Z
50Ω
= 50Ω
0
= 50Ω
0
= 50Ω
0
GNDI
GNDI
DEMUXEN
VOSADJ
VIN+
VIN-
CLK+
CLK-
CLKCOM
MAX108
PRIMARY
PECL
OUTPUTS
AUXILARY
PECL
OUTPUTS
2
2
2
2
2
2
2
P7+/P7-
2
P6+/P6-
P5+/P5-
2
P4+/P4-
P3+/P3-
2
P2+/P2-
P1+/P1-
2
P0+/P0-
A7+/A7-
2
A6+/A6-
A5+/A5-
2
A4+/A4-
A3+/A3-
2
A2+/A2-
TO MEMORY OR DIGITAL SIGNAL PROCESSOR
A1+/A1-
2
RSTIN+
RSTIN-
GNDA
GNDR GNDI GNDD REFOUT REFIN
DREADY+/DREADY-
RSTOUT+/RSTOUT-
2
2
A0+/A0-
2
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 29
192-Contact ESBGA PCB Land Pattern
TOP VIEW
MAX108 192 Ball ESBGA
Printed Circuit Board (PCB) Land Pattern
MAX108
+5V Track/Hold Analog
+5V Comparator Analog
+5V Logic Digital
-5V Track/Hold Analog
+3.3V PECL Supply
T/H Ground
Comparator Ground
Logic Ground
VCCI
VCCA
VCCD
VEE
VCCO
GNDI
GNDA
GNDD
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
30 ______________________________________________________________________________________
Package Information
SUPER BGA.EPS
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
______________________________________________________________________________________ 31
Package Information (continued)
MAX108
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES
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