Rainbow Electronics MAX106 User Manual

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX106 PECL-compatible, 600Msps, 8-bit analog-to­digital converter (ADC) allows accurate digitizing of ana­log signals with bandwidths to 2.2GHz. Fabricated on
Maxim’s proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.

The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of­sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 1027clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out­puts, the MAX106 limits the error magnitude to 1LSB.

The analog input is designed for either differential or sin­gle-ended use with a ±250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.

The MAX106 is packaged in a 25mm x 25mm, 192-con­tact Enhanced Super-Ball-Grid Array (ESBGA™), and is
specified over the commercial (0°C to +70°C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.

Applications

Digital RF/IF Signal Processing

Direct RF Downconversion

High-Speed Data Acquisition

Digital Oscilloscopes

High-Energy Physics

Radar/ECM Systems

ATE Systems

Features

♦ 600Msps Conversion Rate

♦ 2.2GHz Full-Power Analog Input Bandwidth

♦ 7.6 Effective Bits at f

IN

= 300MHz

(Nyquist frequency)

♦ ±0.25LSB INL and DNL
♦ 50Ω Differential Analog Inputs

♦ ±250mV Input Signal Range

♦ On-Chip, +2.5V Precision Bandgap Voltage

Reference

♦ Latched, Differential PECL Digital Outputs

♦ Low Error Rate: 10

-27

Metastable States

♦ Selectable 8:16 Demultiplexer

♦ Internal Demux Reset Input with Reset Output

♦ 192-Contact ESBGA

♦ Pin Compatible with Faster MAX104/MAX108

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

________________________________________________________________ Maxim Integrated Products 1

19-1486; Rev 1; 11/01

PART

MAX106CHC 0°C to +70°C

TEMP RANGE PIN-PACKAGE

192 ESBGA

Typical Operating Circuit appears at end of data sheet.

Ordering Information

ESBGA

TOP VIEW

MAX106

192-Contact ESBGA

Ball Assignment Matrix

ESBGA is a trademark of Amkor/Anam.

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCA to GNDA .........................................................-0.3V to +6V

VCCD to GNDD.........................................................-0.3V to +6V

VCCI to GNDI............................................................-0.3V to +6V

VCCO to GNDD........................................-0.3V to (VCCD + 0.3V)

AUXEN1, AUXEN2 to GND .....................-0.3V to (V

CC

D + 0.3V)

VEEto GNDI..............................................................-6V to +0.3V

Between GNDs......................................................-0.3V to +0.3V

VCCA to VCCD .......................................................-0.3V to +0.3V

VCCA to VCCI.........................................................-0.3V to +0.3V

PECL Digital Output Current ...............................................50mA

REFIN to GNDR ........................................-0.3V to (V

CC

I + 0.3V)

REFOUT Current ................................................+100µA to -5mA

ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V

TTL/CMOS Control Inputs

(DEMUXEN, DIVSELECT) ....................-0.3V to (V

CC

D + 0.3V)

RSTIN+, RSTIN- ......................................-0.3V to (V

CC

O + 0.3V)

VOSADJ Adjust Input ................................-0.3V to (V

CC

I + 0.3V)

CLK+ to CLK- Voltage Difference..........................................±3V

CLK+, CLK-.....................................(VEE- 0.3V) to (GNDD + 1V)

CLKCOM.........................................(VEE- 0.3V) to (GNDD + 1V)

VIN+ to VIN- Voltage Difference ............................................±2V

VIN+, VIN- to GNDI................................................................±2V

Continuous Power Dissipation (T

A

= +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C) ...4.88W
(with heatsink and 200LFM airflow,

derate 106mW/°C above +70°C) ....................................8.48W

Operating Temperature Range

MAX106CHC........................................................0°C to +70°C

Operating Junction Temperature.....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

TA= +25° C

Referenced to GNDR

0 < I

SOURCE

< 2.5mA

Driving REFIN input only

VIN+ and VIN- to GNDI, TA= +25°C

VOSADJ = 0 to 2.5V

Signal + offset w.r.t. GNDI

TA= +25° C

No missing codes guaranteed

CONDITIONS

kΩ

45

R

REF

Reference Input Resistance

mV5∆REFOUT

Reference Output Load
Regulation

V

2.475 2.50 2.525

REFOUTReference Output Voltage

LSB

±4 ±5.5

Input VOSAdjust Range

kΩ

14 25

R

VOS

Input Resistance (Note 2)

ppm/°C

150

TC

R

Input Resistance Temperature
Coefficient

LSB

-0.5 ±0.25 0.5

INLIntegral Nonlinearity (Note 1)

Bits

8

RESResolution

Ω

49 50 51

R

IN

Input Resistance

V

±0.8

V

CM

Common-Mode Input Range

mVp-p

475 500 525

V

FSR

Full-Scale Input Range (Note 1)

LSB

-0.5 ±0.25 0.5

DNLDifferential Nonlinearity (Note 1)

CodesNoneMissing Codes

UNITSMIN TYP MAXSYMBOLPARAMETER

ACCURACY

ANALOG INPUTS

VOSADJUST CONTROL INPUT

REFERENCE INPUT AND OUTPUT

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

CLK+ and CLK- to CLKCOM, TA= +25°C

CONDITIONS

ppm/°C

150

TC

R

Input Resistance Temperature
Coefficient

Ω

48 50 52

R

CLK

Clock Input Resistance

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 10)

(Note 9)

VIN+ = VIN- = ±0.1V

VIH= 2.4V

VIL= 0

dB

40 68

PSRR-

Negative Power-Supply
Rejection Ratio (Note 8)

dB

40 73

PSRR+

Positive Power-Supply Rejection
Ratio (Note 8)

dB

40 68

CMRR

Common-Mode Rejection Ratio
(Note 7)

W

5.25

P

DISS

Power Dissipation (Note 6)

Output Supply Current (Note 6) mA

75 115

ICCO

mA

205 340

ICCDDigital Supply Current

mA

-290 -210

I

EE

Negative Input Supply Current

mA

108 150

I

CCI

Positive Input Supply Current

mA

480 780

I

CCA

Positive Analog Supply Current

V0.8V

IL

Low-Level Input Voltage

V

2.0

V

IH

High-Level Input Voltage

V

-1.810 -1.620

V

OL

Digital Output Low Voltage

V

-1.025 -0.880

V

OH

Digital Output High Voltage

V-1.475V

IL

Digital Input Low Voltage

µA

50

I

IH

High-Level Input Current

µA

-1 1

I

IL

Low-Level Input Current

V

-1.165

V

IH

Digital Input High Voltage

CLOCK INPUTS (Note 3)

TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)

DEMUX RESET INPUT (Note 4)

PECL DIGITAL OUTPUTS (Note 5)

POWER REQUIREMENTS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

4 _______________________________________________________________________________________

fIN= 600MHz

fIN= 500MHz

fIN= 125MHz

fIN= 300MHz

fIN= 600MHz

fIN= 600MHz

fIN= 125MHz

fIN= 300MHz

fIN= 125MHz

fIN= 300MHz

CONDITIONS

56.7

dB

57.4

SFDR

600

Spurious-Free Dynamic
Range

-67.5

-67.5 -63

THD

125

-56.5

-56.5 -52

THD

300

-56.1

dB

-57.0

THD

600

Total Harmonic Distortion
(Note 12)

47.4

45 47.4

SNR

125

47.1

44.8 47.1

SNR

300

46.8

V/V1.1:1VSWRAnalog Input VSWR

GHz2.2BW

-3dB

Analog Input Full-Power
Bandwidth

dB

46.8

SNR

600

Signal-to-Noise Ratio
(No Harmonics)

7.74

7.4 7.74

ENOB

125

7.65

Bits

7.63

ENOB

600

7.62

7.3 7.65

ENOB

300

Effective Number of Bits
(Note 11)

UNITSMIN TYP MAXSYMBOLPARAMETER

fIN= 125MHz

fIN= 300MHz

f

IN

1

= 124MHz, f

IN2

= 126MHz,

at -7dB below full scale

fIN= 125MHz

fIN= 300MHz

63.0 69.9

SFDR

125

57.4

52.0 57.5

SFDR

300

dB-61.8IMDTwo-Tone Intermodulation

47.4

45.3 47.4

SINAD

125

46.8

69.9

dB

46.7

SINAD

600

Signal-to-Noise Ratio and
Distortion

46.6

44.7 46.8

SINAD

300

fIN= 600MHz

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

fIN= 600MHz

Differential

Single-ended

Differential

Single-ended

Differential

Single-ended

AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

VOSADJ control input open LSB-2 0 +2V

OS

Transfer Curve Offset

ANALOG INPUT

DYNAMIC SPECIFICATIONS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 5

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

Figure 17

Figure 17

Figure 15

Figure 15

Figure 4

Figure 17

ps220t

RDREADY

DREADY Rise Time

ps360t

FDATA

DATA Fall Time

ps420t

RDATA

DATA Rise Time

ps-50 150 350t

PD2

DREADY to DATA Propagation
Delay (Note 14)

ns2.2t

PD1

CLK to DREADY Propagation
Delay

ps0t

HD

Reset Input Data Hold Time
(Note 13)

ps0t

SU

Reset Input Data Setup Time
(Note 13)

ps< 0.5t

AJ

Aperture Jitter

ps100t

AD

Aperture Delay

DIV1, DIV2 modes

DIV1, DIV2 modes

20% to 80%, CL= 3pF

9.5

Clock

Cycles

8.5

t

PDA

Auxiliary Port Pipeline Delay

Clock

Cycles

7.5

t

PDP

Primary Port Pipeline Delay

ps180t

FDREADY

DREADY Fall Time

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale

range (FSR) is defined as 256

· slope of the line.

Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit

voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.

Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on

the CLK+ and CLK- inputs.

Note 4: Input logic levels are measured with respect to the V

CC

O power-supply voltage.

Note 5: All PECL digital outputs are loaded with 50Ω to V

CC

O - 2.0V. Measurements are made with respect to the VCCO power-

supply voltage.

Note 6: The current in the V

CC

O power supply does not include the current in the digital output’s emitter followers, which is a func-

tion of the load resistance and the V

TT

termination voltage.

Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the

common-mode voltage, expressed in dB.

Note 8: Measured with the positive supplies tied to the same potential, V

CC

A = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.

Note 9: V

EE

varies from -5.25V to -4.75V.

Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power

supply voltage, expressed in dB.

Note 11: Effective number of bits (ENOB) are computed from a curve fit referenced to the theoretical full-scale range.

7.5

Msps600f

MAX

Maximum Sample Rate

Figure 17 ns0.75t

PWL

Clock Pulse WidthLow

Figure 17 ns0.75 5t

PWH

Clock Pulse Width High

TIMING CHARACTERISTICS

Figures 6, 7, and 8

Figures 6, 7, and 8

DIV4 mode

DIV4 mode

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

8.00

10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc01

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

6.75

6.50

7.25

7.50

7.00

7.75

-6dBFS

-1dBFS

-12dBFS

8.00

10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc02

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

6.75

6.50

7.25

7.50

7.00

7.75

-6dBFS

-1dBFS

-12dBFS

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc03

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

100

35

40

45

50

55

30

10 1000

-1dB FS

-6dB FS

-12dB FS

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc04

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

100

35

40

45

50

55

30

10 1000

-1dB FS

-6dB FS

-12dB FS

50

10 100 1000

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc05

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

30

38

42

34

46

-1dBFS

-12dBFS

-6dBFS

50

10 100 1000

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

MAX106 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

30

38

42

34

46

-6dBFS

-1dBFS

-12dBFS

Note 12: Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse width of one clock period or longer.
Note 14: Guaranteed by design. The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the

DREADY signal (when the output data changes) to the 50% point on a data output bit. This places the falling edge of the
DREADY signal in the middle of the data output valid window, within the differences between the DREADY and DATA rise
and fall times, which gives maximum setup and hold time for latching external data latches.

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

75

10 100 1000

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

MAX106 toc09

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

50

60

65

55

70

-12dBFS

-6dBFS

-1dBFS

8.00

7.75

SINGLE-ENDED CLOCK DRIVE

7.50

SFDR (dB)

EFFECTIVE NUMBER OF BITS

vs. CLOCK POWER

DIFFERENTIAL CLOCK DRIVE

MAX106toc12

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

75

70

65

60

55

50

10 100 1000

-6dBFS

-12dBFS

ANALOG INPUT FREQUENCY (MHz)

-1dBFS

EFFECTIVE NUMBER OF BITS vs.

I = VCCA = VCCD

V

8.00

7.75

7.50

CC

MAX106 toc10

MAX106toc13

EFFECTIVE NUMBER OF BITS vs.

CLOCK FREQUENCY

8.00

7.75

7.50

7.25

ENOB (Bits)

7.00

6.75

fIN = 125MHz, -1dBFS

6.50
100 600

CLOCK FREQUENCY (MHz)

EFFECTIVE NUMBER OF BITS vs. V

8.00

7.75

7.50

EE

MAX106 toc11

MAX106toc14

7.25

ENOB (Bits)

7.00

6.75

6.50

-12 -8 -6 -4-10 -20246810

SPURIOUS-FREE DYNAMIC RANGE

75

73

SINGLE-ENDED CLOCK DRIVE

71

69

DIFFERENTIAL CLOCK DRIVE

67

65

SFDR (dB)

63

61

59

57

55

-12 -8 -6-10 -4-20246810

f

= 125MHz, -1dBFS

IN

CLOCK POWER PER SIDE (dBm)

vs. CLOCK POWER

CLOCK POWER PER SIDE (dBm)

fIN = 125MHz, -1dBFS

MAX106 toc15

7.25

ENOB (Bits)

7.00

6.75

6.50

4.50 5.304.70 5.504.90 5.10

SPURIOUS-FREE DYNAMIC RANGE

I = VCCA = VCCD

vs. V

75

74

73

72

71

70

SFDR (dB)

69

68

67

66

65

4.50 5.304.70 5.504.90 5.10

CC

f

= 125MHz, -1dBFS

IN

VCC (V)

fIN = 125MHz, -1dBFS

V

(V)

CC

MAX106 toc16

7.25

ENOB (Bits)

7.00

6.75

6.50

SPURIOUS-FREE DYNAMIC RANGE

75

74

73

72

71

70

SFDR (dB)

69

68

67

66

65

VEE (V)

vs. V

V

EE

EE

f

IN

(V)

-4.50-5.30 -4.70-5.50 -4.90-5.10

= 125MHz, -1dBFS

MAX106 toc17

-4.50-5.30 -4.70-5.50 -4.90-5.10

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

THD (dB)

-25.6

-51.2

-76.8

AMPLITUDE (dB)

TOTAL HARMONIC DISTORTION

-60

-61

-62

-63

-64

-65

-66

-67

-68

-69

-70

= 304.4677734MHz, RECORD LENGTH 8192)

(f

IN

0

ENOB = 7.67 BITS
SNR = 47.2dB
THD = -56.8dB
SFDR = 57.4dB

H2

vs. V

EE

f

IN

V

(V)

EE

FFT PLOT

FUNDAMENTAL

= 125MHz, -1dBFS

H3

-4.50-5.30 -4.70-5.50 -4.90-5.10

MAX106 toc18

MAX106 toc21

THD (dB)

-25.6

-51.2

-76.8

AMPLITUDE (dB)

TOTAL HARMONIC DISTORTION

I = VCCA = VCCD

vs. V

-60

-61

-62

-63

-64

-65

-66

-67

-68

-69

-70

4.50 4.70 4.90 5.10 5.30 5.50

CC

VCC (V)

FFT PLOT

= 1001.8798828MHz, RECORD LENGTH 8192)

(f

IN

0

ENOB = 7.48 BITS
SNR = 46.0dB
THD = -52.9dB
SFDR = 54.7dB

H3

FUNDAMENTAL

H2

MAX106 toc19

MAX106 toc22

= 125.1708984MHz, RECORD LENGTH 8192)

(f

IN

0

FUNDAMENTAL

-25.6

-51.2

-76.8

AMPLITUDE (dB)

-102.4

-128.0
0 12060 180 240 300

ANALOG INPUT FREQUENCY (MHz)

ENOB = 7.75 BITS
SNR = 47.5dB
THD = -68.8dB
SFDR = 70.8dB

H3

TWO-TONE INTERMODULATION DISTORTION

FFT PLOT (RECORD LENGTH 8192,

-7dB BELOW FULL-SCALE)

FFT PLOT

0

-25.6

-51.2
(2 x f1) - f

-76.8

AMPLITUDE (dB)

f

1

f

2

2

f1 = 123.9990235MHz

= 126.0498047MHz

f

2

SFDR = 61.6dB

(2 x f2) - f

MAX106 toc20

H2

MAX106 toc23

1

MAX106toc24

-102.4

-128.0
0 12060 180 240 300

ANALOG INPUT FREQUENCY (MHz)

ANALOG INPUT BANDWIDTH

FULL-POWER

0

-1

-2

-3

AMPLITUDE (dB)

-4

FULL-POWER BANDWIDTH = 2.2GHz

-5

ANALOG INPUT FREQUENCY (MHz)

500 1500 2500

MAX106toc25

-102.4

-128.0
0 12060 180 240 300

ANALOG INPUT FREQUENCY (MHz)

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO-LOOP DATA)

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5
0 32 64 96 128 160 192 224 256

OUTPUT CODE

-102.4

-128.0
0 12060 180 240 300

ANALOG INPUT FREQUENCY (MHz)

ANALOG INPUT BANDWIDTH

-6dB BELOW FULL-SCALE

-5

-6

-7

-8

AMPLITUDE (dB)

-9

SMALL-SIGNAL BANDWIDTH = 2.4GHz

-10

ANALOG INPUT FREQUENCY (MHz)

500 1500 2500

MAX106 toc26

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

DIFFERENTIAL NONLINEARITY

vs. OUTPUT

(LOW-FREQUENCY SERVO-LOOP DATA)

MAX106 toc27

OUTPUT CODE

DNL (LSB)

0 32 64 96 128 160 192 224 256

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

_______________________________________________________________________________________ 9

Pin Description

DREADY

200mV/div

DATA

200mV/div

DREADY RISE/FALL TIME,

DATA RISE/FALL TIME

MAX106 toc28

500ps/div

1.0

1.1

1.2

1.3

1.4

1.5

0 1000500 1500 2000 2500

VOLTAGE STANDING-WAVE RATIO

vs. ANALOG INPUT FREQUENCY

MAX106 toc29

ANALOG INPUT FREQUENCY (MHz)

VSWR

Test Point. Do not connect.

TESTPOINT

(T.P.)

A10, E17, F2, P3, R17, R18

Digital GroundGNDD

A11, B11, B16, B17, C11, C16, U9, U17,

V9, V17, V18, W9

PECL Supply Voltage, +3V to +5VVCCO

A12–A19, B19, C19, D19, E19, F19, G19,
H19, J19, K19, L19, M19, N19, P19, T19,

U19, V19, W10–W19

Analog Supply Voltage, +5V. Supplies analog comparator array.VCCAA9, B9, C9, U7, V7, W7

Analog Ground—For comparator array.GNDAA8, B8, C8, U6, V6, W6

CONTACT

Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.

VCCIA5, B5, C5, H2, H3, M2, M3, U5, V5, W5

Analog Ground—for T/H amplifier, clock distribution, bandgap refer­ence, and reference amplifier.

GNDI

A1–A4, A6, A7, B1, B2, C1, C2, D1, D2,

D3, G1, H1, J2, J3, K1, K2, K3, L2, L3,

M1, N1, T2, T3, U1, V1, V2, W1–W4

FUNCTIONNAME

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other­wise noted.)

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

10 ______________________________________________________________________________________

Pin Description (continued)

CONTACT

Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.

V

EE

B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,

U2, U3, U4, V3, V4

FUNCTIONNAME

Reference Ground. Must be connected to GNDI.

GNDRB6, B7

Primary Output Data Bit 0 (LSB)P0+B12

Digital Supply Voltage, +5VVCCD

B10, B18, C10, C17, C18, T17, T18, U8,

U18, V8, W8

Primary Output Data Bit 1P1+B14

Reference InputREFINC6

Auxiliary Output Data Bit 1A1+B15

Auxiliary Output Data Bit 0 (LSB)A0+B13

Complementary Primary Output Data Bit 0 (LSB)P0-C12

Complementary Primary Output Data Bit 1P1-C14

Complementary Auxiliary Output Data Bit 0 (LSB)A0-C13

TTL/CMOS Demux Divide-Selection Input
1: Decimation DIV4 mode
0: Demultiplexed DIV2 mode

DIVSELECTD17

Die Temperature Measurement Test Point. See Die Temperature
Measurement section.

ICONSTE1

Tie to VCCO to power the auxiliary port. Tie to GNDD to power
down.

AUXEN2D18

Complementary Auxiliary Output Data Bit 1A1-C15

Reference OutputREFOUTC7

Die Temperature Measurement Test Point. See Die Temperature
Measurement section.

IPTATE2

Offset Adjust InputVOSADJF1

TTL/CMOS Demux Enable Control
1: Enable Demux
0: Disable Demux

DEMUXENE18

Primary Output Data Bit 2P2+F18

Auxiliary Output Data Bit 2A2+G18

Complementary Auxiliary Output Data Bit 2A2-G17

Complementary Primary Output Data Bit 2P2-F17

Complementary Primary Output Data Bit 3P3-H17

Primary Output Data Bit 3P3+H18

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 11

Pin Description (continued)

Differential Input Voltage (-)VIN-J1

Auxiliary Output Data Bit 3A3+J18

Primary Output Data Bit 4P4+L18

Complementary Primary Output Data Bit 4P4-L17

Complementary Auxiliary Output Data Bit 3A3-J17

Auxiliary Output Data Bit 4A4+M18

Primary Output Data Bit 5P5+N18

Complementary Primary Output Data Bit 5P5-N17

CONTACT

Complementary Auxiliary Output Data Bit 5A5-P17

FUNCTIONNAME

This contact must be connected to GNDI.

TESTPOINT

(T.P.)

P2

Complementary Sampling Clock InputCLK-P1

Complementary Auxiliary Output Data Bit 4A4-M17

Auxiliary Output Data Bit 5A5+P18
50Ω Clock Termination ReturnCLKCOMR1, R2, R3

Sampling Clock InputCLK+T1

Complementary PECL Reset OutputRSTOUT-U11

Complementary PECL Demux Reset InputRSTIN-U10

Tie to VCCO to power the auxiliary port. Tie to GNDD to power
down.

AUXEN1R19

Complementary PECL Overrange BitOR-U12

Complementary Primary Output Data Bit 7 (MSB)P7-U14

Complementary Primary Output Data Bit 6P6-U16

Complementary Auxiliary Output Data Bit 6A6-U15

Complementary Auxiliary Output Data Bit 7 (MSB)A7-U13

PECL Reset OutputRSTOUT+V11

PECL Demux Reset InputRSTIN+V10

PECL Overrange BitOR+V12

Primary Output Data Bit 7 (MSB)P7+V14

Primary Output Data Bit 6P6+V16

Auxiliary Output Data Bit 6A6+V15

Auxiliary Output Data Bit 7 (MSB)A7+V13

Complementary Data-Ready ClockDREADY-K17

Differential Input Voltage (+)VIN+L1

Data-Ready ClockDREADY+K18

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

12 ______________________________________________________________________________________

Detailed Description

The MAX106 is an 8-bit, 600Msps flash ADC with on­chip T/H amplifier and differential PECL-compatible
outputs. The ADC (Figure 1) employs a fully differential
8-bit quantizer and a unique encoding scheme to limit
metastable states to typically one error per 1027clock
cycles, with no error exceeding 1LSB max.

An integrated 8:16 output demultiplexer simplifies inter­facing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
has internal reset capability that allows multiple
MAX106s to be time-interleaved to achieve higher
effective sampling rates.

When clocked at 600Msps, the MAX106 provides a typ­ical effective number of bits (ENOB) of 7.6 bits at an
analog input frequency of 300MHz. The analog input of
the MAX106 is designed for differential or single-ended
use with a ±250mV full-scale input range. In addition,
this fast ADC features an on-board +2.5V precision
bandgap reference. If desired, an external reference
can also be used.

Figure 1. Simplified Functional Diagram

REF

REF

OUT

BANDGAP

REFERENCE

IN

+2.5V

REFERENCE
AMPLIFIER

VOSADJ

50Ω

VIN+

VIN-

50Ω

GNDI

CLK+

50Ω

CLKCOM

50Ω

CLK-

RSTIN+

RSTIN-

GNDI

T/H
CLOCK
DRIVER

RESET INPUT
DUAL LATCH

GNDR

BIAS CURRENTS

T/H AMPLIFIER

ADC
CLOCK
DRIVER

LOGIC
CLOCK
DRIVER

RESET

PIPELINE

8-BIT

FLASH ADC

DELAYED

RESET

MAX106

DEMUXEN

2

16

DEMUX
CLOCK

GENERATOR

DIVSELECT

DEMUX
CLOCK
DRIVER

OVERRANGE

BIT

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

DATA

READY CLOCK

DEMUX

RESET OUTPUT

DIFFERENTIAL

PECL OUTPUTS

OR

2

A0–A7

16

P0–P7

16

DREADY

2

RSTOUT

2

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 13

Principle of Operation

The MAX106’s flash or parallel architecture provides
the fastest multibit conversion of all common integrated
ADC designs. The key to this high-speed flash archi­tecture is the use of an innovative, high-performance
comparator design. The flash converter and down­stream logic translate the comparator outputs into a
parallel 8-bit output code and pass this binary code on
to the optional 8:16 demultiplexer, where primary and
auxiliary ports output PECL-compatible data at up to
300Msps per port (depending on how the demultiplex­er section is set on the MAX106). The ideal transfer
function appears in Figure 2.

On-Chip Track/Hold Amplifier

As with all ADCs, if the input waveform is changing
rapidly during conversion, ENOB and signal-to-noise
ratio (SNR) specifications will degrade. The MAX106’s
on-chip, wide-bandwidth (2.2GHz) T/H amplifier reduces
this effect and increases the ENOB performance signifi­cantly, allowing precise capture of fast analog data at
high conversion rates.

The T/H amplifier buffers the input signal and allows a
full-scale signal input range of ±250mV. The T/H ampli­fier’s differential 50Ω input termination simplifies inter­facing to the MAX106 with controlled impedance lines.
Figure 3 shows a simplified diagram of the T/H amplifier
stage internal to the MAX106.

Aperture width, delay, and jitter (or uncertainty) are
parameters that affect the dynamic performance of
high-speed converters. Aperture jitter, in particular,
directly influences SNR and limits the maximum slew
rate (dV/dt) that can be digitized without a significant
contribution of errors. The MAX106’s innovative T/H
amplifier design typically limits aperture jitter to less
than 0.5ps.

Aperture Width

Aperture width (tAW) is the time the T/H circuit requires
(Figure 4) to disconnect the hold capacitor from the
input circuit (for instance to turn off the sampling bridge
and put the T/H unit in hold mode).

Aperture Jitter

Aperture jitter (t

AJ

) is the sample-to-sample variation

(Figure 4) in the time between the samples.

Aperture Delay

Aperture delay (t

AD

) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).

Figure 3. Internal Structure of the 2.2GHz T/H Amplifier

Figure 4. T/H Aperture Timing

Figure 2. Transfer Function

OVERRANGE + 255

255
254

129
128
127
126

DIGITAL OUTPUT

3
2
1
0

ANALOG INPUT

(-FS + 1LSB)

0

+FS

(+FS - 1LSB)

ALL INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).

VIN+

VIN-

GNDI

CLK+

CLK-

CLKCOM

50Ω50Ω

50Ω50Ω

INPUT

AMPLIFIER

CLOCK

SPLITTER

SAMPLING

BRIDGE

AMPLIFIER

C

GNDI

BUFFER

TO
COMPARATORS

HOLD

TO
COMPARATORS

CLK

CLK

ANALOG

INPUT

SAMPLED

DATA (T/H)

t

AD

t

AW

t

AJ

TRACK TRACK

T/H

APERTURE DELAY (t
APERTURE WIDTH (t
APERTURE JITTER (t

HOLD

)

AD

)

AW

)

AJ

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

14 ______________________________________________________________________________________

Internal Reference

The MAX106 features an on-chip +2.5V precision
bandgap reference that can be used by connecting
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally tied to GNDR. GNDR must
be connected to GNDI on the user’s application board.
REFOUT can source up to 2.5mA to supply external
devices if required.

An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer­ence supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT must not be simultaneously
connected at any time, to avoid conflicts between the
two references. REFIN has a typical input resistance of
5kΩ and accepts input voltages of +2.5V ±200mV.
Using the MAX106’s internal reference is recommend­ed for best performance.

Digital Outputs

The MAX106 provides data in offset binary format to dif­ferential PECL outputs. A simplified circuit schematic of
the PECL output cell is shown in Figure 5. All PECL out­puts are powered from VCCO, which may be operated
from any voltage between +3.0V to VCCD for flexible
interfacing with either +3.3V or +5V systems. The nomi­nal VCCO supply voltage is +3.3V.

All PECL outputs on the MAX106 are open-emitter
types and must be terminated at the far end of each
transmission line with 50Ω to VCCO - 2V. Table 1 lists all
MAX106 PECL outputs and their functions.

Demultiplexer Operation

The MAX106 features an internal data demultiplexer,
which provides for three different modes of operation
(see the following sections on Demultiplexed DIV2

Mode, Non-Demultiplexed DIV1 Mode, and Decimation
DIV4 Mode) controlled by two TTL/CMOS-compatible

inputs: DEMUXEN and DIVSELECT.

DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSE­LECT low selects demultiplexed DIV2 mode, and DIV­SELECT high selects decimation DIV4 mode (Table 2).

Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true value; a “-”
denotes the complementary outputs.

A0+ to A7+,

A0- to A7-

Overrange True and Complementary OutputsOR+, OR-

Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.

DREADY+, DREADY-

Reset Output True and Complementary OutputsRSTOUT+, RSTOUT-

PECL OUTPUT SIGNALS

Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true value; a “-”
denotes the complementary outputs.

P0+ to P7+,

P0- to P7-

FUNCTION

Figure 5. Simplified PECL Output Structure

Table 1. PECL Output Functions

O

V

CC

500Ω 500Ω

A_+/P_+

DIFF.
PAIR

GNDD

1.8mA

GNDD GNDD

A_-/P_-

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 15

Non-Demultiplexed DIV1 Mode

The MAX106 may be operated at up to the full sam­pling rate (600Msps) in non-demultiplexed DIV1 mode
(Table 2). In this mode, the internal demultiplexer is dis­abled and sampled data is presented to the primary
port only, with the data repeated at the auxiliary port,
but delayed by one clock cycle (Figure 6). Since the
auxiliary output port contains the same data stream as
the primary output port, the auxiliary port can be shut
down to save power by connecting AUXEN1 and
AUXEN2 to digital ground (GNDD). This powers down
the internal bias cells and causes both outputs (true
and complementary) of the auxiliary port to pull up to a
logic-high level. To save additional power, the external
50Ω termination resistors connected to the PECL termi-

nation power supply (V

CC

O - 2V) may be removed from

all auxiliary output ports.

Demultiplexed DIV2 Mode

The MAX106 features an internally selectable DIV2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two con­secutive samples appearing in the primary and auxil­iary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to V

CC

O to power up the auxiliary port

PECL output drives.

Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram

Figure 7. Demuxed DIV2-Mode Timing Diagram

CLK

DREADY+

DREADY

DREADY-

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

ADC SAMPLE NUMBER

CLK-

n n+1 n+2 n+3 n+4 n+5

CLK+

ADC SAMPLES ON THE RISING EDGE OF CLK+

n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13

n n+1 n+2 n+3 n+4

n+1 n+2 n+3 n+4

n+5

NOTE: THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA.
GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TO SAVE POWER.

ADC SAMPLE NUMBER

CLK-

n n+1 n+2 n+3 n+4 n+5

CLK

CLK+

DREADY+

DREADY

DREADY-

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

NOTE: THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES.
BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.

ADC SAMPLES ON THE RISING EDGE OF CLK+

n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13

n n+2 n+4

n+1n-1 n+3

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

16 ______________________________________________________________________________________

Decimation DIV4 Mode

The MAX106 also offers a special decimated, demulti­plexed output (Figure 8) that discards every other input
sample and outputs data at one-quarter the input sam­pling rate for system debugging at slower output data
rates. With an input clock of 600MHz, the effective out­put data rate will be reduced to 150MHz per output port
in the DIV4 mode (Table 2). Since every other sample is
discarded, the effective sampling rate is 300Msps.

Overrange Operation

A single differential PECL overrange output bit (OR+,
OR-) is provided for both primary and auxiliary demulti­plexed outputs. The operation of the overrange bit
depends on the status of the internal demultiplexer. In
demultiplexed DIV2 mode and decimation DIV4 mode,

the OR bit will flag an overrange condition if either the
primary or auxiliary port contains an overranged sam­ple (Table 2). In non-demultiplexed DIV1 mode, the OR
port will flag an overrange condition only when the pri­mary output port contains an overranged sample.

Applications Information

Single-Ended Analog Inputs

The MAX106 T/H amplifier is designed to work at full
speed for both single-ended and differential analog
inputs (Figure 9). Inputs VIN+ and VIN- feature on-chip,
laser-trimmed 50Ω termination resistors to provide
excellent voltage standing-wave ratio (VSWR) perfor­mance.

Figure 8. Decimation DIV4-Mode Timing Diagram

Table 2. Demultiplexer Operation

Flags overrange data appearing in the pri­mary port only.

Low

High

DEMUXEN OVERRANGE-BIT OPERATION

X

Low

DIVSELECT

DIV1

600Msps/port

DIV2

300Msps/port

DEMUX MODE

High

Flags overrange data appearing in either
the primary or auxiliary port.

High

DIV4

150Msps/port

X = Don’t care

CLK

DREADY+

DREADY

DREADY-

AUXILIARY

DATA PORT

ADC SAMPLE NUMBER

CLK-

n n+1 n+2 n+3 n+4 n+5

CLK+

ADC SAMPLES ON THE RISING EDGE OF CLK+

n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13

n-2 n+2

PRIMARY

DATA PORT

NOTE: THE LATENCY TO THE PRIMARY PORT REMAINS 7.5 CLOCK CYCLES, WHILE THE LATENCY OF THE AUXILIARY PORT INCREASES TO 9.5 CLOCK CYCLES.
THIS EFFECTIVELY DISCARDS EVERY OTHER SAMPLE AND REDUCES THE OUTPUT DATA RATE TO 1/4 THE SAMPLE CLOCK RATE.

n

n+4

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 17

In a typical single-ended configuration, the analog
input signal (Figure 10a) enters the T/H amplifier stage
at the in-phase input (VIN+), while the inverted phase
input (VIN-) is reverse-terminated to GNDI with an
external 50Ω resistor. Single-ended operation allows for
an input amplitude of ±250mV. Table 3 shows a selec­tion of input voltages and their corresponding output
codes for single-ended operation.

Differential Analog Inputs

To obtain a full-scale digital output with differential input
drive (Figure 10b), 250mVp-p must be applied between
VIN+ and VIN- (VIN+ = +125mV and VIN- = -125mV).
Midscale digital output codes (01111111 or 10000000)
occur when there is no voltage difference between
VIN+ and VIN-. For a zero-scale digital output code, the

in-phase input (VIN+) must see -125mV and the invert­ed input (VIN-) must see +125mV. A differential input
drive is recommended for best performance. Table 4
represents a selection of differential input voltages and
their corresponding output codes.

Figure 9. Simplified Analog Input Structure (Single-Ended/
Differential)

Figure 10a. Single-Ended Analog Input Signals

Figure 10b. Differential Analog Input Signals

Table 3. Ideal Input Voltage and Output Code Results for Single-Ended Operation

0V 11111111 (full scale)+250mV

VIN-

1

OVERRANGE BITVIN+ OUTPUT CODE

0V 11111111+250mV - 1LSB 0

0V

0V

01111111

toggles

10000000

0V 0

00000001 -250mV + 1LSB 0

0V 00000000 (zero scale)-250mV 0

ANALOG INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS SIMPLIFIED DRAWING).

+2.8V

+250mV

V

IN+

VIN+

50Ω

GNDI

50Ω

VIN-

V

EE

500mVp-p

FS ANALOG

INPUT RANGE

-250mV

+125mV

±250mV

FS ANALOG

INPUT RANGE

-125mV

500mV

250mV

= ±250mV

V

IN

V

IN-

V

IN+

-250mV

0V

t

V

IN-

0V

t

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

18 ______________________________________________________________________________________

Offset Adjust

The MAX106 provides an analog input (VOSADJ) to com­pensate for system offsets. The offset adjust input is a
self-biased voltage divider from the internal +2.5V preci­sion reference. The nominal open-circuit voltage is one­half the reference voltage. With an input resistance of
typically 25kΩ, this pin may be driven by an external
10kΩ potentiometer (Figure 11) connected between
REFOUT and GNDI to correct for offset errors. This con­trol provides a typical ±5.5LSB offset adjustment range.

Clock Operation

The MAX106 clock inputs are designed for either sin­gle-ended or differential operation (Figure 12) with flexi­ble input drive requirements. Each clock input is
terminated with an on-chip, laser-trimmed 50Ω resistor
to CLKCOM (clock-termination return). The CLKCOM
termination voltage can be connected anywhere
between ground and -2V for compatibility with standard
ECL drive levels.

The clock inputs are internally buffered with a preampli­fier to ensure proper operation of the data converter,
even with small-amplitude sine-wave sources. The
MAX106 was designed for single-ended, low-phase­noise sine-wave clock signals with as little as 100mV
amplitude (-10dBm). This eliminates the need for an
external ECL clock buffer and its added jitter.

Single-Ended Clock Inputs (Sine-Wave Drive)

Excellent performance is obtained by AC- or DC-cou­pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 5). For proper DC bal­ance, the undriven clock input should be externally
50Ω reverse-terminated to GNDI.

Table 4. Ideal Input Voltage and Output Code Results for Differential Operation

-125mV

-125mV + 0.5LSB

11111111 (full scale)+125mV

VIN-

1

11111111+125mV - 0.5LSB 0

OVERRANGE BIT

0V

+125mV - 0.5LSB

01111111

toggles

10000000

0V 0

00000001-125mV + 0.5LSB 0

+125mV 00000000 (zero scale)-125mV 0

VIN+ OUTPUT CODE

Figure 11. Offset Adjust with External 10kΩ Potentiometer

Figure 12. Simplified Clock Input Structure (Single-Ended/
Differential)

REFOUT

10k

POT

GNDI

CLK+

50Ω

CLKCOM

50Ω

CLK-

MAX106

VOSADJ

GNDI

+0.8V

CLK INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).

V

EE

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 19

The dynamic performance of the data converter is
essentially unaffected by clock-drive power levels from

-10dBm (100mV clock signal amplitude) to +10dBm
(1V clock signal amplitude). The MAX106 dynamic per­formance specifications are determined by a single­ended clock drive of +4dBm (500mV clock signal
amplitude). To avoid saturation of the input amplifier
stage, limit the clock power level to a maximum of
+10dBm.

Differential Clock Inputs (Sine-Wave Drive)

The advantages of differential clock drive (Figure 13b,
Table 5) can be obtained by using an appropriate
balun or transformer to convert single-ended sine-wave
sources into differential drives. The precision on-chip
laser-trimmed 50Ω clock-termination resistors ensure
excellent amplitude matching. See Single-Ended Clock

Inputs (Sine-Wave Drive) for proper input amplitude
requirements.

Single-Ended Clock Inputs (ECL Drive)

Configure the MAX106 for single-ended ECL clock
drive by connecting the clock inputs as shown in Figure
13c (Table 5). A well-bypassed VBBsupply (-1.3V) is
essential to avoid coupling noise into the undriven
clock input, which would degrade the dynamic perfor­mance.

Differential Clock Inputs (ECL Drive)

The MAX106 may be driven from a standard differential
(Figure 13d, Table 5) ECL clock source by setting the
clock termination voltage at CLKCOM to -2V. Bypass
the clock-termination return (CLKCOM) as close to the
ADC as possible with a 0.01µF capacitor connected to
GNDI.

Figure 13a. Single-Ended Clock Input Signals

Figure 13c. Single-Ended ECL Clock Drive

Figure 13b. Differential Clock Input Signals

Figure 13d. Differential ECL Clock Drive

+0.5V

CLK+

CLK- = 0V

CLK+

+0.5V

CLK-

-0.5V

NOTE: CLKCOM = 0V

-0.8V

-1.8V

NOTE: CLKCOM = -2V

CLK+

CLK- = -1.3V

t

t

-0.5V

NOTE: CLKCOM = 0V

-0.8V

-1.8V

NOTE: CLKCOM = -2V

t

CLK+

CLK-

t

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

20 ______________________________________________________________________________________

AC-Coupling Clock Inputs

The clock inputs CLK+ and CLK- can also be driven
with positive referenced ECL (PECL) logic levels if the
clock inputs are AC-coupled. Under this condition, con­nect CLKCOM to GNDI. Single-ended ECL/PECL/sine­wave drive is also possible if the undriven clock input is
reverse-terminated to GNDI through a 50Ω resistor in
series with a capacitor whose value is identical to that
used to couple the driven input.

Demux Reset Operation

The MAX106 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one­half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX106s and/or synchroniz­ing external demultiplexers. The simplified block dia­gram of Figure 1 shows that the demux reset signal path
consists of four main circuit blocks. From input to out­put, they are the reset input dual latch, the reset
pipeline, the demux clock generator, and the reset out­put. The signals associated with the demux reset opera­tion and the control of this section are listed in Table 6.

Reset Input Dual Latch

The reset input dual-latch circuit block accepts differ­ential PECL reset inputs referenced to the same V

CC

O
power supply that powers the MAX106 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50kΩ
resistors and a 20µA current source. This combination
creates a -1V difference between RSTIN+ and RSTIN­to disable the internal reset circuitry. When driven with
PECL logic levels terminated with 50Ω to (VCCO - 2V),
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.

To properly latch the reset input data, setup (tSU) and
data-hold times (tHD) must be met with respect to the
rising edge of the sample clock. The timing diagram of
Figure 15 shows the timing relationship of the reset
input and sampling clock.

Table 5. DC-Coupled Clock Drive Options

-10dBm to +4dBm Figure 13aSingle-Ended Sine Wave

CLK+

GNDI

CLKCOMCLOCK DRIVE REFERENCE

External 50Ω to GNDI

CLK-

-10dBm to +4dBm -10dBm to +4dBm Figure 13bDifferential Sine Wave GNDI

ECL Drive -1.3V Figure 13cSingle-Ended ECL -2V

ECL Drive

ECL Drive

Figure 13dDifferential ECL -2V

Figure 14. Simplified Reset Input Structure

Figure 15. Reset Input Timing Definitions

50k50k

RSTIN+

RSTIN-

20µA

GNDD

RESET INPUTS ARE ESD PROTECTED
(NOT SHOWN ON THIS SIMPLIFIED DRAWING).

RSTIN+

50% 50%

RSTIN-

t

SU

50%

O

V

CC

t

HD

CLK+

CLK-

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 21

Reset Pipeline

The next section in the reset signal path is the reset
pipeline. This block adds clock latency cycles to the
reset signal to match the latency of the converted ana­log data through the ADC. In this way, when reset data
arrives at the RSTOUT+/RSTOUT- PECL output it will be
time-aligned with the analog data present in the prima­ry and auxiliary ports at the time the reset input was
deasserted at RSTIN+/RSTIN-.

Demux Clock Generator

The demux clock generator creates the DIV1, DIV2, or
DIV4 clocks required for the different modes of demux
and non-demux operation. The TTL/CMOS control
inputs DEMUXEN and DIVSELECT control the demuxed
mode selection, as described in Table 2. The timing
diagrams in Figures 16 and 17 show the output timing
and data alignment in DIV1, DIV2, and DIV4 modes,
respectively.

The phase relationship between the sampling clock at
the CLK+/CLK- inputs and the data-ready clock at the
DREADY+/DREADY- outputs will be random at device
power-up. As with all divide-by-two circuits, two possi­ble phase relationships exist between these clocks.
The difference between the phases is the inversion of
the DIV2/DREADY clock. The timing diagram in Figure
16 shows this relationship.

Reset all MAX106 devices to a known DREADY phase
after initial power-up for applications such as interleav­ing, where two or more MAX106 devices are used to
achieve higher effective sampling rates. This synchro­nization is necessary to set the order of output samples
between the devices. Resetting the converters accom­plishes this synchronization. The reset signal is used to
force the internal counter in the demux clock-generator
block to a known phase state.

Table 6. Demux Operating and Reset Control Signal

Figure 16. CLK and DREADY Timing in Demuxed DIV2 Mode
Showing Two Possible DREADY Phases

Figure 17. Output Timing for All Modes (DIV1, DIV2, DIV4)

Sampling clock inputs

Master ADC Timing Signal. The ADC samples on the rising edge of
CLK+.

CLK+, CLK-

TYPE

Differential PECL outputs

Data-Ready PECL Output. Output data changes on the rising edge of
DREADY+.

DREADY+, DREADY-

Differential PECL inputs Demux Reset Input Signals. Resets the internal demux when asserted.RSTIN+, RSTIN-

Differential PECL outputs Reset Outputs—for resetting additional external demux devices.RSTOUT+, RSTOUT-

SIGNAL NAME FUNCTION

CLK+

50%

t

DREADY-

DREADY+

PD1

"PHASE 1"

t

FDREADY

DREADY +

80% 80%

"PHASE 2"

DREADY -

CLK-

DREADY +

50%

DREADY -

20% 20%

t

RDREADY

t

PWH

CLK+

CLK-

AUXILIARY PORT DATA

PRIMARY PORT DATA

t

PWL

t

PD1

t

PD2

DREADY +

DREADY -

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

22 ______________________________________________________________________________________

Reset Output

Finally, the reset signal is presented in differential PECL
format to the last block of the reset signal path.
RSTOUT+/RSTOUT- output the time-aligned reset sig­nal used for resetting additional external demuxes in
applications where further reduction in the output data
rate is desired. Many demux devices require their reset
signal to be asserted for several clock cycles while they
are clocked. To accomplish this, the MAX106 DREADY
clock will continue to toggle while RSTOUT is asserted.

When a single MAX106 device is used, no synchroniz­ing reset is required since the order of the samples in
the output ports is unchanged regardless of the phase
of the DREADY clock. In DIV2 mode, the data in the
auxiliary port is delayed by 8.5 clock cycles while the
data in the primary port is delayed by 7.5 clock cycles.
The older data is always in the auxiliary port, regardless
of the phase of the DREADY clock.

The reset output signal, RSTOUT, is delayed by one
fewer clock cycle (6.5 clock cycles) than the primary
port. The reduced latency of RSTOUT serves to mark

the start of synchronized data in the primary and auxil­iary ports. When the RSTOUT signal returns to a zero,
the DREADY clock phase is reset.

Since there are two possible phases of the DREADY
clock with respect to the input clock, there are two pos­sible timing diagrams to consider. The first timing dia­gram (Figure 18) shows the RSTOUT timing and data
alignment of the auxiliary and primary output ports
when the DREADY clock phase is already reset. For
this example, the RSTIN pulse is two clock cycles long.
Under this condition, the DREADY clock continues
uninterrupted, as does the data stream in the auxiliary
and primary ports.

The second timing diagram (Figure 19) shows the
results when the DREADY phase is opposite from the
reset phase. In this case, the DREADY clock “swallows”
a clock cycle of the sample clock, resynchronizing to
the reset phase. Note that the data stream in the auxil­iary and primary ports has reversed. Before reset was

Figure 18. Reset Output Timing in Demuxed DIV2 Mode (DREADY Aligned)

CLK

RESET
INPUT

DREADY

ADC SAMPLE NUMBER

n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13

CLK-

CLK+

RSTIN-

RSTIN+

DREADY-

DREADY+

t

SU

ADC SAMPLES ON THE RISING EDGE OF CLK+

t

HD

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

RESET OUT
DATA PORT

NOTE: THE LATENCY TO THE RESET OUTPUT IS 6.5 CLOCK CYCLES. THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND
THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. ALL DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.

RSTOUT-

RSTOUT+

n n+2 n+4

n+1n-1 n+3

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 23

asserted, the auxiliary port contained “even” samples
while the primary port contained “odd” samples. After
RSTOUT is deasserted (which marks the start of the
DREADY clock’s reset phase), note that the order of the
samples in the ports has been reversed. The auxiliary
port also contains an out-of-sequence sample. This is a
consequence of the “swallowed” clock cycle that was
needed to resynchronize DREADY to the reset phase.
Also note that the older sample data is always in the aux­iliary port, regardless of the DREADY phase.

These examples show the combinations that result with
a reset input signal of two clock cycles. It is also possi­ble to successfully reset the internal MAX106 demux
with a reset pulse only one clock cycle long, proving
the setup-time and hold-time requirements are met with
respect to the sample clock. However, this is not rec­ommended when additional external demuxes are
used.

Note that many external demuxes require their reset
signals to be asserted while they are clocked, and may
require more than one clock cycle of reset. More impor­tantly, if the phase of the DREADY clock is such that a
clock pulse will be “swallowed” to resynchronize, then

no reset output will occur at all. In effect, the RSTOUT
signal will be “swallowed” along with the clock pulse.
The best method to ensure complete system reset is to
assert RSTIN for the appropriate number of DREADY
clock cycles required to complete reset of the external
demuxes.

Die Temperature Measurement

For applications that require monitoring of the die tem­perature, it is possible to determine the die temperature
of the MAX106 under normal operating conditions by
observing the currents I

CONST

and I

PTAT

, at contacts

ICONST and IPTAT. I

CONST

and I

PTAT

are two 100µA
(nominal) currents that are designed to be equal at
+27°C. These currents are derived from the MAX106’s
internal precision +2.5V bandgap reference. I

CONST

is

designed to be temperature independent, while I

PTAT

is
directly proportional to the absolute temperature. These
currents are derived from pnp current sources refer­enced from VCCI and driven into two series diodes con­nected to GNDI. The contacts ICONST and IPTAT may
be left open because internal catch diodes prevent sat­uration of the current sources. The simplest method of

Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)

ADC SAMPLE NUMBER

n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13

CLK-

CLK

CLK+

RESET
INPUT

DREADY

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

RESET OUT

DATA PORT

NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.
THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.

t

SU t

RSTIN-

RSTIN+

DREADY+

DREADY-

RSTOUT-

RSTOUT+

ADC SAMPLES ON THE RISING EDGE OF CLK+

HD

n-2

n-1 n+1

CLOCK PULSE “SWALLOWED”

OUT-OF-SEQUENCE SAMPLE

n

n+2

n+4

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

24 ______________________________________________________________________________________

determining the die temperature is to measure each
current with an ammeter (which shuts off the internal
catch diodes) referenced to GNDI. The die temperature
in °C is then calculated by the expression:

Another method of determining the die temperature
uses the operational amplifier circuit shown in Figure

20. The circuit produces a voltage that is proportional
to the die temperature. A possible application for this
signal is speed control for a cooling fan to maintain
constant MAX106 die temperature. The circuit operates
by converting the I

CONST

and I

PTAT

currents to volt-

ages V

CONST

and V

PTAT

, with appropriate scaling to
account for their equal values at +27°C. This voltage
difference is then amplified by two amplifiers in an
instrumentation-amplifier configuration with adjustable
gain. The nominal value of the circuit gain is 4.5092V/V.
The gain of the instrumentation amplifier is given by the
expression:

To calibrate the circuit, first connect pins 2-3 on JU1 to
zero the input of the PTAT path. With the MAX106 pow­ered up, adjust potentiometer R3 until the voltage at the
V

TEMP

output is -2.728V. Connecting pins 1-2 on JU1
restores normal operation to the circuit after the calibra­tion is complete. The voltage at the V

TEMP

node will
then be proportional to the actual MAX106 die tempera­ture according to the equation:

The overall accuracy of the die temperature measure­ment using the operational-amplifier scaling circuitry is
limited mainly by the accuracy and matching of the
resistors in the circuit.

Thermal Management

Depending on the application environment for the
ESBGA-packaged MAX106, the customer may have to
apply an external heatsink to the package after board
assembly. Existing open-tooled heatsinks are available
from standard heatsink suppliers (listed in Heatsink
Manufacturers). The heatsinks are available with preap­plied adhesive for easy package mounting.

T ( C) 100 V

DIE TEMP

°= ⋅

A

V

VV

A

R
R

R

R

V

TEMP

CONST PTAT

V

=

−

=+ +1

1
2

2

1
3

T 300

I

I

273

DIE

PTAT

CONST

=











−

Figure 20. Die Temperature-Acquisition Circuit with the MAX479

3.32k

6.65k

R1

I

PTAT

12.1k

1/4 MAX479

12.1k

1/4 MAX479

6.05k

6.65k

I

CONST

2

JU1

1

3

7.5k

V

PTAT

V

CONST

R2
15k

1/4 MAX479

5k

10-TURN

R2

15k

R1

7.5k

1/4 MAX479

V

TEMP

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 25

Thermal Performance

The MAX106 has been modeled to determine the thermal
resistance from junction to ambient. Table 7 lists the
ADC’s thermal performance:

Ambient Temperature: TA= +70°C
Heatsink Dimensions: 25mm x 25mm x 10mm
PC Board Size and Layout: 4in. x 4in.

2 Signal Layers
2 Power Layers

Heatsink Manufacturers

Aavid Engineering and IERC provide open-tooled, low­profile heatsinks, fitting the 25mm x 25mm ESBGA
package.

Aavid Engineering, Inc.
Phone: [phone]
Heatsink Catalog No.: 335224B00032
Heatsink Dimensions: 25mm x 25mm x 10mm

International Electronic Research Corporation (IERC)
Phone: [phone]
Heatsink Catalog No.: BDN09-3CB/A01
Heatsink Dimensions: 23.1mm x 23.1mm x 9mm

Bypassing/Layout/Power Supply

Grounding and power-supply decoupling strongly influ­ence the MAX106’s performance. At 600MHz clock fre­quency and 8-bit resolution, unwanted digital crosstalk
may couple through the input, reference, power-supply,
and ground connections and adversely influence the
dynamic performance of the ADC. Therefore, closely
follow the grounding and power-supply decoupling
guidelines (Figure 22).

Maxim strongly recommends using a multilayer printed
circuit board (PCB) with separate ground and power­supply planes. Since the MAX106 has separate analog

and digital ground connections (GNDA, GNDI, GNDR,
and GNDD, respectively), the PCB should feature sep­arate analog and digital ground sections connected at
only one point (star ground at the power supply). Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane. Keep digital signals far away from the sensitive
analog inputs, reference inputs, and clock inputs. High­speed signals, including clocks, analog inputs, and
digital outputs, should be routed on 50Ω microstrip
lines such as those employed on the MAX106 evalua­tion kit.

The MAX106 has separate analog and digital power­supply inputs: V

EE

(-5V analog and substrate supply)
and VCCI (+5V) to power the T/H amplifier, clock distri­bution, bandgap reference, and reference amplifier;
V

CC

A (+5V) to supply the ADC’s comparator array;
VCCO (+3V to VCCD) to establish power for all PECL­based circuit sections; and VCCD (+5V) to supply all
logic circuits of the data converter.

The MAX106 VEEsupply contacts must not be left
open while the part is being powered up. To avoid this
condition, add a high-speed Schottky diode (such as a
Motorola 1N5817) between VEEand GNDI. This diode
prevents the device substrate from forward biasing,
which could cause latchup.

Table 7. Thermal Performance for
MAX106 With or Without Heatsink

16.50 12.5

14.3 9.4200

13 8.3400

12.5 7.4800

Figure 21. MAX106 Thermal Performance

MAX106 θJA(°C/W)

WITHOUT

HEATSINK

WITH HEATSINK

AIRFLOW

(linear ft/min)

THERMAL RESISTANCE vs. AIRFLOW

18

16

14

12

(°C/W)

JA

θ

10

8

6

0 200100 300 400 500 600 700 800

WITHOUT HEATSINK

WITH HEATSINK

AIRFLOW (linear ft./min.)

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

26 ______________________________________________________________________________________

All supplies should be decoupled with large tantalum or
electrolytic capacitors at the point they enter the PCB.
For best performance, bypass all power supplies to the
appropriate ground with a 10µF tantalum capacitor to
filter power-supply noise, in parallel with a 0.01µF
capacitor and a high-quality 47pF ceramic chip capaci­tor located very close to the MAX106 device, to filter
very high-frequency noise.

Static Parameter Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX106 are mea­sured using the best-straight-line fit method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.

Figure 22. MAX106 Bypassing and Grounding

O

V

CC

10nF 10nF 47pF 47pF 47pF 47pF

GNDD

V

GNDI

10µF

I

CC

10µF 10nF 10nF 47pF 47pF 47pF 47pF

NOTE:

LOCATE ALL 47pF CAPACITORS AS CLOSE
AS POSSIBLE TO THE MAX106 DEVICE.

V

EE

A

V

CC

1N5817

GNDI

GNDA

V

GNDD

10µF 10nF 10nF 47pF 47pF

D

CC

10µF 10nF 10nF 47pF 47pF 47pF 47pF

10µF

10nF 10nF 47pF 47pF 47pF 47pF

VCCA = +4.75V TO +5.25V
VCCD = +4.75V TO +5.25V
VCCI = +4.75V TO +5.25V
VCCO = +3.0V TO VCCD
VEE = -4.75V TO -5.25V

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 27

Bit Error Rates (BERs)

Errors resulting from metastable states may occur when
the analog input voltage (at the time the sample is
taken) falls close to the decision point of any one of the
input comparators. Here, the magnitude of the error
depends on the location of the comparator in the com­parator network. If it is the comparator for the MSB, the
error will reach full scale. The MAX106’s unique encod­ing scheme solves this problem by virtually eliminating
these errors.

Dynamic Parameter Definitions

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum (SNR) is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):

SNR (max) = (6.02 · N + 1.76) dB

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har­monics, and the DC offset.

Effective Number of Bits

ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from a curve fit referenced to the theoreti­cal full-scale range.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is computed
from the ENOB as follows:

SINAD = (6.02 · ENOB) + 1.76

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:

where V

1

is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio,
expressed in decibels, of the RMS amplitude of the fun­damental (maximum signal component) to the RMS
value of the next-largest spurious component, exclud­ing DC offset.

Intermodulation Distortion

The two-tone intermodulation distortion (IMD) is the
ratio, expressed in decibels, of either input tone to the
worst 3rd-order (or higher) intermodulation products.
The input tone levels are at -7dB full scale.

THD 20 log V V V V / V

2232425

2

1

=+++

















⋅

Chip Information

TRANSISTOR COUNT: 20,486

SUBSTRATE CONNECTED TO V

EE

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

28 ______________________________________________________________________________________

Typical Operating Circuit

DIFFERENTIAL

ANALOG

500mVp-p FS

SAMPLE

CLOCK

600MHz

+4dBm

INPUT

+5V

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

50Ω

GNDI

GNDI

-5V ANALOG

V

DIVSELECT

DEMUXEN

VOSADJ

VIN+

VIN-

CLK+

CLK-

CLKCOM

+5V ANALOG

EEVCC

+5V DIGITAL

AVCCIVCCDV

MAX106

+3.3V DIGITAL

OAUXEN1 AUXEN2

CC

PRIMARY

OUTPUTS

AUXILARY

OUTPUTS

PECL

PECL

OR±

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Z0 = 50Ω

V

P7±

P6±

P5±

P4±

P3±

P2±

P1±

P0±

A7±

A6±

A5±

A4±

A3±

A2±

CC

50Ω

O - 2V

ALL OUTPUTS
MUST BE TERMINATED
LIKE THIS.

TO MEMORY OR DIGITAL SIGNAL PROCESSOR

2

A1±

2

A0±

RSTIN+

RSTIN-

GNDA

GNDR GNDI GNDD REFOUT REFIN

DREADY±

RSTOUT±

2

2

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

______________________________________________________________________________________ 29

192-Contact ESBGA PCB Land Pattern

TOP VIEW

MAX108 192 Ball ESBGA

Printed Circuit Board (PCB) Land Pattern

MAX106

+5V Track/Hold Analog

+5V Comparator Analog

+5V Logic Digital

-5V Track/Hold Analog
+3.3V PECL Supply

T/H Ground

Comparator Ground

Logic Ground

VCCI
VCCA
VCCD
VEE
VCCO
GNDI
GNDA
GNDD

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

30 ______________________________________________________________________________________

Package Information

SUPER BGA.EPS

MAX106

±5V, 600Msps, 8-Bit ADC with On-Chip

2.2GHz Bandwidth Track/Hold Amplifier

Package Information (continued)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31

© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.