Rainbow Electronics MAX1011 User Manual

General Description

The MAX1011 is a 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer­ence, and a clock oscillator. The ADC converts analog
signals into binary-coded digital outputs at sampling
rates up to 90Msps. The ability to directly interface with
baseband signals makes the MAX1011 ideal for use in
a wide range of communications and instrumentation
applications.

The MAX1011’s input amplifier features a true differential
input, a -0.5dB analog bandwidth of 55MHz, and a user­programmable input full-scale range of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled signal,
input offset is typically less than 1/4LSB. Dynamic per­formance is 5.85 effective number of bits (ENOB) with a
20MHz analog input signal, or 5.7 ENOB with a 50MHz
signal.

The MAX1011 operates with +5V analog and +3.3V digi­tal supplies for easy interfacing to +3.3V-logic-compatible
digital signal processors and microprocessors. It comes
in a 24-pin QSOP package.

Applications

IF Sampling Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Instrumentation

Features

♦ High Sampling Rate: 90Msps
♦ Low Power Dissipation: 215mW
♦ Excellent Dynamic Performance:

5.85 ENOB with 20MHz Analog Input

5.7 ENOB with 50MHz Analog Input

♦ ±1/4LSB INL and DNL (typ)
♦ ±1/4LSB Input Offset (typ)
♦ Internal Bandgap Voltage Reference
♦ Internal Oscillator with Overdrive Capability
♦ 55MHz (-0.5dB) Bandwidth Input Amplifier with

True Differential Input

♦ User-Selectable Full-Scale Range

(125mVp-p, 250mVp-p, or 500mVp-p)

♦ Single-Ended or Differential Input Drive
♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs

MAX1011

Low-Power, 90Msps, 6-Bit ADC

________________________________________________________________

Maxim Integrated Products

1

MAX1011

D0–D5

DCLK

TNK+
TNK-

INPUT

AMP

IN+

IN-

GAIN

DATA

BUFFER

6

ADC

VREF

BANDGAP

REFERENCE

OCC+ OCC-

6

OFFSET

CORREC-

TION

CLOCK

OUT

CLOCK
DRIVER

Functional Diagram

19-1335; Rev 0a; 2/98

PART

MAX1011CEG 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

24 QSOP

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]
For small orders, phone [phone] ext. 3468.

Ordering Information

MAX1011

Low-Power, 90Msps, 6-Bit ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +5V ±5%, V

CCO

= 3.3V ±300mV, TA= T

MIN

to T

MAX

, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND ..........................................................-0.3V to +6.5V

V

CCO

to OGND......................................................-0.3V to +6.5V

GND to OGND ......................................................-0.3V to +0.3V

Digital and Clock Output Pins to OGND...-0.3V to V

CCO

(10sec)

All Other Pins to GND...............................................-0.3V to V

CC

Continuous Power Dissipation (TA= +70°C)

24-Pin QSOP (derate 10mW/°C above +70°C)...........800mW

Operating Temperature Range...............................0°C to +70°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, <10sec)...........................+300°C

CONDITIONS

LSB-0.5 ±0.25 0.5INLIntegral Nonlinearity

Bits6RESResolution

UNITSMIN TYP MAXSYMBOLPARAMETER

GAIN = open (mid gain)

GAIN = VCC(high gain)

No missing codes over temperature

237.5 250 262.5V

FSM

118.75 125 131.25V

FSH

LSB-0.5 ±0.25 0.5DNLDifferential Nonlinearity

Other analog input driven with external source
(Note 2)

Guaranteed by design

V1.75 2.75V

CM

GAIN = GND (low gain)

Common-Mode Voltage Range

pF1.5 3C

IN

Input Capacitance

kΩ13 20 29R

IN

Input Resistance

V2.25 2.35 2.45V

AOC

Input Open-Circuit Voltage

mVp-p

475 500 525V

FSL

Full-Scale Input Range

Other oscillator input tied to VCC+ 0.3V

I

SOURCE

= 50µA V0.7V

CCO

V

OH

Digital Outputs Logic-High
Voltage

kΩ4.8 8 12.1R

OSC

Oscillator Input Resistance

I

SINK

= 400µA V0.5V

OL

Digital Outputs Logic-Low
Voltage

VCC= 4.75V to 5.25V (Note 3)
20MHz, full-scale analog inputs,

CL= 15pF (Note 4)

mW215PDPower Dissipation

mA8.5 13.8I

CCO

Digital Outputs Supply Current

dB-65 -40PSRRPower-Supply Rejection Ratio

mA37 63.5I

CC

Supply Current

DC ACCURACY (Note 1)

INVERTING AND NONINVERTING ANALOG INPUTS

OSCILLATOR INPUTS

DIGITAL OUTPUTS (D0–D5)

POWER SUPPLY

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +5V ±5%, V

CCO

= 3.3V ±300mV, TA= +25°C, unless otherwise noted.)

Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).

However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common­mode input range (Figures 4 and 5).

Note 3: PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in V

CC

supply voltage,

expressed in decibels.

Note 4: The current in the V

CCO

supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran­sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig­ital outputs to a minimum.

Note 5: Offset-correction compensation enabled, 0.22µF at compensation inputs (Figures 2 and 3).
Note 6: t

PD

and t

SKEW

are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a

data bit. t

DCLK

is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-

itive load on the outputs is 15pF.

GAIN = GND, open, V

CC

GAIN = open (mid gain), fIN= 50MHz,

-1dB below full scale

GAIN = open (mid gain)

5.7

ENOB

M

5.6 5.85

Effective Number of Bits

GAIN = open (mid gain)

GAIN = GND (low gain)

Guaranteed by design

CONDITIONS

MHz55BWAnalog Input -0.5dB Bandwidth

Msps90f

MAX

Maximum Sample Rate

GAIN = VCC(high gain)

LSBOFFInput Offset (Note 5) -0.5 0.5

dB35.5 37SINAD

Signal-to-Noise Plus Distortion
Ratio

Bits

5.85ENOB

L

5.8ENOB

H

(Note 6)

(Note 6)

ns1t

SKEW

Data Valid Skew

ns3.0t

PD

Clock to Data Propagation
Delay

UNITSMIN TYP MAXSYMBOLPARAMETER

TNK+ to DCLK (Note 6) ns4.5t

DCLK

Input to DCLK Delay

Figure 8 ns5.5t

AD

Aperture Delay

Figure 8

clock
cycle

1PDPipeline Delay

TIMING CHARACTERISTICS (Data outputs: RL= 1MΩ, CL= 15pF)

DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VIN= 20MHz sine, amplitude -1dB below

full scale, unless otherwise noted.)

MAX1011

Low-Power, 90Msps, 6-Bit ADC

4 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(VCC= +5V ±5%, V

CCO

= 3.3V ±300mV, f

CLK

= 90Msps, GAIN = open (midgain) MAX1011 evaluation kit, TA= +25°C, unless

otherwise noted.)

6.0

5.0
10

100

EFFECTIVE NUMBER OF BITS

vs. ANALOG INPUT FREQUENCY

5.2

MAX1011-01

ANALOG INPUT FREQUENCY (MHz)

EFFECTIVE NUMBER OF BITS

5.4

5.6

5.8

f

CLK

= 90Msps

-1.0
1 10 100

ANALOG INPUT BANDWIDTH

-0.8

MAX1011-02

ANALOG INPUT FREQUENCY (MHz)

MAGNITUDE (dB)

-0.6

-0.2

-0.4

0

5.5
1 10 100

EFFECTIVE NUMBER OF BITS

vs. SAMPLING/CLOCK FREQUENCY

5.6

MAX1011-03

CLOCK FREQUENCY (MHz)

EFFECTIVE NUMBER OF BITS

5.7

5.9

5.8

6.0

fIN = 20MHz

-50

1k 100k 1M

OSCILLATOR OPEN-LOOP PHASE NOISE

vs. FREQUENCY OFFSET

-110

-130

-90

-70

MAX1011-04

FREQUENCY OFFSET FROM CARRIER (Hz)

PHASE NOISE (dBc)

10k

0.50

-0.50
0 64

INTEGRAL NONLINEARITY

vs. CODE

-0.25

0.25

MAX1011-06

CODE

INL (LSB)

10 20 30 40 50 60

0

0.50

-0.50
0 64

DIFFERENTIAL NONLINEARITY

vs. CODE

-0.25

0.25

MAX1003-07

CODE

DNL (LSB)

10 20 30 40 50 60

0

-80

-60

-40

-20

0

0 9 18 27 36 45

FFT PLOT

MAX1011-05

FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 19.9512MHz
f

CLK

= 90.000MHz
1024 POINTS
AC-COUPLED
SINGLE-ENDED
AVERAGED

_______________Detailed Description

Converter Operation

The MAX1011 integrates a 6-bit analog-to-digital con­verter (ADC), a buffered voltage reference, and oscilla­tor circuitry. The ADC uses a flash conversion technique
to convert an analog input signal into a 6-bit parallel
digital output code. The MAX1011’s unique design
includes 63 fully differential comparators and a propri­etary encoding scheme that ensures no more than
1LSB dynamic encoding error. The control logic inter­faces easily to most digital signal processors (DSPs)
and microprocessors (µPs) with +3.3V CMOS-compati­ble logic interfaces. Figure 1 shows the MAX1011 in a
typical application.

Programmable Input Amplifier

The MAX1011 has a programmable-gain input amplifier
with a -0.5dB bandwidth of 55MHz and a true differen­tial input. To maximize performance in high-speed
systems, the amplifier has less than 3pF of input
capacitance. The input amplifier gain is programmed
via the GAIN pin to provide three possible input full­scale ranges (FSRs) as shown in Table 1.

Single-ended and differential AC-coupled input circuit
examples are shown in Figures 2 and 3. Each of the

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 5

Pin Description

PIN

Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).GAIN1

FUNCTIONNAME

Positive Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground
pin 2 for DC-coupled inputs.

OCC+2

Noninverting Analog InputIN+4

Negative Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground
pin 3 for DC-coupled inputs.

OCC-3

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 9).V

CC

6

Analog GroundGND

9, 10,

12, 13

Inverting Analog InputIN-5

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 10).V

CC

11

Digital Clock Output. Frames the output data.DCLK18

Digital Output Supply, +3.3V ±300mV. Bypass with a 47pF capacitor to OGND (pin 16).V

CCO

17

Digital Outputs 0–5. D5 is the most significant bit (MSB).D0–D519–24

250Open
125V

CC

GAIN

500GND

INPUT FULL-SCALE RANGE

(mVp-p)

Table 1. Input Amplifier Programming

Positive Oscillator/Clock InputTNK+7
Negative Oscillator/Clock InputTNK-8

No ConnectionN.C.15
Digital Output GroundOGND16

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 13).V

CC

14

MAX1011

amplifier inputs is internally biased to a 2.35V reference
through a 20kΩ resistor, eliminating external DC bias
circuits. A series 0.1µF capacitor is required at the
amplifier input for AC-coupled signals.

When operating with AC-coupled inputs, the input
amplifier’s DC offset voltage is nulled to within ±1/2LSB
by an on-chip, offset-correction amplifier. An external
compensation capacitor is required to set the dominant

pole of the offset-correction amplifier’s frequency
response (Figures 2 and 3). The compensation capaci­tor will determine the low-frequency corner of the ana­log input response according to the following formula:

fc= 1 / (0.1 x C)

where C is the value of the compensation capacitor in
µF, and fcis the corner frequency in Hz.

Low-Power, 90Msps, 6-Bit ADC

6 _______________________________________________________________________________________

6 BITS

DATA

BUFFER

DIGITAL

DEMODULATOR

OR

DSP

6

DCLK

TANK

MAX1011

LO

RF

Figure 1. IF Sampling Receiver

Figure 2. Single-Ended AC-Coupled Input

Figure 3. Differential AC-Coupled Input

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+ OCC-

IN-

0.1µF

0.22µF

V

SOURCE

0.1µF

OFFSET

CORREC-

TION

0.1µF

V

SOURCE

0.1µF

IN+

IN-

20k

OCC+ OCC-

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

0.22µF

OFFSET

CORREC-

TION

MAX1011

For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The amplifi­er’s input common-mode voltage range extends from

1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offset­correction amplifier by grounding the OCC+ and OCC­pins (Figures 4 and 5).

ADC

The ADC block receives the analog signal from the
input amplifier. The ADC uses flash conversion with 63
fully differential comparators to digitize the analog input
signal into a 6-bit output in offset binary format.

The MAX1011 features a proprietary encoding scheme
that ensures no more than 1LSB dynamic encoding
error. Dynamic encoding errors resulting from meta­stable states may occur when the analog input voltage,
at the time the sample is taken, falls close to the deci­sion point for any one of the input comparators. The
resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1011’s unique design reduces the magnitude of
this type of error to 1LSB.

Internal Voltage Reference

An internal buffered-bandgap reference is included on
the MAX1011 to drive the ADC’s reference ladder. The

on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from exter­nal circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations of temperature and power supplies.

Oscillator Circuit

The MAX1011 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) net­work as shown in Figure 6. Alternatively, the oscillator
may be overdriven with an external clock source as
shown in Figure 7.

Internal Clock Operation (Tank)

If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequen­cy (SRF) of at least twice the intended oscillator fre­quency. Coilcraft’s 1008HS-221, with an SRF of
700MHz and a Q of 45, works well for this application.
Generate different clock frequency ranges by adjusting
varactor and tank elements.

An internal clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultane­ously clocked, maximizing the ADC’s effective number
of bits (ENOB) performance.

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 7

Figure 4. Single-Ended DC-Coupled Input

Figure 5. Differential DC-Coupled Input

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+ OCC-

IN-

OFFSET CORRECTION DISABLED

V

SOURCE

V

CM

1.75V TO 2.75V

OFFSET

CORREC-

TION

IN+

V

SOURCE

IN-

DIFFERENTIAL SOURCE

20k

WITH COMMON MODE
FROM 1.75V TO 2.75V.

20k

OFFSET CORRECTION DISABLED

OCC+ OCC-

OFFSET

CORREC-

TION

INPUT

AMP

MAX1011

2.35V INTERNAL REFERENCE

MAX1011

External Clock Operation

To accommodate designs that use an external clock,
the MAX1011’s internal oscillator can be overdriven by
an external clock source (Figure 7). The external clock
source should be a sinusoid to minimize clock phase
noise and jitter, which can degrade the ADC’s ENOB
performance. AC couple the clock source (recom­mended voltage level is approximately 1Vp-p) to the
oscillator inputs (Figure 7).

Output Data Format

The conversion results are output on a 6-bit-wide data
bus. Data is latched into the ADC output latch following
a pipeline delay of one clock cycle (Figure 8). Output
data is clocked out of the ADC’s data output pins (D0
through D5) on the rising edge of the clock output
(DCLK), with a DCLK-to-data propagation delay (tPD) of

3.0ns. The MAX1011 outputs are +3.3V CMOS-logic
compatible.

Transfer Function

Figure 9 shows the MAX1011’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.

___________Applications Information

The MAX1011 is designed with separate analog and
digital power-supply and ground connections to isolate
high-current digital noise spikes from the more sensi­tive analog circuitry. The high-current digital output
ground (OGND) and analog ground (GND) should be
at the same DC level, connected at only one location
on the board. This will provide best noise immunity and

improved conversion accuracy. Use of separate
ground planes is strongly recommended.

The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto the board, i.e., close to the connector. 10µF elec­trolytic capacitors with low-ESR ratings are recom­mended. For best effective bits performance, minimize
capacitive loading at the digital outputs. Keep the digi­tal output traces as short as possible.

The MAX1011 requires a +5V ±5% power supply for
the analog supply (V

CC

) and a +3.3V ±300mV power

supply connected to V

CCO

for the logic outputs.
Bypass each of the VCCsupply pins to its respective
GND with high-quality ceramic capacitors located as
close to the package as possible (Table 2). Consult the
evaluation kit manual for a suggested layout and
bypassing scheme.

Low-Power, 90Msps, 6-Bit ADC

8 _______________________________________________________________________________________

Figure 7. External Clock Drive Circuit

MAX1011

CLK

DRIVER

TNK-

V

CLK

V

CLK

= 300mV

p-p

TO 1.25V

p-p

TNK+

50Ω

50Ω

Z

0

= 50Ω

50Ω

0.1µF

0.1µF

0.01µFOscillator/Clock

47pFDigital Output

9

16

13

BYPASS
TO GND/

OGND

(PIN)

10

6

17

0.01µFConverter 14

VCC/

V

CCO

(PIN)

11

SUPPLY

FUNCTION

0.01µFAnalog Inputs

CAPACITOR

VALUE

Table 2. Bypassing Guide

Figure 6. Tank Resonator Oscillator

MAX1011

CLK

DRIVER

VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287
(SOT23 PACKAGE)
INDUCTOR COILCRAFT 1008HS-221.

V

TUNE

= 0V TO 8V

f

OSC

= 70MHz TO 109MHz

TNK-

TNK+

V

TUNE

220nH

5pF

47pF

47pF

47k

47k

10k

______________Dynamic Performance

Signal-to-noise and distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit­ed to frequencies above DC and below one-half the
ADC sample rate.

The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per­fect 6-bit ADC can do no better than 38dB.

The FFT Plot (see

Typical Operating Characteristics

)
shows the result of sampling a pure 20MHz sinusoid at
a 90MHz clock rate. This FFT plot of the output shows
the output level in various spectral bands. The plot has
been averaged to reduce the quantization noise floor
and reveal the low-amplitude spurs. This emphasizes the
excellent spurious-free dynamic range of the MAX1011.

The effective resolution (or effective number of bits) the
ADC provides can be measured by transposing the
equation that converts resolution to SINAD: N = (SINAD

- 1.76)/ 6.02 (see

Typical Operating Characteristics

).

MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________ 9

Figure 9. Ideal Transfer Function

111111

OUTPUT CODE

111110
111101

100001
100000
011111
011110

000011
000010
000001
000000

-FSR
2

0

1LSB

INPUT VOLTAGE (IN+ TO IN-)

FSR
2

Figure 8. MAX1011 Timing Diagram

DATA OUT

1.4V

DATA VALID N - 1 DATA VALID N

1.4V

50%

t

SKEW

t

DCLK

t

AD

t

PD

TNK+

(INPUT CLOCK)

DCLK

ANALOG

INPUT

N

N + 1

N + 2

MAX1011

Low-Power, 90Msps, 6-Bit ADC

10 ______________________________________________________________________________________

Pin Configuration Chip Information

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

D5
D4
D3
D2IN+

OCC-

OCC+

GAIN

TOP VIEW

D1

DCLK

D0

V

CCO

OGND

TNK-

TNK+

V

CC

IN-

16
15
14
13

9
10
11
12

N.C.
V

CC

GND

GND

V

CC

GND

GND

QSOP

MAX1011

TRANSISTOR COUNT: 2823
SUBSTRATE CONNECTED TO GND

MAX1011

Low-Power, 90Msps, 6-Bit ADC

______________________________________________________________________________________ 11

Package Information

QSOP.EPS

MAX1011

Low-Power, 90Msps, 6-Bit ADC

12 ______________________________________________________________________________________

NOTES