How it Works
Rainbow Electronics
Loading...
LM93
User Manual
92 pgs670.1 Kb0
Table of contents
Loading...

Rainbow Electronics LM93 User Manual

April 2004
LM93 Hardware Monitor with Integrated Fan Control for Server Management

1.0 General Description

The LM93, hardware monitor, has a two wire digital interface compatible with SMBus 2.0. Using an 8-bit Σ∆ ADC, the LM93 measures the temperature of two remote diode con­nected transistors as well as its own die and 16 power supply voltages.
To set fan speed, the LM93 has two PWM outputs that are each controlled by up to four temperature zones. The fan­control algorithm is lookup table based. The LM93 includes a digital filter that can be invoked to smooth temperature read­ings for better control of fan speed. The LM93 has four tachometer inputs to measure fan speed. Limit and status registers for all measured values are included.
The LM93 builds upon the functionality of previous mother­board management ASICs and uses some of the LM85’s features (i.e. smart tachometer mode). It also adds measure­ment and control support for dynamic Vccp monitoring and PROCHOT. It is designed to monitor a dual processor Xeon class motherboard with a minimum of external components.

2.0 Features

n 8-bit Σ∆ ADC n Monitors 16 power supplies n Monitors 2 remote thermal diodes n Internal ambient temperature sensing n Programmable autonomous fan control based on
temperature readings with fan boost support
n Fan control based on 13-step lookup table n Temperature reading digital filter n 1.0˚C digital temperature sensor resolution n 0.5˚C temperature resolution for fan control n 2 PWM fan speed control outputs n 4 fan tachometer inputs n Dual processor thermal throttling (PROCHOT)
monitoring
n Dual dynamic VID monitoring (6 VIDs per processor) n 8 general purpose I/Os:
— 4 can be configured as fan tachometer inputs — 2 can be configured to connect to THERMTRIP from
a processor
— 2 are standard GPIOs that could be used to monitor
IERR signal
n 2 general purpose inputs that can be used to monitor
SCSI termination signals
n Limit register comparisons of all monitored values n 2-wire, SMBus 2.0 compliant, serial digital interface
— Supports byte/block read and write — Configurable slave address (tri-level pin selects 1 of
3 possible addresses)
n 2.5V reference voltage output n 56-pin TSSOP package n XOR-tree test mode

3.0 Key Specifications

n Voltage Measurement Accuracy n Resolution 8-bits, 1˚C n Temperature Sensor Accuracy n Temperature Range:
— LM93 Operational 0˚C to +85˚C — Remote Temp Accuracy 0˚C to +125˚C
n Power Supply Voltage +3.0V to +3.6V n Power Supply Current 0.9 mA
±
2% FS (max)
±
3˚C (max)

4.0 Applications

n Servers n Workstations n Multi-Microprocessor based equipment
LM93 Hardware Monitor with Integrated Fan Control for Server Management

5.0 Ordering Information

Order Number NS Package Number Transport media
LM93CIMT MTD56 34 units in rail
LM93CIMTX MTD56 1000 units in tape-and-reel
I2C is a registered trademark of the Philips Corporation.
© 2004 National Semiconductor Corporation DS200682 www.national.com

6.0 Block Diagram

LM93
20068201
www.national.com 2

7.0 Application

Baseboard management of a Dual processor server. Two LM93s may be required to manage a quad processor base-
2 Way Xeon Server Management
LM93
board. The block diagram of LM93 hardware is illustrated below. The hardware implementation is a single chip ASIC solution.
20068205
www.national.com3
LM93
1.0 General Description ..................................................................................................................................... 1
Table of Contents
2.0 Features ....................................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................................ 1
4.0 Applications .................................................................................................................................................. 1
5.0 Ordering Information .................................................................................................................................... 1
6.0 Block Diagram .............................................................................................................................................. 2
7.0 Application .................................................................................................................................................... 3
8.0 Connection Diagram .................................................................................................................................... 7
9.0 Pin Descriptions ........................................................................................................................................... 8
10.0 Server Terminology .................................................................................................................................. 10
11.0 Recommended Implementation ................................................................................................................ 11
12.0 Functional Description .............................................................................................................................. 12
12.1 MONITORING CYCLE TIME ................................................................................................................ 12
12.2 Σ∆ A/D INHERENT AVERAGING .......................................................................................................... 12
12.3 TEMPERATURE MONITORING ........................................................................................................... 12
12.3.1 Temperature Data Format ............................................................................................................... 12
12.3.2 Thermal Diode Fault Status ............................................................................................................. 12
12.4 VOLTAGE MONITORING ...................................................................................................................... 12
12.5 RECOMMENDED EXTERNAL SCALING RESISTORS FOR +12V POWER RAILS .......................... 13
12.6 RECOMMENDED EXTERNAL SCALING CIRCUIT FOR −12V POWER INPUT ................................ 13
12.7 DYNAMIC Vccp MONITORING USING VID ......................................................................................... 15
12.8 V
OUTPUT ....................................................................................................................................... 15
REF
12.9 PROCHOT BACKGROUND INFORMATION ........................................................................................ 15
12.10 PROCHOT MONITORING .................................................................................................................. 16
12.11 PROCHOT OUTPUT CONTROL ........................................................................................................ 16
12.12 FAN SPEED MEASUREMENT ........................................................................................................... 17
12.13 SMART FAN SPEED MEASUREMENT ............................................................................................. 17
13.0 Inputs/Outputs .......................................................................................................................................... 17
13.1 ALERT OUTPUT ................................................................................................................................... 17
13.2 RESET INPUT/OUTPUT ....................................................................................................................... 17
13.3 PWM1 AND PWM2 OUTPUTS ............................................................................................................. 17
13.4 SCSI_TERMx INPUTS .......................................................................................................................... 17
13.5 VRD1_HOT AND VRD2_HOT INPUTS ................................................................................................ 18
13.6 GPIO PINS ............................................................................................................................................ 18
13.7 FAN TACH INPUTS ............................................................................................................................... 18
14.0 SMBus Interface ....................................................................................................................................... 18
14.1 SMBUS ADDRESSING ......................................................................................................................... 18
14.2 DIGITAL NOISE EFFECT ON SMBUS COMMUNICATION ................................................................. 18
14.3 GENERAL SMBUS TIMING .................................................................................................................. 18
14.4 SMBUS ERROR SAFETY FEATURES ................................................................................................ 19
14.5 SERIAL INTERFACE PROTOCOLS ..................................................................................................... 19
14.5.1 Address Incrementing ...................................................................................................................... 19
14.5.2 Block Command Code Summary .................................................................................................... 20
14.5.3 Write Operations ............................................................................................................................. 20
14.5.3.1 Write Byte ................................................................................................................................... 20
14.5.3.2 Write Word ................................................................................................................................. 20
14.5.3.3 SMBus Write Block to Any Address ........................................................................................... 21
14.5.3.4 I
2
C™Block Write ....................................................................................................................... 21
14.5.4 Read Operations .............................................................................................................................. 22
14.5.4.1 Read Byte .................................................................................................................................. 22
14.5.4.2 Read Word ................................................................................................................................. 22
14.5.4.3 SMBus Block-Write Block-Read Process Call ........................................................................... 22
14.5.4.4 Simulated SMBus Block-Write Block-Read Process Call .......................................................... 24
14.5.4.5 SMBus Fixed Address Block Reads .......................................................................................... 24
14.5.4.6 I
2
C Block Reads ......................................................................................................................... 25
14.6 READING AND WRITING 16-BIT REGISTERS ................................................................................... 25
15.0 Using The LM93 ....................................................................................................................................... 26
15.1 POWER ON .......................................................................................................................................... 26
15.2 RESETS ................................................................................................................................................ 26
15.3 ADDRESS SELECTION ........................................................................................................................ 26
15.4 DEVICE SETUP .................................................................................................................................... 26
15.5 ROUND ROBIN VOLTAGE/TEMPERATURE CONVERSION CYCLE ................................................. 26
www.national.com 4
Table of Contents (Continued)
15.6 ERROR STATUS REGISTERS ............................................................................................................. 27
15.6.1 ASF Mode ........................................................................................................................................ 27
15.7 MASKING, ERROR STATUS AND ALERT ........................................................................................... 27
15.8 LAYOUT AND GROUNDING ................................................................................................................ 27
15.9 THERMAL DIODE APPLICATION ......................................................................................................... 27
15.9.1 Accuracy Effects of Diode Non-Ideality Factor ................................................................................ 28
15.9.2 PCB Layout for Minimizing Noise .................................................................................................... 28
15.10 FAN CONTROL ................................................................................................................................... 28
15.10.1 Automatic Fan Control Algorithm ................................................................................................... 28
15.10.2 Fan Control Temperature Resolution ............................................................................................ 30
15.10.3 Zone 1-4 to PWM1-2 Binding ........................................................................................................ 31
15.10.4 Fan Control Duty Cycles ............................................................................................................... 31
15.10.5 Alternate PWM Frequencies .......................................................................................................... 31
15.10.6 Fan Control Priorities ..................................................................................................................... 31
15.10.7 PWM to 100% Conditions ............................................................................................................. 31
15.10.8 VRDx_HOT Ramp-Up/Ramp-Down .............................................................................................. 32
15.10.9 PROCHOT Ramp-Up/Ramp-Down ............................................................................................... 32
15.10.10 Manual PWM Override ................................................................................................................ 32
15.10.11 Fan Spin-Up Control .................................................................................................................... 32
15.11 XOR TREE TEST ................................................................................................................................ 33
16.0 Registers .................................................................................................................................................. 34
16.1 REGISTER WARNINGS ....................................................................................................................... 34
16.2 REGISTER SUMMARY TABLE ............................................................................................................. 34
16.3 FACTORY REGISTERS 00h–3Fh ........................................................................................................ 40
16.3.1 Register 00h XOR Test ................................................................................................................. 40
16.3.2 Register 01h SMBus Test ............................................................................................................. 40
16.3.3 Register 3Eh Manufacturer ID ...................................................................................................... 40
16.3.4 Register 3Fh Version/Stepping ..................................................................................................... 40
16.4 BMC ERROR STATUS REGISTERS 40h–47h .................................................................................... 41
16.4.1 Register 40h B_Error Status 1 ...................................................................................................... 41
16.4.2 Register 41h B_Error Status 2 ...................................................................................................... 42
16.4.3 Register 42h B_Error Status 3 ...................................................................................................... 42
16.4.4 Register 43h B_Error Status 4 ...................................................................................................... 43
16.4.5 Register 44h B_P1_PROCHOT Error Status ............................................................................... 43
16.4.6 Register 45h B_P2_PROCHOT Error Status ............................................................................... 44
16.4.7 Register 46h B_GPI Error Status .................................................................................................. 44
16.4.8 Register 47h B_Fan Error Status .................................................................................................. 45
16.5 HOST ERROR STATUS REGISTERS .................................................................................................. 45
16.5.1 Register 48h H_Error Status 1 ...................................................................................................... 45
16.5.2 Register 49h H_Error Status 2 ...................................................................................................... 46
16.5.3 Register 4Ah H_Error Status 3 ..................................................................................................... 47
16.5.4 Register 4Bh H_Error Status 4 ..................................................................................................... 48
16.5.5 Register 4Ch H_P1_PROCHOT Error Status ............................................................................... 49
16.5.6 Register 4Dh B_P2_PROCHOT Error Status ............................................................................... 50
16.5.7 Register 4Eh H_GPI Error Status ................................................................................................. 51
16.5.8 Register 4Fh H_Fan Error Status ................................................................................................. 52
16.6 VALUE REGISTERS ............................................................................................................................. 52
16.6.1 Registers 50–53h Unfiltered Temperature Value Registers ......................................................... 52
16.6.2 Registers 54–55h Filtered Temperature Value Registers ............................................................. 52
16.6.3 Register 56–65h A/D Channel Voltage Registers ........................................................................ 53
16.6.4 Register 67h Current P1_PROCHOT ........................................................................................... 53
16.6.5 Register 68h Average P1_PROCHOT .......................................................................................... 54
16.6.6 Register 69h Current P2_PROCHOT ........................................................................................... 54
16.6.7 Register 6Ah Average P2_PROCHOT ......................................................................................... 54
16.6.8 Register 6Bh GPI State ................................................................................................................. 55
16.6.9 Register 6Ch P1_VID .................................................................................................................... 55
16.6.10 Register 6Dh P2_VID .................................................................................................................. 55
16.6.11 Register 6E–75h Fan Tachometer Readings .............................................................................. 56
16.7 LIMIT REGISTERS ................................................................................................................................ 57
16.7.1 Registers 78–7Fh Temperature Limit Registers ........................................................................... 57
16.7.2 Registers 80–83h Fan Boost Temperature Registers .................................................................. 57
LM93
www.national.com5
LM93
16.7.3 Registers 90–AFh Voltage Limit Registers ................................................................................... 58
16.7.4 Register B0–B1h PROCHOT User Limit Registers ...................................................................... 59
16.7.5 Register B2–B3h Dynamic Vccp Limit Offset Registers ............................................................... 60
16.7.6 Register B4–BBh Fan Tach Limit Registers ................................................................................. 61
16.8 SETUP REGISTERS ............................................................................................................................. 62
16.8.1 Register BCh Special Function Control 1 (Voltage Hysteresis and Fan Control Filter Enable) ... 62
16.8.2 Register BDh Special Function Control 2 (Smart Tach Mode Enable and Fan Control Temperature
Resolution Control) ..................................................................................................................................... 63
16.8.3 Register BEh GPI/VID Level Control ............................................................................................63
16.8.4 Register BFh PWM Ramp Control ................................................................................................ 64
16.8.5 Register C0h Fan Boost Hysteresis (Zones 1/2) .......................................................................... 64
16.8.6 Register C1h Fan Boost Hysteresis (Zones 3/4) .......................................................................... 65
16.8.7 Register C2h Zones 1/2 Spike Smoothing Control ....................................................................... 65
16.8.8 Register C3h Zones 1/2 MinPWM and Hysteresis ....................................................................... 66
16.8.9 Register C4h Zones 3/4 MinPWM and Hysteresis ....................................................................... 66
16.8.10 Register C5h GPO ...................................................................................................................... 67
16.8.11 Register C6h PROCHOT Override .............................................................................................. 68
16.8.12 Register C7h PROCHOT Time Interval ...................................................................................... 69
16.8.13 Register C8h PWM1 Control 1 ................................................................................................... 70
16.8.14 Register C9h PWM1 Control 2 ................................................................................................... 71
16.8.15 Register CAh PWM1 Control 3 ................................................................................................... 72
16.8.16 Register CBh Special Function PWM1 Control 4 ....................................................................... 72
16.8.17 Register CCh PWM2 Control 1 ................................................................................................... 73
16.8.18 Register CDh PWM2 Control 2 ................................................................................................... 74
16.8.19 Register CEh PWM2 Control 3 ................................................................................................... 75
16.8.20 Register CFh Special Function PWM2 Control 4 ....................................................................... 75
16.8.21 Register D0h–D3h Zone 1 to 4 Base Temperatures .................................................................. 76
16.8.22 Register D4h–DFh Lookup Table Steps— Zone 1/2 and Zone 3/4 Offset Temperature ........... 76
16.8.23 Register E0h Special Function TACH to PWM Binding .............................................................. 77
16.8.24 Register E2h LM93 Status Control .............................................................................................78
16.8.25 Register E3h LM93 Configuration ............................................................................................... 79
16.9 SLEEP STATE CONTROL AND MASK REGISTERS .......................................................................... 80
16.9.1 Register E4h Sleep State Control ................................................................................................ 80
16.9.2 Register E5h S1 GPI Mask ........................................................................................................... 81
16.9.3 Register E6h S1 Tach Mask ......................................................................................................... 81
16.9.4 Register E7h S3 GPI Mask ........................................................................................................... 82
16.9.5 Register E8h S3 Tach Mask ......................................................................................................... 82
16.9.6 Register E9h S3 Temperature/Voltage Mask ................................................................................ 82
16.9.7 Register EAh S4/5 GPI Mask ....................................................................................................... 83
16.9.8 Register EBh S4/5 Temperature/Voltage Mask ............................................................................ 83
16.10 OTHER MASK REGISTERS ............................................................................................................... 84
16.10.1 Register ECh GPI Error Mask ..................................................................................................... 84
16.10.2 Register EDh Miscellaneous Error Mask .................................................................................... 84
16.10.3 Register EEh Special Function Zone 1 Adjustment Offset ......................................................... 85
16.10.4 Register EFh Special Function Zone 2 Adjustment Offset ......................................................... 85
17.0 Absolute Maximum Ratings ..................................................................................................................... 86
18.0 Operating Ratings ................................................................................................................................... 86
19.0 Data Sheet Version History ...................................................................................................................... 91
20.0 Physical Dimensions ................................................................................................................................ 92
Table of Contents (Continued)
www.national.com 6

8.0 Connection Diagram

LM93
56 Pin TSSOP
NS Package MTD56
Top View
NS Order Numbers:
LM93CIMT (34 units per rail), or
LM93CIMTX (1000 units per tape-and-reel)
20068202
www.national.com7

9.0 Pin Descriptions

LM93
Symbol Pin # Type Function
GPIO_0/TACH1 1 Digital I/O
(Open-Drain)
GPIO_1/TACH2 2 Digital I/O
(Open-Drain)
GPIO_2/TACH3 3 Digital I/O
(Open-Drain)
GPIO_3/TACH4 4 Digital I/O
(Open-Drain)
GPIO_4 / P1_THERMTRIP
GPIO_5 / P2_THERMTRIP
5 Digital I/O
(Open-Drain)
6 Digital I/O
(Open-Drain)
GPIO_6 7 Digital I/O
(Open-Drain)
GPIO_7 8 Digital I/O
(Open-Drain)
VRD1_HOT
9 Digital Input CPU1 voltage regulator HOT
Can be configured as fan tach input or a general purpose open-drain digital I/O.
Can be configured as fan tach input or a general purpose open-drain digital I/O.
Can be configured as fan tach input or a general purpose open-drain digital I/O.
Can be configured as fan tach input or a general purpose open-drain digital I/O..
A general purpose open-drain digital I/O. Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors.
A general purpose open-drain digital I/O. Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors.
Can be used to detect the state of CPU1 IERR or a general purpose open-drain digital I/O
Can be used to detect the state of CPU2 IERR or a general purpose open-drain digital I/O
VRD2_HOT 10 Digital Input CPU2 voltage regulator HOT
SCSI_TERM1 11 Digital Input SCSI Channel 1 termination fuse. Could also be used as a general
purpose input to trigger an error event.
SCSI_TERM2
12 Digital Input SCSI Channel 2 termination fuse. Could also be used as a general
purpose input to trigger an error event.
SMBDAT 13 Digital I/O
(Open-Drain)
Bidirectional System Management Bus Data. Output configured as 5V tolerant open-drain. SMBus 2.0 compliant.
SMBCLK 14 Digital Input System Management Bus Clock. Driven by an open-drain output,
and is 5V tolerant. SMBus 2.0 Compliant.
ALERT/XtestOut
15 Digital Output
(Open-Drain)
Open-drain ALERT output used in an interrupt driven system to signal that an error event has occurred. Masked error events do not activate the ALERT output. When in XOR tree test mode, functions as XOR Tree output.
RESET
16 Digital I/O
(Open-Drain)
Open-drain reset output when power is first applied to the LM93. Used as a reset for devices powered by 3.3V stand-by. After reset, this pin becomes a reset input. See section 6.2 for more information.
AGND 17 GROUND Input Analog Ground
V
REF
18 Analog Output 2.5V used for external ADC reference, or as a V
REF
reference
voltage
REMOTE1− 19 Remote Thermal
Diode_1- Input (CPU 1 THERMDC)
This is the negative input (current sink) from the CPU1 thermal diode. Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE1− and REMOTE1+.
REMOTE1+ 20 Remote Thermal
Diode_1+ I/O (CPU1 THERMDA)
This is a positive connection to the CPU1 thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE1− and REMOTE1+.
www.national.com 8
9.0 Pin Descriptions (Continued)
Symbol Pin # Type Function
REMOTE2− 21 Remote Thermal
Diode_2 - Input (CPU2 THERMDC)
REMOTE2+ 22 Remote Thermal
Diode_2 + I/O (CPU2 THERMDA)
AD_IN1 23 Analog Input (+12V1) Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator.
AD_IN2 24 Analog Input (+12V2) Analog Input for +12V Rail 2 monitoring, for CPU2 voltage regulator.
AD_IN3 25 Analog Input (+12V3) Analog Input for +12V Rail 3, for Memory/3GIO slots. External
AD_IN4 26 Analog Input
(FSB_Vtt)
AD_IN5 27 Analog Input (3GIO /
PXH / MCH_Core)
AD_IN6 28 Analog Input
(ICH_Core)
AD_IN7 (P1_Vccp) 29 Analog Input
(CPU1_Vccp)
AD_IN8 (P2_Vccp) 30 Analog Input
(CPU2_Vccp)
AD_IN9 31 Analog Input (+3.3V) Analog input for +3.3V monitoring.
AD_IN10 32 Analog Input (+5V) Analog input for +5V monitoring silver box supply monitoring.
AD_IN11 33 Analog Input
(SCSI_Core)
AD_IN12 34 Analog Input
(Mem_Core)
AD_IN13 35 Analog Input
(Mem_Vtt)
AD_IN14 36 Analog Input
(Gbit_Core)
AD_IN15 37 Analog Input (-12V) Analog input for -12V monitoring. External resistors required to scale
Address Select 38 3 level analog input This input selects the lower two bits of the LM93 SMBus slave
This is the negative input (current sink) from the CPU2 thermal diode. Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE2− and REMOTE2+.
This is a positive connection to the CPU2 thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE2− and REMOTE2+.
External attenuation resistors required such that 12V is attenuated to 0.927V.
External attenuation resistors required such that 12V is attenuated to 0.927V.
attenuation resistors required such that 12V is attenuated to 0.927V.
Analog input for 1.2V monitoring
Analog input for 1.5V monitoring.
Analog input for 1.5V monitoring.
Analog input for +Vccp (processor voltage) monitoring.
Analog input for +Vccp (processor voltage) monitoring.
Analog input for +2.5V monitoring.
Analog input for +1.969V monitoring.
Analog input for +0.984V monitoring.
Analog input for +0.984V S/B monitoring.
to positive level. Full scale reading at 1.236V.
address.
LM93
www.national.com9
9.0 Pin Descriptions (Continued)
LM93
Symbol Pin # Type Function
AD_IN16 39 POWER (V
standby power
GND 40 GROUND Digital Ground. Digital ground and analog ground need to be tied
PWM1 41 Digital Output
(Open-Drain)
PWM2 42 Digital Output
(Open-Drain)
P1_VID0 43 Digital Input Voltage Identification signal from the processor.
P1_VID1 44 Digital Input Voltage Identification signal from the processor.
P1_VID2 45 Digital Input Voltage Identification signal from the processor.
P1_VID3 46 Digital Input Voltage Identification signal from the processor.
P1_VID4 47 Digital Input Voltage Identification signal from the processor.
P1_VID5 48 Digital Input Voltage Identification signal from the processor.
P1_PROCHOT
P2_PROCHOT
P2_VID0 51 Digital Input Voltage Identification signal from the processor.
P2_VID1 52 Digital Input Voltage Identification signal from the processor.
P2_VID2 53 Digital Input Voltage Identification signal from the processor.
P2_VID3 54 Digital Input Voltage Identification signal from the processor.
P2_VID4 55 Digital Input Voltage Identification signal from the processor.
P2_VID5 56 Digital Input Voltage Identification signal from the processor.
49 Digital I/O
(Open-Drain)
50 Digital I/O
(Open-Drain)
) +3.3V
DD
VDDpower input for LM93. Generally this is connected to +3.3V standby power. The LM93 can be powered by +3.3V if monitoring in low power states is not required, but power should be applied to this input before any other pins. This pin also serves as the analog input to monitor the 3.3V stand-by (SB) voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100 pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF should be closest to the power pin.
together at the chip then both taken to a low noise system ground. A voltage difference between analog and digital ground may cause erroneous results.
Fan control output 1.
Fan control output 2
Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional level shifter.
Connected to CPU2 PROCHOT (processor hot) signal through a bi-directional level shifter.
The overscore indicates the signal is active low (“Not”).

10.0 Server Terminology

A/D Analog to Digital Converter
ACPI Advanced Configuration and Power
Interface
ALERT
ASF Alert Standard Format
BMC Baseboard Micro-Controller
BW Bandwidth
DIMM Dual inline memory module
DP Dual-processor
ECC Error checking and correcting
FRU Field replaceable unit
FSB Front side bus
www.national.com 10
SMBus signal to bus master that an event occurred that has been flagged for attention.
FW Firmware
Gb Gigabit
GB Gigabyte
Gbe Gigabit Ethernet
GPIO General purpose I/O
HW Hardware
2
I
C Inter integrated circuit (bus)
LAN Local area network
LVDS Low-Voltage Differential Signaling
Mb Megabit
MB Megabyte
MP Multi-processor
MTBF Mean time between failures
LM93
10.0 Server Terminology (Continued)
MTTR Mean time to repair
NIC Network Interface Card (Ethernet Card)
OS Operating system
P/S Power Supply
PCI PCI Local Bus
PDB Power Distribution Board

11.0 Recommended Implementation

POR Power On Reset
PS Power Supply
SMBCLK and SMBDAT
VRD Voltage Regulator Down - regulates Vccp
These signals comprise the SMBus interface (data and clock) See the SMBus Interface section for more information.
voltage for a CPU
Note: 100 pF cap is optional and should be placed close to the LM93, if used. The maximum capacitance between these pins is 300 pF.
20068207
20068206
www.national.com11

12.0 Functional Description

LM93
The LM93 provides 16 channels of voltage monitoring, two remote thermal diode monitors, an onboard ambient tem­perature sensor, 2 PROCHOT monitors, 4 fan tachometers, 8 GPIOs, THERMTRIP monitor for masking error events, 2 SCSI_TERM inputs, and all the associated limit registers on a single chip, which communicates to the rest of the base­board over the System Management Bus (SMBus).
Readings from both the external thermal diodes and the internal temperature sensor are made available as an 8-bit two’s-complement digital byte with the LSB representing 1˚C.
All but 4 of the analog inputs include internal scaling resis­tors. External scaling resistors are required for measuring
±
12V. The inputs are converted to 8-bit digital values such that a nominal voltage appears at ages and
1
⁄4scale for negative voltages. The analog inputs
3
⁄4scale for positive volt-
are intended to be connected to both baseboard resident VRDs and to standard voltage rails supplied by a SSI com­pliant power supply.
The LM93 provides a number of internal registers, which are detailed in the register section of this document.

12.1 MONITORING CYCLE TIME

When the LM93 is powered up, it cycles through each tem­perature measurement followed by the analog voltages in sequence, and it continuously loops through the sequence. The total monitoring cycle time is not more than 100 ms, as this is the time period that most external micro-controllers require to read the register values.
Each measured value is compared to values stored in the limit registers. When the measured value violates the pro­grammed limit, a corresponding status bit in the B_ and H_Error Status Registers is set.
The PROCHOT and dynamic VID/Vccp monitoring is per­formed independently of the analog and temperature moni­toring cycle.

12.2 Σ∆ A/D INHERENT AVERAGING

The Σ∆ A/D architecture filters the input signal. During one conversion many samples are taken of the input voltage and these samples are effectively averaged to give the final result. The output of the Σ∆ A/D is the average value of the signal during the sampling interval. For a voltage measure­ment, the samples are accumulated for 1.5 ms. For a tem­perature measurement, the samples are accumulated for
8.4 ms.

12.3 TEMPERATURE MONITORING

The LM93 remote diode target is the embedded thermal diode found in a Xeon class processor. In some cases instead of using the embedded thermal diode, found on the Xeon processor, a diode connected 2N3904 transistor type can also be used. An example of this would be a MMBT3904 with its collector and base tied to the thermal diode RE­MOTE+ pin and the emitter tied to the thermal diode REMOTE− pin. Since the MMBT3904 is a surface mount device and has very small thermal mass, it measures the board temperature where it is mounted. The non-ideality and series resistance varies for different diodes. Since the LM93 is optimized for the Xeon processor, when measuring a 2N3904 transistor an offset in the error band of approxi­mately −4˚C may be observed. This can be corrected for by programming the appropriate Zone Adjustment Offset regis­ter.
The LM93 acquires temperature data from three different sources:
2 external diodes (embedded in a processor or discrete) 1 internal diode (internal to the LM93) In addition to these three temperatures, a fourth temperature
can be externally written into the LM93 from the SMBus. This value can be used to control fans, or compared against limits, etc. The temperature value registers are located at addresses 50h–53h. The temperature sources are referred to as “zones” for convenience:
Zone Description
Zone 1 Processor 1 remote diode
(REMOTE1+, REMOTE1−)
Zone 2 Processor 2 remote diode
(REMOTE2+, REMOTE2−)
Zone 3 Internal LM93 on-chip sensor
Zone 4 External Digital Sensor written in from SMBus

12.3.1 Temperature Data Format

Most of the temperature data for the LM93 is represented in a common format. The format is an 8-bit, twos complement byte with the LSB equal to 1.0 ˚C. This applies to tempera­ture measurements as well as any temperature limit regis­ters and some configuration registers. Some fan control configuration registers use four bits and have a binary for­mat, please see the fan control configuration register de­scriptions for further details on this 4-bit format.
Temperature Binary Hex
+125˚C 0111 1101 7Dh
+25˚C 0001 1001 19h
+1.0˚C 0000 0001 01h
0˚C 0000 0000 00h
−1.0˚C 1111 1111 FFh
−25˚C 1110 0111 E7h
−55˚C 1100 1001 C9h
−127˚C 1000 0001 81h
Note: A value of 80h has a special meaning in the limit registers. It means that the temperature channel is masked. In addition, temperature readings of 80h indicate thermal diode faults.

12.3.2 Thermal Diode Fault Status

The LM93 provides for indications of a fault (open or short circuit) with the remote thermal diodes. Before a remote diode conversion is updated, the status of the remote diode is checked for an open or short circuit condition. If such a fault condition occurs, a status bit is set in the status register. A short circuit is defined as the input pins being connected to each other. When an open or short circuit is detected, the corresponding temperature register is set to 80h.

12.4 VOLTAGE MONITORING

The LM93 contains inputs for monitoring voltages. Scaling is such that the correct value refers to approximately 3/4 scale
±
or 192 decimal on all inputs except the
12V. Input voltages are converted by an 8-bit Delta-Sigma (∆Σ) A/D. The Delta­Sigma A/D architecture provides inherent filtering and spike smoothing of the analog input signal.
±
12V inputs must be scaled externally. A full scale
The reading is achieved when 1.236V is applied to these inputs. For optimum performance the +12V should be scaled to
www.national.com 12
12.0 Functional Description
(Continued)
provide a nominal should be scaled to provide a nominal thevenin resistance at the pin should be kept between 1 kΩ and7kΩ.
The −12V monitoring is particularly challenging. It is required
3
⁄4full scale reading, while the −12V
1
⁄4scale reading. The
to bring the −12V rail into the positive input voltage region of the A/D input. It is suggested that the supply rail for the LM93 device be used as the offset voltage. This voltage is usually derived from the P/S 5V stand-by voltage rail via a accurate linear regulator. In this fashion we can always assume that the offset voltage is present when the −12V rail is present as the system cannot be turned on without the
3.3V stand-by voltage being present.
that an external offset voltage and external resistors be used

Voltage vs Register Reading

Register Reading
at
Nominal
Maximum
Voltage
Pin
Normal
Use
Nominal
Voltage
Voltage
AD_IN1 +12V1 0.927V C0h 1.236V FFh 0V 00h −0.3V to (V
AD_IN2 +12V2 0.927V C0h 1.236V FFh 0V 00h −0.3V to (V
AD_IN3 +12V3 0.927V C0h 1.236V FFh 0V 00h −0.3V to (V
Register
Reading at
Maximum
Voltage
Minimum
Voltage
Register
Reading at
Minimum
Voltage
Absolute
Maxmum Range
+ 0.05V)
DD
+ 0.05V)
DD
+ 0.05V)
DD
AD_IN4 FSB_Vtt 1.20V C0h 1.60V FFh 0V 00h −0.3V to +6.0V
AD_IN5 3GIO 1.5V C0h 2V FFh 0V 00h −0.3V to +6.0V
AD_IN6 ICH_Core 1.5V C0h 2V FFh 0V 00h −0.3V to +6.0V
AD_IN7 Vccp1 1.20V C0h 1.60V FFh 0V 00h −0.3V to +6.0V
AD_IN8 Vccp2 1.20V C0h 1.60V FFh 0V 00h −0.3V to +6.0V
AD_IN9 +3.3V 3.30V C0h 4.40V FFh 0V 00h −0.3V to +6.0V
AD_IN10 +5V 5.0V C0h 6.667V FAh 0V 00h −0.3V to +6.5V
AD_IN11 SCSI_Core 2.5V C0h 3.333V FFh 0V 00h −0.3V to +6.0V
AD_IN12 Mem_Core 1.969V C0h 2.625V FFh 0V 00h −0.3V to +6.0V
AD_IN13 Mem_Vtt 0.984V C0h 1.312V FFh 0V 00h −0.3V to +6.0V
AD_IN14 Gbit_Core 0.984V C0h 1.312V FFh 0V 00h −0.3V to +6.0V
AD_IN15 −12V 0.309V 40h 1.236V FFh 0V 00h −0.3V to (V
DD
+ 0.05V)
AD_IN16 +3.3V S/B 3.3V C0h 3.6V D1h 3.0V AEh −0.3V to +6.0V
Application Note: The nominal voltages listed in this table are only typical values. Voltage rails with different nominal voltages can be monitored, but the register reading at the nominal value is no longer C0h. For example, a Mem_Core rail at 2.5V nominal could be monitored with AD_IN12, or a Mem_Vtt rail at 1.2V could be monitored with AD_IN13.
LM93
±
1%

12.5 RECOMMENDED EXTERNAL SCALING RESISTORS FOR +12V POWER RAILS

The +12V inputs require external scaling resistors. The re­sistors need to scale 12V down to 0.927V.
Required External Scaling
Resistors for +12V Power Input
yields a ratio of 11.94498, which has a +0.27% deviation from the theoretical. It is also recommended that the resis-
±
tors have
1% tolerance or better.
Each LSB in the voltage value registers has a weight of 12V / 192 = 62.5 mV. To calculate the actual voltage of the +12V power input, use the following equation:
= (8-bit value register code) x (62.5 mV)
V
IN
12.6 RECOMMENDED EXTERNAL SCALING CIRCUIT FOR −12V POWER INPUT
20068208
To calculate the required ratio of R1 to R2 use this equation:
The −12V input requires external resistors to level shift the nominal input voltage of −12V to +0.309V.
It is recommended that the equivalent thevenin resistance of the divider be between 1k and 7k to minimize errors caused by leakage currents at extreme temperatures. The best val­ues for the resistors are: R1=13.7 kΩ and R2=1.15 kΩ. This
www.national.com13
12.0 Functional Description
LM93
(Continued)
Required External Level Shifting
Resistors for −12V Power Input
20068210
The +3.3V standby voltage is used as a reference for the level shifting. Therefore, the tolerance of this voltage directly effects the accuracy of the −12V reading. To minimize ratio
±
errors, a tolerance of better than
1% should be used. It is recommended that the equivalent thevenin resistance of the divider is between 1k and 7k to minimize errors caused by leakage currents at extreme temperatures. To calculate the ratio of R1 to R2 use this equation:
where VINis the nominal input voltage of −12V, V reference voltage of +3.3V and AD_IN is the voltage required at the AD input for a
1
⁄4scale reading or 0.309V.
Therefore, for this case:
Using standard 1% resistor values for R1 of 5.76 kΩ and R2 of 1.4 kΩ yields an R1 to R2 ratio of 4.1143.
The input voltage V
can be calculated using the value
IN
register reading (VR) using this equation:
The table below summarizes the theoretical voltage values for value register readings near −12V.
Value Register V
IN
% ∆ from −12V
15 -13.2068 -10.0563
16 -13.1821 -9.8505
17 -13.1574 -9.6448
18 -13.1327 -9.4390
19 -13.1080 -9.2332
20 -13.0833 -9.0275
21 -13.0586 -8.8217
22 -13.0339 -8.6159
23 -13.0092 -8.4101
24 -12.9845 -8.2044
25 -12.9598 -7.9986
26 -12.9351 -7.7928
REF
is the
Value Register V
IN
27 -12.9104 -7.5871
28 -12.8858 -7.3813
29 -12.8611 -7.1755
30 -12.8364 -6.9698
31 -12.8117 -6.7640
32 -12.7870 -6.5582
33 -12.7623 -6.3524
34 -12.7376 -6.1467
35 -12.7129 -5.9409
36 -12.6882 -5.7351
37 -12.6635 -5.5294
38 -12.6388 -5.3236
39 -12.6141 -5.1178
40 -12.5894 -4.9121
41 -12.5648 -4.7063
42 -12.5401 -4.5005
43 -12.5154 -4.2947
44 -12.4907 -4.0890
45 -12.4660 -3.8832
46 -12.4413 -3.6774
47 -12.4166 -3.4717
48 -12.3919 -3.2659
49 -12.3672 -3.0601
50 -12.3425 -2.8544
51 -12.3178 -2.6486
52 -12.2931 -2.4428
53 -12.2684 -2.2370
54 -12.2438 -2.0313
55 -12.2191 -1.8255
56 -12.1944 -1.6197
57 -12.1697 -1.4140
58 -12.1450 -1.2082
59 -12.1203 -1.0024
60 -12.0956 -0.7967
61 -12.0709 -0.5909
62 -12.0462 -0.3851
63 -12.0215 -0.1793
64 -11.9968 0.0264
65 -11.9721 0.2322
66 -11.9474 0.4380
67 -11.9228 0.6437
68 -11.8981 0.8495
69 -11.8734 1.0553
70 -11.8487 1.2610
71 -11.8240 1.4668
72 -11.7993 1.6726
73 -11.7746 1.8784
74 -11.7499 2.0841
75 -11.7252 2.2899
76 -11.7005 2.4957
% ∆ from −12V
www.national.com 14
12.0 Functional Description
(Continued)
Value Register V
IN
77 -11.6758 2.7014
78 -11.6511 2.9072
79 -11.6264 3.1130
80 -11.6018 3.3188
81 -11.5771 3.5245
82 -11.5524 3.7303
83 -11.5277 3.9361
84 -11.5030 4.1418
85 -11.4783 4.3476
86 -11.4536 4.5534
87 -11.4289 4.7591
88 -11.4042 4.9649
89 -11.3795 5.1707
90 -11.3548 5.3765
91 -11.3301 5.5822
92 -11.3054 5.7880
93 -11.2807 5.9938
94 -11.2561 6.1995
95 -11.2314 6.4053
96 -11.2067 6.6111
97 -11.1820 6.8168
98 -11.1573 7.0226
99 -11.1326 7.2284
100 -11.1079 7.4342
101 -11.0832 7.6399
102 -11.0585 7.8457
103 -11.0338 8.0515
104 -11.0091 8.2572
105 -10.9844 8.4630
106 -10.9597 8.6688
107 -10.9351 8.8745
108 -10.9104 9.0803
109 -10.8857 9.2861
110 -10.8610 9.4919
111 -10.8363 9.6976
112 -10.8116 9.9034
113 -10.7869 10.1092

12.7 DYNAMIC Vccp MONITORING USING VID

The AD_IN7 (CPU1 Vccp) and AD_IN8 (CPU2 Vccp) inputs are dynamically monitored using the P1_VIDx and P2_VIDx inputs to determine the limits. The dynamic comparisons operate independently of the static comparisons which use the statically programmed limits.
According to the VRM/VRD 10 specification when a VID signal is ramping to a new value, it steps by one LSB at a time, and one step occurs every 5 µs. In worse case, up to 20 steps may occur at once over 100 µs. The Vccp voltage from the VRD has to settle to the new value within 50 µs of the last VID change. The LM93 expects that the VID changes will not occur more frequently than every 5 µs.
% ∆ from −12V
The VID signal can be changed by the processor under program control, by internal thermal events or by external control, like force PROCHOT.
The reference voltages selected by each value of the 6 bit VID can be found in the VRM/VRD 10 spec. Transient VID values caused by line-to-line skew are ignored by the LM93. See the VRM/VRD 10 spec for the worst case line-to-line skew.
The LM93 averages the VID values over a sampling window to determine the average voltage that the VID input was indicating during the sampling window. At the completion of a voltage conversion cycle the LM93 performs limit compari­sons based on average VID values and not instantaneous values. The upper limit is determined by adding the upper limit offset to the average voltage indicated by VID. The lower limit is determined by subtracting the lower limit offset from average voltage indicated by VID. If the AD_IN7 (or AD_IN8) voltage falls outside the upper and lower limits, an error event is generated. Dynamic and static comparisons are performed once every 100 ms. The averaging time inter­val is 1.5 ms.
If at any time during the Vccp sampling window, the VID code indicates that the VRD should turn off its output, the dynamic Vccp checking is disabled for that sample.
±
The comparison accuracy is
25 mV, therefore the compari­son limits must be set to include this error. Since the Vccp voltage may be in the process of settling to a new value (due to a VID change), this settling should be taken into account when setting the upper and lower limit offsets.
The LM93 has a limitation on the upper limit voltage for dynamic Vccp checking. The upper limit cannot exceed
1.5875V. If the sum of the voltage indicated by VID and the upper offset voltage exceed 1.5875, the upper limit checking is disabled.
12.8 V
V
REF
a voltage reference input for the BMC A/D inputs. V
2.5V V
REF
OUTPUT
REF
is a fixed voltage to be used by an external VRD or as
±
1%. There is internal current limit protection for the
REF
output in case it gets shorted to supply or ground
accidentally.

12.9 PROCHOT BACKGROUND INFORMATION

PROCHOT is an output from a processor that indicates that the processor has reached a predetermined temperature trip point. At this trip point the processor can be programmed to lower its internal operating frequency and/or lower its supply voltage by changing the value of the 6 bit VID that it supplies to the VRD. The final VID setting and the rate at which it transitions to the new VID is programmable within the pro­cessor.
If PROCHOT is 100% throttled, it does not mean that the CPU is not executing, but it may mean that the CPU is about to encounter a thermal trip if the processor temperature continues to rise.
PROCHOT is also an input to some processors so that an external controller can force a thermal throttle based on external events.
PROCHOT is no longer asserted by the processor when the temperature drops below the predefined thermal trip point.
Oscillation around the trip point is avoided by the processor by requiring that the temperature be above/below the trip point for a predetermined period of time. A counter inside the processor is used to track this time and it has to be incre-
LM93
is
www.national.com15
12.0 Functional Description
LM93
(Continued)
mented to a max count for an above temperature trip and decremented to zero when below the trip temperature set­ting, to remove the trip.
The minimum time for PROCHOT assertion is time depen­dant on the FSB frequency. The minimum time that the processor asserts PROCHOT is estimated to be 187 µs.

12.10 PROCHOT MONITORING

PROCHOT monitoring applies to both the P1_PROCHOT and P2_PROCHOT inputs. Both inputs are monitored in the same fashion, but the following description discusses a single monitor. (Px_PROCHOT represents both P1_PROCHOT and P2_PROCHOT).
PROCHOT monitoring is meant to achieve two goals. One goal is to measure the percentage of time that PROCHOT is asserted over a programmable time period. The result of this measurement can be read from an 8-bit register where one LSB equals 1/256th of the PROCHOT Time Interval (0.39%). The second goal is to have a status register that indicates, as a coarse percentage, the amount of time a processor has been throttled. This second goal is required in order to communicate information over the NIC using ASF, i.e. status can be sent, not values.
To achieve the first goal, the PROCHOT input is monitored over a period of time as defined by the PROCHOT Time Interval Register. At the end of each time period, the 8-bit measurement is transferred to the Current Px_PROCHOT register. Also at the end of each measurement period, the Current Px_PROCHOT register value is moved to the Aver­age Px_PROCHOT register by adding the new value to the old value and dividing the result by 2. Note that the value that is averaged into the Average Px_PROCHOT register is not the new measurement but rather the previous measurement. If the SMBus writes to the Current P1_PROCHOT (or Cur­rent P2_PROCHOT) register, the capture cycle restarts for both monitoring channels (P1_PROCHOT and P2_PROCHOT). Also note, that a strict average of two 8-bit values may result in Average Px_PROCHOT reflecting a value that is one LSB lower than the Current Px_PROCHOT in steady state.
It should be noted that the 8-bit result has a positive bias of one half of an LSB. This is necessary because a value of 00h represents that Px_PROCHOT was not asserted at all dur­ing the sampling window. Any amount of throttling results in a reading of 01h.
The following table demonstrates the mapping for the 8-bit result:
8–Bit Result Percentage Thottled
0 Exactly 0%
1 Between 0% and 0.39%
2 Between 0.39% and 0.78%
AA
n Between (n-1)/256 and n/256
AA
253 Between 98.4% and 98.8%
254 Between 98.8% and 99.2%
255 Greater than 99.2%
To achieve the second goal, the LM93 has several compara­tors that compare the measured percentage reading against several fixed and 1 variable value. The variable value is user programmable.
The result of these comparisons generates several error status bits described in the following table:
Status Description Comparison Formula
100% Throttle PROCHOT was never
de-asserted during monitoring interval.
Greater than or equal to 75% and less than 100%
Greater than or equal to 50% and less than 75%
Greater than or equal to 25% and less than 50%
Greater than or equal to
12.5% and less than 25%
Greater than 0% and less than 12.5%
Greater than 0% 0
Greater than user limit user limit
These status bits are reflected in the PROCHOT Error Sta­tus Registers. Each of the P1_PROCHOT and P2_PROCHOT inputs is monitored independently, and each has its own set of status registers.
In S3 and S4/5 sleep states, the PROCHOT Monitoring function does not run. The Current Px_PROCHOT registers are reset to 00h and the Average Px_PROCHOT registers hold their current state. Once the sleep state changes back to S0, the monitoring function is restarted. After the first PROCHOT measurement has been made, the measure­ment is written directly into the Current and Average Px­_PROCHOT registers without performing any averaging. Av­eraging returns to normal on the second measurement.

12.11 PROCHOT OUTPUT CONTROL

In some cases, it is necessary for the LM93 to drive the Px_PROCHOT outputs low. There are several conditions that cause this to happen.
The LM93 can be told to logically short the two PROCHOT inputs together. When this is done, the LM93 monitors each of the Px_PROCHOT inputs. If any external device asserts one of the PROCHOT signals, the LM93 responds by assert­ing the other PROCHOT signal until the first PROCHOT signal is de-asserted. This feature should never be enabled if the PROCHOT signals are already being shorted by an­other means.
Whenever one of the VRDx_HOT inputs is asserted, the corresponding Px_PROCHOT pins are asserted by the LM93. The response time is less than 10 µs. When the VRDx_HOT input is de-asserted, the Px_PROCHOT pin is no longer asserted by the LM93. If the LM93 is configured to short the PROCHOT signals together, it always asserts them together whenever either of the VRDx_HOT inputs is as­serted.
Software can manually program the LM93 to drive a PWM type signal onto P1_PROCHOT or P2_PROCHOT. This is done via the PROCHOT Override register. See the descrip­tion of this register for more details. Once again, if the LM93
193 ≤ measured value and not 100%
129 ≤ measured value 193
65 ≤ measured value
33 ≤ measured value<65
0<measured value<33
<
measured value
<
measured
value
<
<
129
www.national.com 16
LM93
12.0 Functional Description
(Continued)
is configured to short the PROCHOT signals together, it always asserts them together whenever this function is en­abled.

12.12 FAN SPEED MEASUREMENT

The fan tach circuitry measures the period of the fan pulses by enabling a counter for two periods of the fan tach signal. The accumulated count is proportional to the fan tach period and inversely proportional to the fan speed. All four fan tach signals are measured within 1 second.
Fans in general do not over-speed if run from the correct voltage, so the failure condition of interest is under speed due to electrical or mechanical failure. For this reason only low-speed limits are programmed into the limit registers for the fans. It should be noted that, since fan period rather than speed is being measured, a fan tach error event occurs when the measurement exceeds the limit value.

12.13 SMART FAN SPEED MEASUREMENT

If a fan is driven using a low-side drive PWM, the tachometer output of the fan is corrupted. The LM93 includes smart tachometer circuitry that allows an accurate tachometer reading to be achieved despite the signal corruption. In smart tach mode all four signals are measured within 4 seconds.
A smart tach capture cycle works according to the following steps:
1. Both PWM outputs are synchronized such that they activate simultaneously.
2. Both PWM output active times are extended for up to 50 ms.
3. The number of tach signal periods during the 50 ms interval are tracked:
a) If less than 1 period is sensed during the 50 ms exten-
sion the result returned is 3FFh.
b) After one period occurs the count for that period is
memorized.
c) If during the 50 ms interval 2 periods do not occur, the
tach value reported is the 1 period count multiplied by
2.
d) If 2 periods do occur, the 2 period count is loaded into
the value register and the 50 ms PWM extension is terminated.
The lowest two bits in each of the Fan Tach value registers are reserved. The smart tach feature takes advantage of these bits. In normal tach mode, these bits return 00. In smart tach mode the two bits determine the accuracy level of the reading. 11 is most accurate (2 periods used) and 10 is the least accurate (1 period used). If less than 1 period occurred during the measurement cycle, the lower two bits are set to 10.
In smart fan tach mode, the TACH_EDGE field is honored in the LM93 Status/Control register. If only one edge type is active, the measurement always uses that edge type (rising or falling). If both are active, the measurement uses which­ever edge type occurs first.
Typically the minimum RPM captured by smart fan tach mode is 900 RPM for a fan that produces two pulses per revolution at about 50% duty cycle.

13.0 Inputs/Outputs

Besides all the pins associated with sensor inputs the LM93 has several pins that are assigned for other specific func­tions.

13.1 ALERT OUTPUT

The ALERT output is an active-low open drain output signal. The ALERT output is used to signal a micro-controller that one or more sensors have crossed their corresponding limit thresholds. This is generally not a fatal event unless the micro-controller decides it to be.
If enabled, the ALERT output is asserted whenever any bit in any BMC Error Status register is set (with the exception of the fixed PROCHOT threshold bits). By definition, when ALERT is enabled, it always matches the inverse of the BMC_ERR bit in the LM93 Status/Control register. When the ALERT output is disabled, an alert event can still be deter­mined by reading the state of the BMC_ERR bit.
The ALERT functions like an interrupt. The LM93 does not support the SMBus ARA (Alert Response Address) protocol.
ALERT is only de-asserted when there are no error status bits set in any BMC Error Status registers. Alternatively, software can disable the ALERT output to cause it to de­assert. The ALERT output re-asserts once enabled if any BMC Error Status register bits are still set.
Further information on how the ALERT output behaves can be found in Section 15.7 MASKING, ERROR STATUS AND ALERT.

13.2 RESET INPUT/OUTPUT

This pin acts as an active low reset output when power is applied to the LM93. It is asserted when the LM93 first sees a voltage that exceeds the internal POR level on its +3.3V S/B V their defaults when power is applied.
After this reset has completed, the RESET pin becomes an input. When an external device asserts RESET, the LM93 clears the LOCK bit in the LM93 Configuration register. This feature allows critical registers to be locked and provides a controlled mechanism to unlock them.
Asserting RESET externally causes the Sleep State Control register to be automatically set to S4/5. This causes several error events to be masked according to the S4/5 masking definitions. Refer to the register descriptions for more infor­mation.

13.3 PWM1 AND PWM2 OUTPUTS

The PWM outputs are used to control the speed of fans. The output signal duty cycle can automatically be controlled by the temperature of one or more temperature zones. It is also influenced by various other inputs and registers. See Section
15.10 FAN CONTROL for further information on the behavior of the PWM outputs.

13.4 SCSI_TERMx INPUTS

These inputs can be used to monitor the status of the electronic fuse on each of the SCSI channels. In prior imple­mentations the reference voltage out to the terminators was measured. When LVDS SCSI was introduced this reference voltage could take on multiple voltage levels depending on the mode of the SCSI bus. Also when the SCSI terminators were disabled, the V Monitoring individual terminators was also pin intensive. All
input. The internal registers of the LM93 are reset to
DD
voltage could not be guaranteed.
REF
www.national.com17
13.0 Inputs/Outputs (Continued)
LM93
of these issues caused problems that were difficult to work around so moving to monitoring the fuse was selected as the solution.
These inputs do not have to be used for monitoring SCSI fuses. Assertion of the SCSI_TERMx inputs to a Low sets the associated bits the status registers. Therefore, any active low signal could be connected to these pins to generate an error event.

13.5 VRD1_HOT AND VRD2_HOT INPUTS

These inputs monitor the thermal sensor associated with each processor VRD on a baseboard. When one of the inputs is activated, it indicates that the VRD has exceeded a predetermined temperature threshold. The LM93 responds by gradually increasing the duty cycle of any PWM outputs that are bound to the corresponding processor and setting the appropriate error status bits. The corresponding PROCHOT signal is also asserted. See the Section 15.10
FAN CONTROL and the Section 12.11 PROCHOT OUTPUT CONTROL for more information.

13.6 GPIO PINS

The LM93 has 8 GPIO pins than can act as either as inputs or outputs. Each can be configured and controlled indepen­dently. When acting as an input the pin can be masked to prevent it from setting a corresponding bit in the GPI Error status registers.

13.7 FAN TACH INPUTS

The fan inputs are Schmitt-Trigger digital inputs. Schmitt­trigger input circuitry is included to accommodate slow rise and fall times typical of fan tachometer outputs.
The maximum input signal range is 0V to +6.0V, even when
is less than 5V. In the event that these inputs are
V
DD
supplied from fan outputs, which exceed 0V to +6.0V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range, thereby preventing damage to the LM93.
Hot plugging fans can involve spikes on the Tach signals of up to 12V so diode protection or other circuitry is required. For “Hot Plug” fans, external clamp diodes may be required for signal conditioning.

14.0 SMBus Interface

The SMBus is used to communicate with the LM93. The LM93 provides the means to monitor power supplies for fan status and power failures. LM93 is designed to be tolerant to 5V signalling. Necessary pull-ups are located on the base­board. Care should be taken to ensure that only one pull-up is used for each SMBus signal. For proper operation, the SMBus slave addresses of all devices attached to the bus must comply with those listed in this document. The SMBus interface obeys the SMBus 2.0 protocols and signaling lev­els.
The SMBus interface of the LM93 does not load down the SMBus if no power is applied to the LM93. This allows a module containing the LM93 to be powered down and re­placed, if necessary.

14.1 SMBUS ADDRESSING

Each time the LM93 is powered up, it latches the assigned SMBus slave address (determined by ADDR_SEL) during the first valid SMBus transaction in which the first five bits of
the targeted slave address match those of the LM93 slave address. Once the address has been latched, the LM93 continues to use that address for all future transactions until power is lost.
The address select input detects three different voltage lev­els and allows for up to 3 devices to exist in a system. The address assignment is as follows:
Address Select Pin
(ADDR_SEL)
High 01011 01
V
/2 01011 10
DD
Low 01011 00

14.2 DIGITAL NOISE EFFECT ON SMBUS COMMUNICATION

Noise coupling into the digital lines (greater than 150mV), overshoot greater than V may prevent successful SMBus communication with the LM93. SMBus No Acknowledge (NACK) is the most com­mon symptom, causing unnecessary traffic on the bus. Al­though, the SMBus maximum frequency of communication is rather low (100 kHz max), care still needs to be taken to ensure proper termination within a system with multiple parts on the bus and long printed circuit board traces. The LM93 includes on chip low-pass filtering of the SMBCLK and SMB­DAT signals to make it more noise immune. Minimize noise coupling by keeping digital traces out of switching baseboard areas as well as ensuring that digital lines containing high speed data communications cross at right angles to the SMBDAT and SMBCLK lines.

14.3 GENERAL SMBUS TIMING

The SMBus 2.0 specification defines specific conditions for different types of read and write operations but in general the SMBus protocol operates as follows:
The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SMBDAT while the serial clock line SMBCLK re­mains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits. This consists of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data is written to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmit­ted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Ac­knowledge Bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master writes to the slave device. If the R/W bit is a 1 the master reads from the slave device.
Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge bit. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal.
If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction, such as
and undershoot less than GND,
DD
Slave Address
Assignment
www.national.com 18
14.0 SMBus Interface (Continued)
telling the slave device to expect a block write, or it may simply be a register address that tells the slave where sub­sequent data is to be written.
Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read opera­tion, it is necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read.
When all data bytes have been read or written, stop condi­tions are established. In WRITE mode, the master will allow the data line to go high during the 10th clock pulse to assert a STOP condition. In READ mode, the slave drives the data not the master. For the bit in question, the slave is looking for an acknowledge and the master doesn’t drive low. This is known as ‘No Acknowledge’. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.
Note, a repeated START may be given only between a write and read operation that are in succession.

14.4 SMBUS ERROR SAFETY FEATURES

To provide a more robust SMBus interface, the LM93 incor­porates a timeout feature for both SMBCLK and SMBDAT. If either signal is low for a long period of time (see SMBus AC specs), the LM93 SMBus state machine reverts to the idle state and waits for a START signal. Large block transfers of all zeros should be avoided if the SMBCLK is operating at a very low frequency to avoid accidental timeouts. Pulling the Reset pin low does not reset the SMBus state machine. If the LM93 SMBDAT pin is low during a system reset, the LM93’s state machine timeouts and resets automatically. If the LM93’s SMBDAT pin is high during a system reset, the first assertion of a start by the master resets the LM93’s interface state machine.
Although it is a violation of the SMBus specification, in some cases a START or STOP signal occurs in the middle of a byte transfer instead of coming after an acknowledge bit. If this occurs, only a partial byte was transferred. If a byte was being written, it is aborted and the partial byte is not com­mitted. If a byte was being read from a read-to-clear register, the register is not cleared.

14.5 SERIAL INTERFACE PROTOCOLS

The LM93 contains volatile registers, the registers occupy address locations from 00h to EFh.
Data can be read and written as a single byte, a word, or as a block of several bytes. The LM93 supports the following SMBus/I
2
C transactions/protocols: — Send Byte — Write Byte — Write Word — SMBus Write Block
2
—I
C Block Write — Read Byte — Read Word — SMBus Read Block — SMBus Block-Write Block-Read Process Call
2
C Block Read
—I
In addition to these transactions the LM93 supports a few extra items and also has some behavior that must be defined beyond the SMBus 2.0 specification. No other SMBus 2.0 transactions are supported (PEC, ARA etc.).
The SMBus specification defines several protocols for differ­ent types of read and write operations. The ones used in the LM93 are discussed below. The following abbreviations are used in the diagrams:
S — START P — STOP R — READ W — WRITE A — ACKNOWLEDGE /A — NO ACKNOWLEDGE

14.5.1 Address Incrementing

The established base address does not increment. Repeat­edly reading without re-establishing a new base address returns data from the same address each time. I
2
C read transactions can use this information and skip reestablishing the base address, when only one master is used. One exception to this rule exists when a block write and block read is used to emulate a block write/read process call. This is detailed later, see the Block Write/Read Process Call description.
LM93
www.national.com19
14.0 SMBus Interface (Continued)
LM93

14.5.2 Block Command Code Summary

Block command codes control the block read and write operations of the LM93 as summarized in the following table:
Command Code Name Value Description
Block Write Command F0h SMBus Block Write Command Code
Block Read Command F1h SMBus Block Write/Read Process Call
Fixed Block 0 F2h Fixed Block Read Command Code: address 40h, size 8 bytes
Fixed Block 1 F3h Fixed Block Read Command Code: address 48h, size 8 bytes
Fixed Block 2 F4h Fixed Block Read Command Code: address 50h, size 6 bytes
Fixed Block 3 F5h Fixed Block Read Command Code: address 56h, size 16 bytes
Fixed Block 4 F6h Fixed Block Read Command Code: address 67h, size 4 bytes
Fixed Block 5 F7h Fixed Block Read Command Code: address 6Eh, size 8 bytes
Fixed Block 6 F8h Fixed Block Read Command Code: address 78h, size 12 bytes
Fixed Block 7 F9h Fixed Block Read Command Code: address 90h, size 32 bytes
Fixed Block 8 FAh Fixed Block Read Command Code: address B4h, size 8 bytes
Fixed Block 9 FBh Fixed Block Read Command Code: address C8h, size 8 bytes
Fixed Block 10 FCh Fixed Block Read Command Code: address D00h, size 16 bytes
Fixed Block 11 FDh Fixed Block Read Command Code: address E5h, size 9 bytes

14.5.3 Write Operations

The LM93 supports the following SMBus write protocols.
14.5.3.1 Write Byte
In this operation the master device sends an address byte and one data byte to the slave device, as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a command code (register address).
5. The slave asserts ACK.
6. The master sends the data byte.
7. The slave asserts ACK.
8. The master asserts a STOP condition to end the transaction.
12 34 5678
S Slave
Address
W A Register
Address
A Data
Byte
AP
14.5.3.2 Write Word
In this operation the master device sends an address byte and two data bytes to the slave device, as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a command code (register address).
5. The slave asserts ACK.
6. The master sends the low data byte.
7. The slave asserts ACK.
8. The master sends the high data byte.
9. The slave asserts ACK.
10. The master asserts a STOP condition to end the transaction.
12 34 56 78 910
S Slave
Address
www.national.com 20
W A Register
Address
A Data Byte
Low
A Data Byte
High
AP
14.0 SMBus Interface (Continued)
14.5.3.3 SMBus Write Block to Any Address
The start address for a block write is embedded in this transaction. In this operation the master sends a block of data to the slave as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a command code that tells the slave device to expect a block write. The LM93 command code for a block write is F0h.
5. The slave asserts ACK.
6. The master sends a byte that tells the slave device how many data bytes it will send (N). The SMBus specification allows a maximum of 32 data bytes to be sent in a block write.
7. The slave asserts ACK.
8. The master sends data byte 1, the starting address of the block write.
9. The slave asserts ACK after each data byte.
10. The master sends data byte 2.
11. The slave asserts ACK.
12. The master continues to send data bytes and the slave asserts ACK for each byte.
13. The master asserts a STOP condition to end the transaction.
12 34 56 78 910 11A12 13
S Slave
Address
W A Command
F0h (Block Write)
A Byte
Count (N)
A Data
Byte 1 (Start Address)
A Data
Byte 2
A
A
Data Byte N
AP
LM93
Special Notes
1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM93 but are ignored.
2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.
3. The Byte Count field is ignored by the LM93. The master device may send more or less bytes and the LM93 accepts them.
4. The SMBus specification requires that block writes never exceed 32 data bytes. Meeting this requirement means that only 31 actual data bytes can be sent (the register address counts as one byte). The LM93 does not care if this requirement is met.
2
14.5.3.4 I
In this transaction the master sends a block of data to the LM93 as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends the starting address of the block write.
5. The slave asserts ACK after each data byte.
6. The master sends data byte 1.
7. The slave asserts ACK.
8. The master continues to send data bytes and the slave asserts ACK for each byte.
9. The master asserts a STOP condition to end the transaction
Special Notes:
1. Any attempts to write to bytes beyond normal address space are acknowledged by the LM93 but are ignored.
2. Block writes do not wrap from address FFh back to 00h the address remains at FFh.
C™Block Write
12 34 56 7 8 9
S Slave
Address
W A Register
Address
A Data
Byte 1
A
A
Data Byte N
AP
www.national.com21
14.0 SMBus Interface (Continued)
LM93

14.5.4 Read Operations

The LM93 uses the following SMBus read protocols.
14.5.4.1 Read Byte
In the LM93, the read byte protocol is used to read a single byte of data from a register. In this operation the master device receives a single byte from a slave device, as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a register address.
5. The slave asserts an ACK.
6. The master sends a Repeated START.
7. The master sends the slave address followed by the read bit (high).
8. The slave asserts an ACK.
9. The master receives a data byte and asserts a NACK.
10. The master asserts a STOP condition and the transaction ends.
12 34 567 89 10
S Slave
Address
14.5.4.2 Read Word
In the LM93, the read word protocol is used to read two bytes of data from a register or two consecutive registers. In this operation the master device reads two bytes from a slave device, as follows:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a register address.
5. The slave asserts an ACK.
6. The master sends a Repeated START.
7. The master sends the slave address followed by the read bit (high).
8. The slave asserts an ACK.
9. The master receives the Low data byte and asserts an ACK.
10. The master receives the High data byte and asserts a NACK.
11. The master asserts a STOP condition and the transaction ends.
12 34 567 89 10 11
S Slave
Address
W A Register
W A Register
Address
A S Slave
Address
A S Slave
Address
R A Data
Address
R A Data
Byte
Byte Low
A Data
Byte High
/A P
/A P
14.5.4.3 SMBus Block-Write Block-Read Process Call
This transaction is used to read a block of data from the LM93. Below is the sequence of events that occur in this transaction:
1. The master device asserts a START condition.
2. The master sends the 7-bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK.
4. The master sends a command code that tells the slave device to expect a block read (F1h) and the slave asserts ACK.
5. The master sends the Byte Count for this write which is 2 and the slave asserts ACK.
6. The master sends the Start Register Address for the block read and the slave asserts the ACK.
7. The master sends the Byte Count (1-32) for the block read processes call and the slave asserts ACK.
8. The master asserts a repeat START condition.
9. The master sends the 7-bit slave address followed by the read bit (high).
10. The slave asserts ACK.
11. The master receives a byte count data byte that tells it how many data bytes will received. This field reflects the number of bytes requested by the Byte Count transmitted to the LM93. The SMBus specification allows a maximum of 32 data bytes to be received in a block read. Then master asserts ACK.
www.national.com 22
14.0 SMBus Interface (Continued)
12. The master receives byte 1 and then asserts ACK.
13. The master receives byte 2 and then asserts ACK.
14. The master receives N-3 data bytes, and asserts ACK for each one.
15. The master receives data byte N and asserts a NACK.
16. The master asserts a STOP condition to end the transaction.
12345678910
S Slave
Address
Special Notes:
1. The LM93 returns 00h when address locations outside of normal address space are read.
2. Block reads do not wrap around from address FFh to 00h
3. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not acknowledge a byte.
4. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master to issue a STOP signal.
W A Block
Read Command Code (F1h)
11 12 13 14 15 15 16
A
Byte Count (1–20h) (N)
A Byte
A Data
Byte 1
Count (2h)
A Start
Register Address
A Data
Byte 2
A Byte
Count (1–20h) (N)
A
A S Slave
A
Data Byte N
Address
/A P
RA
A
LM93
www.national.com23
14.0 SMBus Interface (Continued)
LM93
14.5.4.4 Simulated SMBus Block-Write Block-Read Process Call
Alternatively, if the master cannot support an SMBus Block-Write Block-Read process call, it can be emulated by two transactions (a block write followed by a block read). This should only be done in a single master system, since in a dual master system collisions can occur that corrupt the data and transaction. Below is the sequence of events for these transactions:
1. The master issues a START to start this transaction.
2. The master sends the 7-bit slave address followed by a write bit (low).
3. The slave asserts the ACK.
4. The master sends the Block Read command code (F1h) and the slave asserts the ACK.
5. The master sends the Byte Count (2h) for this transaction and the slave asserts the ACK.
6. The master sends the Start Register Address and the slave asserts the ACK.
7. The master sends the Byte Count (1-20h) for the Block-Read Process Call and the slave asserts the ACK.
8. The master sends a STOP to end this transaction.
9. The master sends a START to start this transaction.
10. The master sends the 7-bit slave address followed by a write bit (low) and the slave asserts the ACK.
11. The master sends the Block Read Command code (F1h) and the slave asserts the ACK.
12. The master sends a repeat START.
13. The master sends the 7-bit slave address followed by a read bit (high) and the slave asserts the ACK.
14. The master receives Byte Count (this matches the size sent by the master in step 7) and asserts the ACK.
15. The master receives Data Byte 1 and asserts the ACK.
16. The master receives Data Byte 2 and asserts the ACK.
17. The master receives N-3 data bytes, and asserts ACK for each one.
18. The master receives the last data byte and asserts a NACK.
19. The master issues a STOP to end this transaction.
12345678910
S Slave
Address
W A Block
Read Command Code (F1h)
A Byte
Count (2h)
A Start
Register Address
A Byte
Count (1–20h) (N)
A P S Slave
Address
WA
A
11 12 13 14 15 16 17 16
A
Block Read Command Code (F1h)
Special Notes:
1. Steps 9 through 19 can be repeated to read another block of data. The address auto-increments such that the next block starts where the last block left off. The size returned by the LM93 is the same each time.
2. The LM93 returns 00h when address locations outside of normal address space are read.
3. Block reads do not wrap around from address FFh to 00h
4. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not acknowledge a byte.
5. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master to issue a STOP signal.
6. After a block read is finished, the base address of the LM93 is updated to point to the byte just beyond the last byte read.
14.5.4.5 SMBus Fixed Address Block Reads
Block reads can be performed from pre-defined addresses. A special command code has been reserved for each pre-defined address. See the Section 14.5.2 Block Command Code Summary for more details on the command codes. Below is the sequence of events that occur for this type of block read:
1. The master sends a START to start this transaction.
2. The master sends the 7-bit slave address followed by a write bit (low).
3. The slave asserts an ACK.
4. The master sends a Fixed Block Command Code (F2h-FDh) and the slave asserts an ACK.
A S Slave
Address
R A Byte
Count (1–20h) (N)
A Data
Byte 1
A Data
Byte 2
A
A
Data Byte N
/A P
www.national.com 24
14.0 SMBus Interface (Continued)
5. The master sends a repeated START.
6. The master sends the 7-bit slave address followed by a read bit (high).
7. The slave asserts an ACK.
8. The master receives the Byte Count (depends on the Fixed Block Command Code used) and asserts an ACK.
9. The master receives the first data byte and asserts an ACK.
10. The master continues to receive data bytes and asserting an ACK.
11. The master receives the last data byte.
12. The master asserts a NACK.
13. The master issues a STOP to end this transaction.
12 34 56 78 9 1011 1213
S Slave
Address
W A Fixed
Block Command
A S Slave
Address
R A Byte
Count (N)
A Data
Byte 1
Code (F2h–FDh)
Special Notes:
1. The LM93 returns 00h when address locations outside of normal address space are read.
2. Block reads do not wrap around from address FFh to 00h.
3. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not acknowledge a byte.
4. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master to issue a STOP signal.
2
14.5.4.6 I
The LM93 supports I
C Block Reads
2
C block reads. The following sequence of events occur in this transaction:
1. The master sends a START to start this transaction .
2. The master send 7-bit slave address followed by a write bit (low).
3. The slave asserts an ACK.
4. The master sends the register address and the slave asserts an ACK.
5. The master sends a repeated START.
6. The master sends the 7-bit slave address followed by a read bit (high).
7. The slave asserts an ACK.
8. The master receives Data Byte 1 and asserts an ACK.
9. The master continues to receive bytes and asserting an ACK for each byte received.
10. The master receives the last byte.
11. The master asserts a NACK.
12. The master issues a STOP.
12 34 56 78 9
S Slave
Address
W A Register
Address
A S Slave
Address
R A Data
Byte 1
A Data
Byte 2
A
A
Data
/A P
Byte N
A
10 11 12
A
A
Data
/A P
Byte N
LM93
Special Notes:
1. The LM93 returns 00h when address locations outside of normal address space are read.
2. Block reads do not wrap around from address FFh to 00h.
3. If the master acknowledges more bytes that it requested, the LM93 continues to supply data until the master does not acknowledge a byte.
4. If the master does not acknowledges a byte to prematurely abort a block read, the LM93 gets off the bus to allow the master to issue a STOP signal.

14.6 READING AND WRITING 16-BIT REGISTERS

Whenever the low byte of a 16-bit register is read, the high byte is frozen. After the high byte is read, it is unfrozen. This ensures that the entire 16-bit value is read properly and the high byte matches with the low byte. If the low byte of a different 16-bit register is read, the currently frozen high byte
is unfrozen and the high byte of the new 16-bit register is frozen. In a system with two SMBus masters, it is very important that only one master reads any 16-bit registers at a time. One possible method to achieve this would involve using 16-bit SMBus reads (instead of two separate 8-bit reads) to read 16-bit registers.
www.national.com25
14.0 SMBus Interface (Continued)
LM93
Whenever the low byte of a 16-bit register is written, the write is buffered and does not take effect until the corresponding high byte is written. If the low byte of a different 16-bit register is written, the previously buffered low byte of the first register is discarded. If a device attempts to write the high byte of a 16-bit register, and the corresponding low byte was not written (or was discarded), then the LM93 will NACK the byte.

15.0 Using The LM93

15.1 POWER ON

The LM93 generates a power on reset signal on RESET when power is applied for the first time to the part.

15.2 RESETS

Upon power up, the RESET output is asserted when the voltage on the power supply crosses the power-on-reset threshold level (see Electrical Specifications). The RESET output is open-drain and should be used with an external pull-up resistor connected to V has completed, the RESET pin becomes an input and when asserted causes the LOCK bit in the LM93 Configuration register to be cleared. In addition, assertion of RESET causes the sleep control register to be automatically set to S4/S5. This causes several error events to be masked ac­cording to the S4/S5 masking definitions.
Register Types
Factory regs x
. Once the power on reset
DD
Power
On Reset
External
Reset
Register Types
Power
On Reset
External
Reset
BMC Error Status regs x
Host Error Status regs x
Value regs
Limit regs x
Setup regs x
LM93 Configuration Lock Bit x x
LM93 Configuration GMSK Bit x (reset) x (set)
Sleep Mask x
Sleep State Control x
Other Mask regs x
All other registers are not effected by power on reset or external reset.

15.3 ADDRESS SELECTION

LM93 is designed to be used primarily in dual processor server systems that may require only one monitoring device.
If multiple LM93 devices are implemented in a system, they must have unique SMBus slave addresses. See the Section
14.1 SMBUS ADDRESSING for more information. The board designer may apply a 10 kΩ pull-down and/or
pull-up resistors to ground and/or to 3.3V SB V
DD
on the ADDR_SEL pin. The LM93 is designed to work with resistors of 5% tolerance for the case where two resistors are re­quired. Upon the first SMBus communication to the part, the LM93 assigns itself an SMBus address according to the ADDR_SEL input.
Address Select Board Implementation SMBus Address
less-than 10% of V
≈ V
/2 10 kΩ (5%) Resistor to 3.3V SB VDDand to Ground 0101,110b
DD
greater-than 90% of V
DD
DD
Pulled to ground through a 10 kΩ resistor 0101,100b
Pulled to 3.3V SB VDDthrough a 10 kΩ resistor 0101,101b

15.4 DEVICE SETUP

BIOS executes the following steps to configure the registers in the LM93. All steps may not be necessary if default values are acceptable.
Set limits and parameters (not necessarily in this order):
Set up Fan control Set up PWM temperature bindings Set fan tach limits Set fan boost temperature and hysteresis Set the VRD_HOT and PROCHOT PWM ramp control
Set voltage sensor limits and hysteresis Set the Dynamic Vccp offset limits Set the Sleep State control and mask registers Set Other Mask Registers (GPI Error, VRDx_HOT, SC-
SI_TERM, and dynamic Vccp limit checking) Set start bit to select user values and unmask error events Set the sleep state to 0 Set Lock bit to lock the limit and parameter registers
(optional)
rate Enable Smart Tach Mode and Tachometer Input to PWM
binding (required with direct PWM drive of fans) Set the temperature absolute limits Set the temperature hysteresis values Set temperature filtered or unfiltered usage Set the Zone Adjustment Offset temperature Set the PROCHOT override and time interval values

15.5 ROUND ROBIN VOLTAGE/TEMPERATURE CONVERSION CYCLE

The LM93 monitoring function is started as soon as the part is powered up. The LM93 performs a “round robin” sampling of the inputs, in the order shown below. Each cycle of the round robin is completed in less than 100 ms.
The results of the sampling and conversions can be found in the value registers and are available at any time.
Set the PROCHOT user limit Enable THERMTRIP masking of error events (if GPIO4
and GPIO5 are used as THERMTRIP inputs)
www.national.com 26
15.0 Using The LM93 (Continued)
Channel
#
1 Temp Zone 1 Remote Diode 1 Temp
2 Temp Zone 2 Remote Diode 2 Temp
3 Temp Zone 3 Internal Temperature
4 AIN1 +12V1
5 AIN2 +12V2
6 AIN3 +12V3
7 AIN4 FSB_Vtt
8 AIN5 3GIO/PXH/MCH_Core
9 AIN6 ICH_Core
10 AIN7 CPU_1Vccp
11 AIN8 CPU2_Vccp
12 AIN9 3.3V
13 AIN10 +5V
14 AIN11 SCSI_Core
15 AIN12 Mem_Core
16 AIN13 Mem_Vtt
17 AIN14 GBIT_Core
18 AIN15 −12V
19 AIN16 3.3V SB V

15.6 ERROR STATUS REGISTERS

The LM93 contains several error status registers for the BMC side, and duplicated error status registers for the Host side. These registers are used to reflect the state of all the possible error conditions that the LM93 monitors.
The BMC/Host Error Status registers hold a set bit until the event is cleared by software, even if the condition causing the error event goes away.
To clear a bit in the Error Status registers, a ‘1’ has to be written to the specific bit that is required to be cleared. If the event that caused the error is no longer active then the bit is cleared.
Clearing a bit in a BMC Error Status register does not clear the corresponding bit in the Host Error Status register or vise versa.

15.6.1 ASF Mode

In order for the LM93 part to act as a legacy sensor (6.1.2 of ASF spec DSP0114 rev 2) and to easily bolt up to the SMBus of an ASF capable NIC chip, the treatment of the Error Status registers needs to change.
The LM93 can be placed into ASF mode by setting the appropriate bit in the LM93 Status/Control register. Once this bit is set, the BMC Error Status registers become read-to­clear. Writing a ‘1’ to clear a particular bit is also allowed in ASF mode. The Host Error Status registers are not effected by ASF mode.
Input Typical Assignment
Reading
Reading
Reading
Supply Rail
DD
LM93

15.7 MASKING, ERROR STATUS AND ALERT

Masking is always applied to bits in the HOST and BMC Error Status registers. If an event is masked, the corre­sponding error bit in the HOST or BMC Error Status registers is prevented from ever being set. As a result, this prevents the event from ever causing ALERT to be asserted. Masking an event does not clear its associated Error Status bit if it is currently set.
Voltage errors are masked by writing a high voltage limit value of FFh. This is the default high limit for all voltages.
Temperature errors are masked by writing a high tempera­ture limit value of 80h. This is the default high limit for all temperatures. Masking a temperature channel masks both temperature errors and diode fault errors.
The GPI Mask register allows GPI errors to be masked. Any bits that are set in this register mask events for the corre­sponding GPIO_x pin.
User PROCHOT status is not really an error but it can be used to notify the user of processor throttling past a preset USER limit. A user limit of FFh acts as the mask for this register. Error bits associated with the predefined PROCHOT thresholds cannot be masked. It is important to note though, that these error bits do not cause BMC_ERR, HOST_ERR, or ALERT to be asserted under any condition.
Fan tach errors are masked if the tach limit for the given tach is set to FFh .
SCSI_TERMx errors and VRDx_HOT errors can be masked by setting the appropriate bit in the VRD THERMTRIP and SCSI_TERM Error Mask register.
When the LM93 powers up, the ALERT output is disabled. The ALERT output can be enabled by setting the ALERT_EN bit in the LM93 Configuration register.
In addition the manual masking options, the LM93 also masks some errors depending on the sleep state of the system. The sleep state of the system is communicated to the LM93 by writing to the Sleep State Control register. Some types of error events are always masked in certain sleep modes. Some types of error events are optionally masked in certain sleep modes if their sleep mask register bit is set. Refer to the register descriptions for more informa­tion.

15.8 LAYOUT AND GROUNDING

Analog components such as voltage dividers should be physically located as close as possible to the LM93.
The LM93 bypass capacitors, the parallel combination of 100 pF, 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors must be connected between power pin (pin 39) and ground, and should be located as close as possible to the LM93. The 100 pF capacitor should be placed closest to the power pin.

15.9 THERMAL DIODE APPLICATION

To measure temperature external to the LM93, we need to use a remote discrete diode to sense the temperature of external objects or ambient air. Remember that the tempera­ture of a discrete diode is effected, and often dominated, by the temperature of its leads.
Most silicon diodes do not lend themselves well to this application. It is recommended that a MMBT3904 transistor type base emitter junction be used with the collector tied to the base.
www.national.com27
15.0 Using The LM93 (Continued)
LM93
Thermal Diode Temperature vs. LM93 Temperature
Reading

15.9.1 Accuracy Effects of Diode Non-Ideality Factor

The technique used in today’s remote temperature sensors is to measure the change in V
at two different operating
BE
points of a diode. For a bias current ratio of N:1, this differ­ence is given as:
20068215

15.9.2 PCB Layout for Minimizing Noise

In the following guidelines, D+ and D− refer to the RE­MOTE1+, REMOTE1−, REMOTE2+, REMOTE2− pins.
In a noisy environment, such as a power supply, layout considerations are very critical. Noise induced on traces running between the remote temperature diode sensor and the LM93 can cause temperature conversion errors.
The following guidelines should be followed:
1. Place a 0.1 µF and 100 pF LM93 power bypass capaci-
tors as close as possible to the V
pin, with the 100pF
DD
capacitor being the closest. Place 10 µF capacitor in the near vicinity of the LM93 power pin.
2. Place 100 pF capacitor as close as possible to the LM93
thermal diode Remote+ and Remote− pins. Make sure the traces to the 100 pF capacitor are matched and as short as possible. This capacitor is required to minimize high frequency noise error.
3. Ideally, the LM93 should be placed within 10 cm of the
thermal diode pins with the traces being as straight, short and identical as possible. Trace resistance of 1Ω can cause as much as 1˚C of error.
4. Diode traces should be surrounded by a GND guard ring
to either side, above and below, if possible. This GND guard should not be between the Remote+ and Remote− lines. In the event that noise does couple to the diode lines, it would be ideal if it is coupled to both identically, i.e. common mode. That is, equally to the Remote+ (D+) and Remote−(D-) lines. (See figure be­low):
Recommended Diode Trace Layout
where:
- η is the non-ideality factor of the process the diode is manufactured on,
- q is the electron charge,
- k is the Boltzmann’s constant,
- N is the current ratio,
- T is the absolute temperature in ˚K.
The temperature sensor then measures ∆V
and converts
BE
to digital data. In this equation, k and q are well defined universal constants, and N is a parameter controlled by the temperature sensor. The only other parameter is η, which depends on the diode that is used for measurement. Since
is proportional to both η and T, the variations in η
∆V
BE
cannot be distinguished from variations in temperature. Since the non-ideality factor is not controlled by the tempera­ture sensor, it directly adds to the inaccuracy of the sensor.
±
For example, assume a
1% variation in η from part to part (Xeon processors targeted for the LM93 do not have pub­lished thermal diode specifications at the time of this printing, therefore this is probably a very conservative estimate). Assume a temperature sensor has an accuracy specification
±
3˚C at room temperature of 25˚C and the process used
of to manufacture the diode has a non-ideality variation of
±
1%. The resulting accuracy of the temperature sensor at
room temperature is:
±
TACC =
3˚C+(±1% of 298˚K) =±6˚C
The additional inaccuracy in the temperature measurement caused by η, can be eliminated if each temperature sensor is calibrated with the remote diode that it is paired with. The LM93 can be paired with an MMBT3904 when not being used to monitor the thermal diode within an Intel Processor.
20068220
5. Avoid routing diode traces in close proximity to any power supply switching or filtering inductors.
6. Avoid running diode traces close to or parallel to high speed digital and bus lines. Diode traces should be kept at least 2 cm apart from the high speed digital traces.
7. If it is necessary to cross high speed digital traces, the diode traces and the high speed digital traces should cross at a 90 degree angle.
8. Leakage current between Remote+ and GND should be kept to a minimum. 1 nA of leakage can cause as much as 1˚C of error in the diode temperature reading. Keep­ing the printed circuit board as clean as possible mini­mizes leakage current.

15.10 FAN CONTROL

15.10.1 Automatic Fan Control Algorithm

The LM93 fan speed control method is optimized for fan power efficiency, fan reliability and minimum cost. The PWMx outputs can be filtered using an external switching regulator type output stage that provides 5V to 12V DC for fan power. A high PWM frequency is required to minimize the
www.national.com 28
Loading...
+ 64 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use