Rainbow Electronics LM85 User Manual

LM85 Hardware Monitor with Integrated Fan Control

General Description

The LM85, hardware monitor, has a two wire digital interface compatible with SMBus 2.0. Using an 8-bit Σ∆ ADC, the LM85 measures:

– the temperature of two remote diode connected transis-

tors as well as its own die

– the V

nal scaling resistors). To set fan speed, the LM85 has three PWM outputs that are

each controlled by one of three temperature zones. The LM85 includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed. The LM85 has four tachometer inputs to measure fan speed. Limit and status registers for all measured values are included.

, 2.5V, 3.3VSBY, 5.0V, and 12V supplies (inter-

CCP

Features

n 2-wire, SMBus 2.0 compliant, serial digital interface n 8-bit Σ∆ ADC n Monitors V

motherboard/processor supplies

n Monitors 2 remote thermal diodes n Programmable autonomous fan control based on

temperature readings

, 2.5V, 3.3 VSBY, 5.0V, and 12V

CCP

n Noise filtering of temperature reading for fan control n 1.0˚C digital temperature sensor resolution n 3 PWM fan speed control outputs n 4 fan tachometer inputs n Monitors 5 VID control lines n 24-pin QSOP package n XOR-tree test mode

Key Specifications

n Voltage Measurement Accuracy n Resolution 8-bits, 1˚C n Temperature Sensor Accuracy n Temperature Range

— LM85 Operational 0˚C to +85˚C — Remote Temp Accuracy 0˚C to +125˚C

n Power Supply Voltage +3.0V to +3.6V n Power Supply Current 0.53 mA

Applications

n Desktop PC n Microprocessor based equipment

(e.g. Base-stations, Routers, ATMs, Point of Sales)

March 2003

2% FS (max)

3˚C (max)

LM85 Hardware Monitor with Integrated Fan Control

Block Diagram

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Connection Diagram

LM85

24 Pin QSOP

NS Package MQA24

Top View

LM85BIMQ or LM85CIMQ (55 units per rail), or

LM85BIMQX or LM85CIMQX (2500 units per tape and reel)

Information on the differences between the LM85BIMQ and LM85CIMQ can be found in Section 6.0. It is highly recommended that all new designs use the LM85BIMQ.

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Pin Descriptions

Symbol Pin Typ Name and Function/Connection

SMBus

VID Lines

Processor

Power

Inputs

Voltage

SMBDAT 1 Digital I/O

(Open-Drain)

SMBCLK 2 Digital Input System Management Bus Clock. Tied to Open-drain output. 5V

VID0 5 Digital Input Voltage identification signal from the processor. This value is read

VID1 6 Digital Input Voltage identification signal from the processor. This value is read

VID2 7 Digital Input Voltage identification signal from the processor. This value is read

VID3 8 Digital Input Voltage identification signal from the processor. This value is read

VID4 19 Digital Input Voltage identification signal from the processor. This value is read

3.3V 4 POWER +3.3V pin. Can be powered by +3.3V Standby power if monitoring

GND 3 GROUND Ground for all analog and digital circuitry.

5V 20 Analog Input Analog input for +5V monitoring.

12V 21 Analog Input Analog input for +12V monitoring.

2.5V 22 Analog Input Analog input for +2.5V monitoring.

CCP

23 Analog Input Analog input for +V

System Management Bus Data. Open-drain output. 5V tolerant, SMBus 2.0 compliant.

tolerant, SMBus 2.0 compliant.

in the VID0– VID4 Status Register.

in low power states is required. This pin also serves as the analog input to monitor the 3.3V supply. This pin should be bypassed with a 0.1µf capacitor in parallel with 100pf. A bulk capacitance of approximately 10µf needs to be in the near vicinity of the LM85.

(processor voltage) monitoring.

CCP

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Pin Descriptions (Continued)

Symbol Pin Typ Name and Function/Connection

Remote1+ 18 Remote Thermal

Remote1− 17 Remote Thermal

Remote

Fan

Inputs

Tachometer

Fan

Control

Remote2+ 16 Remote Thermal

Remote2− 15 Remote Thermal

TACH1 11 Digital Input Input for monitoring tachometer output of fan 1.

TACH2 12 Digital Input Input for monitoring tachometer output of fan 2.

TACH3 9 Digital Input Input for monitoring tachometer output of fan 3.

TACH4/Address

Select

PWM1/xTest

Out

PWM2 10 Digital Open-Drain

PWM3/Address

Enable

14 Digital Input Input for monitoring tachometer output of fan 4. If in Address

24 Digital Open-Drain

13 Digital Open-Drain

Diode Positive

Input

Diode Negative

Input

Diode Positive

Output

Diode Negative

Input

Output

LM85

Positive input (current source) from the first remote thermal diode. Serves as the positive input into the A/D. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor.

Negative input (current sink) from the first remote thermal diode. Serves as the negative input into the A/D. Connected to THERMDC pin of Pentium processor or the emmiter of a diode connected MMBT3904 NPN transistor.

Select Mode, determines the SMBus address of the LM85.

Fan speed control 1. When in XOR tree test mode, functions as XOR Tree output.

Fan speed control 2.

Fan speed control 3. Pull to ground at power on to enable Address Select Mode (Address Select pin controls SMBus address of the device).

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Absolute Maximum Ratings (Notes 1,

LM85

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

Machine Model 250V

Soldering Temperature, Infrared,

10 seconds (Note 6)

Storage Temperature −65˚C to +150˚C

Distributors for availability and specifications.

Supply Voltage, V+ −0.5V to 6.0V

Voltage on Any Digital Input or

−0.5V to 6.0V

Output Pin

Voltage on 12V Analog Input −0.5V to 16V

Voltage on 5V Analog Input −0.5V to 6.66V

Voltage on Remote1+, Remote2+, −0.5V to (V+ + 0.05V)

Current on Remote1−, Remote2−

1mA

Voltage on Other Analog Inputs −0.5V to 6.0V

Input Current on Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 5)

5mA

20 mA

ESD Susceptibility (Note 4)

Operating Ratings (Notes 1, 2)

LM85 Operating Temperature Range 0˚C ≤ T

Remote Diode Temperature Range 0˚C ≤ T

Supply Voltage (3.3V nominal) +3.0V to +3.6V

Voltage Range

+12V V

+5V V

+3.3V V

and All Other Inputs −0.05V to (V+ + 0.05V)

CCP

−0.05V to 6.66V

VID0–VID4 −0.05V to 5.5V

Typical Supply Current 0.53 mA

≤ +85˚C

≤ +125˚C

−0.05V to 16V

3.0V to 4.4V

Human Body Model 2500V

DC Electrical Characteristics

The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance RS=50Ω unless otherwise specified in conditions. Boldface limits apply for T

A=TMIN

to T

Symbol Parameter Conditions Typical

POWER SUPPLY CHARACTERISTICS

Supply Current (Note 9) Converting, Interface and

Power-On Reset Threshold Voltage 1.6 V (min)

TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS

Resolution 1

Temperature Accuracy (See (Note 10) for Thermal Diode Processor Type)

Temperature Accuracy using Internal Diode (Note

11)

External Diode Current Source High Level 188 280 µA (max)

External Diode Current Ratio 16

ANALOG TO DIGITAL CONVERTER CHARACTERISTICS

TUE Total Unadjusted Error(Note 12) LM85CIMQ -0.5/+3.5 %FS (max)

LM85BIMQ

DNL Differential Non-linearity 1 LSB

Power Supply Sensitivity

Total Monitoring Cycle Time (Note 13) All Voltage and

; all other limits TA= 25˚C.

MAX

Limits

(Note 7)

(Note 8)

1.8 3.5 mA (max)

Fans Inactive, Peak Current

Converting, Interface and

0.53 mA Fans Inactive, Average Current

2.8 V (max)

At 25˚C

0˚C to 100˚C

100˚C to 125˚C

0˚C to 85˚C

2.5 ˚C (max)

3 ˚C (max)

4 ˚C (max)

3 ˚C (max)

Low Level 11.75 µA

2 %FS

1 %/V

182 200 ms (max)

Temperature readings

235˚C

Units

(Limits)

˚C

Bits

(max)

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DC Electrical Characteristics (Continued)

The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance RS=50Ω unless otherwise specified in conditions. Boldface limits apply for T

A=TMIN

to T

Symbol Parameter Conditions Typical

Input Resistance, all analog inputs 210 140 kΩ (min)

DIGITAL OUTPUT: PWM1, PWM2, PWM3, XTESTOUT

Logic Low Sink Current LM85CIMQ VOL=0.55V 8 mA (min)

LM85BIMQ V

Logic Low Level LM85CIMQ I

LM85BIMQ I

SMBUS OPEN-DRAIN OUTPUT: SMBDAT

Logic Low Output Voltage I

High Level Output Current V

SMBUS INPUTS: SMBCLK. SMBDAT

HYST

Logic Input High Voltage 2.1 V (min)

Logic Input Low Voltage 0.8 V (max)

Logic Input Hysteresis Voltage 300 mV

DIGITAL INPUTS: ALL

Logic Input High Voltage 2.1 V (min)

Logic Input Low Voltage 0.8 V (max)

Logic Input Threshold Voltage 1.5 V

Logic High Input Current VIN= V+ 0.005 10 µA (max)

Logic Low Input Current VIN= GND −0.005 −10 µA (max)

Digital Input Capacitance 20 pF

; all other limits TA= 25˚C.

MAX

Limits

(Note 7)

(Note 8)

400 kΩ (max)

=0.4V 8 mA (min)

=+3mA 0.4 V (max)

OUT

=+8mA 0.55 V (max)

OUT

=+8mA 0.4 V (max)

OUT

=+4mA 0.4V V (max)

OUT

= V+ 0.1 10 µA (max)

OUT

LM85

Units

(Limits)

AC Electrical Characteristics

The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for T =T

to T

MIN

Symbol Parameter Conditions Typical

TACHOMETER ACCURACY

FAN PWM OUTPUT

SPIKE SMOOTHING FILTER

; all other limits TA= 25˚C.

MAX

Limits

(Note 7)

Fan Count Accuracy

(Note 8)

10 % (max)

(Limits)

Fan Full-Scale Count 65536 (max)

Fan Counter Clock Frequency 90 kHz

Fan Count Conversion Time 0.7 1.4 sec (max)

Frequency Setting Accuracy

10 % (max)

Frequency Range 10

Duty-Cycle Range 0to100 % (max)

Duty-Cycle Resolution (8-bits) 0.390625 %

Spin-Up Time Interval Range 100

4000

Spin-Up Time Interval Accuracy

Time Interval Deviation

10 % (max)

Time Interval Range 35

0.8

Units

Hz Hz

ms ms

sec sec

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AC Electrical Characteristics (Continued)

LM85

The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for T =T

to T

MIN

Symbol Parameter Conditions Typical

; all other limits TA= 25˚C.

MAX

(Note 7)

Limits

(Note 8)

SMBUS TIMING CHARACTERISTICS

SMB

SMBus Operating Frequency 10

100

BUF

SMBus Free Time Between Stop And

4.7 µs (min)

Start Condition

HD_STA

Hold Time After (Repeated) Start

4.0 µs (min)

Condition (after this period, the first clock is generated)

SU:STA

SU:STO

HD:DAT

Repeated Start Condition Setup Time 4.7 µs (min)

Stop Condition Setup Time 4.0 µs (min)

Data Output Hold Time 300 ns (min)

930 ns (max)

SU:DAT

TIMEOUT

LOW

HIGH

Data Input Setup Time 250 ns (min)

Data And Clock Low Time To Reset Of SMBus Interface Logic(Note 14)

25 35

Clock Low Period 4.7 µs (min)

Clock High Period 4.0

POR

Clock/Data Fall Time 300 ns (max)

Clock/Data Rise Time 1000 ns (max)

Time from Power-On-Reset to LM85

V+>2.8V 500 ms (max)

Reset and Operational

Units

(Limits)

kHz (min)

kHz (max)

ms (min)

ms (max)

µs (min)

µs (max)

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise noted.

Note 3: When the input voltage (V

maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four.

Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Machine model, 200pF discharged directly into each pin.

Note 5: Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 125˚C/W.

Note 6: See the URL ”http://www.national.com/packaging/“ for other recommendations and methods of soldering surface mount devices.

Note 7: Typicals are at T

Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 9: The average current can be calculated from the peak current using the following equation:

Quiescent current will not increase substantially with an SMBus transaction.

Note 10: The accuracy of the LM85CIMQAis guaranteed when using the thermal diode of Intel Pentium 4 processors in 423 pin or 478 pin packages or any thermal diode with a typical non-ideality factor of 1.0045. The accuracy of the LM85BIMQA is guaranteed when using the thermal diode of an Intel Pentium 4 processors or any thermal diode with a typical non-ideality of 1.0021 and series resistance of 3.64Ω or 3.86Ω. When using a 2N3904 type transistor as a thermal diode the error band will be typically shifted by -1˚C.

Note 11: Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power dissipation of the LM85 and the thermal resistance. See (Note 5) for the thermal resistance to be used in the self-heating calculation.

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) at any pin exceeds the power supplies (V

= 25˚C and represent most likely parametric norm.

GND or V

V+ ), the current at that pin should be limited to 5mA. The 20mA

Note 12: TUE , total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the "actual Vin" to achieve a given code transition minus the "theoretical Vin" for the same code. Therefore, a positive error indicates that the input voltage is greater than the theoretical input voltage for a given code. If the theoretical input voltage was applied to an LM85 that has positive error, the LM85’s reading would be less than the theoretical.

Note 13: This specification is provided only to indicate how often temperature and voltage data is updated. The LM85 can be read at any time without regard to conversion state (and will yield last conversion result).

Note 14: Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t SMBDAT pin to a high impedance state.

will reset the LM85’s SMBus state machine, therefore setting the

TIMEOUT

Functional Description

1.0 SMBUS

The LM85 is compatible with devices that are compliant to the SMBus 2.0 specification. More information on this bus can be found at: http://www.smbus.org/. Compatibility of SMBus2.0 to other buses is discuss in the SMBus 2.0 specification.

1.1 Addressing

LM85 is designed to be used primarily in desktop systems that require only one monitoring device. If only one LM85 is used on the motherboard, the designer should be sure that the Address Enable/PWM3 pin is High during the

first SMBus communication addressing the LM85. Address Enable/PWM3 is an open drain I/O pin that at power-on defaults to the input state. A maximum of 10k pull-up resistance is required to assure that the SMBus address of the device will be locked at 010 1110b, which is the default address of the LM85.

During the first SMBus communication TACH4 and PWM3 can be used to change the SMBus address of the LM85. to 0101101b or 0101100b. LM85 address selection procedure:

A10kΩ pull-down resistor to ground on the Address Enable/PWM3 pin is required. Upon power up, the LM85 will be placed into Address Enable mode and assign itself an SMBus address according to the state of the Address Select input. The LM85 will latch the address during the first valid SMBus transaction in which the first five bits of the targeted address match those of the LM85 address, 0 1011b. This feature eliminates the possibility of a glitch on the SMBus interfering with address selection. When the PWM3/Address Enable pin is not used to change the SMBus address of the LM85, it will remain in a high state until the first communication with the LM85. After the first SMBus transaction is completed PWM3 and TACH4 will return to normal operation.

Address Enable Address Select Board Implementation SMBus Address

0 0 Pulled to ground through a 10 kΩ resistor 010 1100b, 2Ch

0 1 Pulled to 3.3V or ground through a 10 kΩ resistor 010 1101b, 2Dh

1 X Pulled to 3.3V through a 10kΩ resistor 010 1110b, 2Eh

LM85

In this way, up to three LM85 devices can exists on an SMBus at any time. Multiple LM85 devices can be used to monitor additional processors and temperature zones.

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2.0 FAN REGISTER DEVICE SET-UP

The BIOS will follow the following steps to configure the fan registers on the LM85. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the fan limit and parameter registers during configuration, the LM85 will continue to operate based on default values until the START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the LM85 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (adress 5Ch through 6Eh).

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Functional Description (Continued)

LM85

1. Set limits and parameters (not necessarily in this order): – [5F-61h] Set PWM frequencies and auto fan control range. – [62-63h] Set spike smoothing and min/off. – [5C-5Eh] Set the fan spin-up delays. – [5C-5Eh] Match each fan with a corresponding thermal zone. – [67-69h] Set the fan temperature limits. – [6A-6Ch] Set the temperature absolute limits. – [64-66h] Set the PWM minimum duty cycle. – [6D-6Eh] Set the temperature Hysteresis values.

2. [40h] Set bit 0 (START) to update fan control and limit register values and start fan control based on these new values.

3. [40h] Set bit 1 (LOCK) to lock the fan limit and parameter registers (optional).

3.0 AUTO FAN CONTROL OPERATING MODE

The LM85 includes the circuitry for automatic fan control. In Auto Fan Mode, the LM85 will automatically adjust the PWM duty cycle of the PWM outputs. PWM outputs are assigned to a thermal zone based on the fan configuration registers. It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, the temperature of a zone exceeds its absolute limit, all PWM outputs will go to 100% duty cycle to provide maximum cooling to the system.

4.0 REGISTER SET

Read/ Write

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default

Value

20h R 2.5V 7 6 5 4 3 2 1 0 N/A

21h R V

CCP

7 6 5 4 3 2 1 0 N/A

22h R 3.3V 7 6 5 4 3 2 1 0 N/A

23h R 5V 7 6 5 4 3 2 1 0 N/A

24h R 12V 7 6 5 4 3 2 1 0 N/A

25h R Processor (Zone1) Temp 7 6 5 4 3 2 1 0 N/A

26h R Internal (Zone2) Temp 7 6 5 4 3 2 1 0 N/A

27h R Remote (Zone3) Temp 7 6 5 4 3 2 1 0 N/A

28h R Tach1 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A

29h R Tach1 MSB 15 14 13 12 11 10 9 8 N/A

2Ah R Tach2 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A

2Bh R Tach2 MSB 15 14 13 12 11 10 9 8 N/A

2Ch R Tach3 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A

2Dh R Tach3 MSB 15 14 13 12 11 10 9 8 N/A

2Eh R Tach4 LSB 7 6 5 4 3 2 LEVEL1 LEVEL0 N/A

2Fh R Tach4 MSB 15 14 13 12 11 10 9 8 N/A

30h R/W Fan1 Current PWM Duty 7 6 5 4 3 2 1 0 N/A

31h R/W Fan2 Current PWM Duty 7 6 5 4 3 2 1 0 N/A

32h R/W Fan3 Current PWM Duty 7 6 5 4 3 2 1 0 N/A

3Eh R Company ID 7 6 5 4 3 2 1 0 01h

3Fh R Version/Stepping VER3 VER2 VER1 VER0 STP3 STP2 STP1 STP0 60h

40h R/W Ready/Lock/Start/Override RES RES RES RES OVRID READY LOCK START 00h

41h R Interrupt Status Register 1 ERR ZN3 ZN2 ZN1 5V 3.3V V

CCP

2.5V 00h

42h R Interrupt Status Register 2 ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 RES 12V 00h

43h R VID0–4 RES RES RES VID4 VID3 VID2 VID1 VID0 N/A

44h R/W 2.5V Low Limit 7 6 5 4 3 2 1 0 00h

45h R/W 2.5V High Limit 7 6 5 4 3 2 1 0 FFh

46h R/W V

47h R/W V

Low Limit 7 6 5 4 3 2 1 0 00h

CCP

High Limit 7 6 5 4 3 2 1 0 FFh

CCP

48h R/W 3.3V Low Limit 7 6 5 4 3 2 1 0 00h

Lock?

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Functional Description (Continued)

LM85

49h R/W 3.3V High Limit 7 6 5 4 3 2 1 0 FFh

4Ah R/W 5V Low Limit 7 6 5 4 3 2 1 0 00h

4Bh R/W 5V High Limit 7 6 5 4 3 2 1 0 FFh

4Ch R/W 12V Low Limit 7 6 5 4 3 2 1 0 00h

4Dh R/W 12V High Limit 7 6 5 4 3 2 1 0 FFh

4Eh R/W Processor (Zone1) Low

4Fh R/W Processor (Zone1) High

50h R/W Internal (Zone2) Low

51h R/W Internal (Zone2) High

52h R/W Remote (Zone3) Low

53h R/W Remote (Zone3) High

54h R/W Tach1 Minimum LSB 7 6 5 4 3 2 1 0 FFh

55h R/W Tach1 Minimum MSB 15 14 13 12 11 10 9 8 FFh

56h R/W Tach2 Minimum LSB 7 6 5 4 3 2 1 0 FFh

57h R/W Tach2 Minimum MSB 15 14 13 12 11 10 9 8 FFh

58h R/W Tach3 Minimum LSB 7 6 5 4 3 2 1 0 FFh

59h R/W Tach3 Minimum MSB 15 14 13 12 11 10 9 8 FFh

5Ah R/W Tach4 Minimum LSB 7 6 5 4 3 2 1 0 FFh

5Bh R/W Tach4 Minimum MSB 15 14 13 12 11 10 9 8 FFh

5Ch R/W Fan1 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

5Dh R/W Fan2 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

5Eh R/W Fan3 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

5Fh R/W Fan1 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U

60h R/W Fan2 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U

61h R/W Fan3 Range/Frequency RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U

62h R/W Min/Off, Zone1 Spike

63h R/W Zone2, Zone3 Spike

64h R/W Fan1 PWM Minimum 7 6 5 4 3 2 1 0 80h U

65h R/W Fan2 PWM Minimum 7 6 5 4 3 2 1 0 80h U

66h R/W Fan3 PWM Minimum 7 6 5 4 3 2 1 0 80h U

67h R/W Zone1 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U

68h R/W Zone2 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U

69h R/W Zone3 Fan Temp Limit 7 6 5 4 3 2 1 0 5Ah U

6Ah R/W Zone1 Temp Absolute

6Bh R/W Zone2 Temp Absolute

6Ch R/W Zone3 Temp Absolute

6Dh R/W Zone1, Zone2 Hysteresis H1-3 H1-2 H1-1 H1-0 H2-3 H2-2 H2-1 H2-0 44h U

6Eh R/W Zone3 Hysteresis H3-3 H3-2 H3-1 H3-0 RES RES RES RES 40h U

Read/ Write

Temp

Smoothing

Limit

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(MSB)

7 6 5 4 3 2 1 0 81h

7 6 5 4 3 2 1 0 7Fh

7 6 5 4 3 2 1 0 81h

7 6 5 4 3 2 1 0 7Fh

7 6 5 4 3 2 1 0 81h

7 6 5 4 3 2 1 0 7Fh

OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00H U

ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E ZN3-2 ZN3-1 ZN3-0 00h U

7 6 5 4 3 2 1 0 64h U

(LSB)

Default

Value

Lock?

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Functional Description (Continued)

LM85

Read/ Write

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default

Value

6Fh R/W XOR Test Tree Enable RES RES RES RES RES RES RES XEN 00h U

74h R/W Tach Monitor Mode RES RES T3/4-1 T3/4-0 T2-1 T2-0 T1-1 T1-0 00h

75h R/W Fan Spin-up Mode RES RES RES RES RES PWM3SUPWM2SUPWM1SU7h U

Note: Reserved bits will always return 0 when read.

4.1 Register 20-24h: Voltage Reading

Lock?

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

20h R 2.5V 7 6543210 N/A

21h R V

CCP

7 6543210 N/A

22h R 3.3V 7 6543210 N/A

23h R 5V 7 6543210 N/A

24h R 12V 7 6543210 N/A

The Register Names difine the typical input voltage at which the reading is

⁄4full scale or C0h.

The Voltage Reading registers are updated automatically by the LM85 at a minimum frequency of 4 Hz. These registers are read only — a write to these registers has no effect.

4.2 Register 25-27h: Temperature Reading

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

25h R Processor (Zone1) Temp 7 6543210 N/A

26h R Internal (Zone2) Temp 7 6543210 N/A

27h R Remote (Zone3) Temp 7 6543210 N/A

The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Processor (Zone1) Temp register reports the temperature measured by the thermal diode connected to the Remote1− and Remote1+ pins, Remote (Zone3) Temp register reports the temperature measured by the thermal diode connected to the the Remote2− and Remote2+ pins, and the Internal (Zone2) Temp register reports the temperature measured by the internal (junction) temperature sensor. Temperatures are represented as 8 bit, 2’s complement, signed numbers, in Celsius, as shown below in Table 1. The Temperature Reading register will return a value of 80h if the remote diode pins are not used by the board designer or are not functioning properly. This reading will cause the zone limit bit(s) (bits 6 and 4) in the Interrupt Status Register (41h) and the remote diode fault status bit(s) (bit 6 or 7) in the Interrupt Status Register 2 (42h) to be set. The Temperature Reading registers are updated automatically by the LM85 at a minimum frequency of 4 Hz. These registers are read only — a write to these registers has no effect.

TABLE 1. Temperature vs Register Reading

Temperature Reading (Dec) Reading (Hex)

−127˚C −127 81h

. . .

−50˚C −50 CEh

. . .

0˚C 0 00h

. . .

127˚C 127 7Fh

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. . .

Functional Description (Continued)

TABLE 1. Temperature vs Register Reading (Continued)

Temperature Reading (Dec) Reading (Hex)

(SENSOR ERROR) 80h

4.3 Register 28-2Fh: Fan Tachometer Reading

LM85

28h 29h

2Ah 2Bh

2Ch 2Dh

2Eh 2Fh

The Fan Tachometer Reading registers contain the number of 11.111 µs periods (90 kHz) between full fan revolutions. The results are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full revolution. These registers will be updated at least once every second.

The value, for each fan, is represented by a 16-bit unsigned number. The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled

or non-functional. The least two significant bits (LEVEL1 and LEVEL2) of the least significant byte are used to indicate the accuracy level of the

tachometer reading. The accuracy ranges from most to least accurate. [LEVEL1:LEVEL2]=11indicates a most accurate value, [LEVEL1:LEVEL2]=01 indicates the least accurate value and [LEVEL1:LEVEL2]=00 is reserved for future use.

FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. These registers are read only — a write to these registers has no effect.

When the least significant byte (LSByte) of the LM85C 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. This is required to ensure a valid reading. The LM85C will update the Fan Tachometer Reading registers at the start of an LSByte read. Therefore, reading the MSByte register twice in a row will yield the same data.

When the LSByte of the LM85B 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated.

During spin-up, the PWM duty cycle reported is 0%.

Read/ Write

R R

Tach1 LSB Tach1 MSB715

Tach2 LSB Tach2 MSB715

Tach3 LSB Tach3 MSB715

Tach4 LSB Tach4 MSB715

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

6 14

5 13

4 12

3 11

2 10

LEVEL19LEVEL08N/A

Default Value

N/A

4.4 Register 30-32h: Current PWM Duty

30h R/W Fan1 Current PWM Duty 7 6543210 N/A

31h R/W Fan2 Current PWM Duty 7 6543210 N/A

32h R/W Fan3 Current PWM Duty 7 6543210 N/A

The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this register and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section.

When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read only unless the fan is in manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan. The PWM duty cycle is represented as shown in the following table.

Read/ Write

Bit 7 (MSB)

Current Duty Value (Decimal) Value (Hex)

0% 0 00h

0.3922% 1 01h

. . .

25.098% 64 40h

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

. . .

(LSB)

Default Value

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Functional Description (Continued)

LM85

Current Duty Value (Decimal) Value (Hex)

4.5 Register 3Eh: Company ID

. . .

50.196% 128 80h

. . .

100% 255 FFh

. . .

3Eh R Company ID 7 6543210 01h

The company ID register contains the company identification number. For National Semiconductor this is 01h. This number is assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read only — a write to this register has no effect.

4.6 Register 3Fh: Version/Stepping

3Fh R Version/Stepping VER3 VER2 VER1 VER0 STP3 STP2 STP1 STP0 60h

The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM85 silicon. The four most significant bits [7.4] reflect the LM85 base device number when set to a value of 0110b. All LM85 revisions will have a base number of 6. For the LM85C, this register will read 01100000b (60h). The LM85B will read 01100010b (62h).If new revisions of the LM85C or LM85B are released the last 4 bits of this register will change.

The register is used by application software to identify which device in the hardware monitor family of ASICs has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping.

This register is read only — a write to this register has no effect.

4.7 Register 40h: Ready/Lock/Start/Override

40h R/W Ready/Lock/Start/Override RES RES RES RES OVRID READY LOCK START 00h

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Bit Name R/W Default Description

0 START R/W 0 When software writesa1tothis bit, the LM85 fan monitoring and PWM output

control functions will use the values set in the fan control limit and parameter registers (address 5Ch through 6Eh). Before this bit is set, the LM85 will not update the used register values, the default values will remain in effect. Whenever this bit is set to 0, the LM85 fan monitoring and PWM output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (5C through 6Eh). The LM85 will preserve the values currently stored in the limit and parameter registers when this bit is set or cleared. This bit becomes read only when the Ready/Lock/Start/Override register Lock bit is set. It is expected that all limit and parameter registers will be set by BIOS or application software prior to setting this bit.

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Functional Description (Continued)

Bit Name R/W Default Description

1 LOCK R/W 0 Setting this bit to 1 locks specified limit and parameter registers. Once this bit

is set, limit and parameter registers become read only and will remain locked until the device is powered off. This register bit becomes read only once it is set.

2 READY R 0 The LM85 sets this bit automatically after the part is fully powered up, has

completed the power-up-reset process, and after all A/D converters are properly functioning.

3 OVRID R/W If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of

whether or not the lock bit is set. For the LM85C only, when a PWM is programmed in the disabled mode (Fan Configuration registers 5C-5Eh, bits fan_config[7:5] = ZON[2:0]=100) the PWM stays in the disabled mode for this case. Override bit works in all other cases (zone1-3, hottest ...). For the LM85B the OVRID bit has precedence over the disabled mode. Therefore, when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode.

4–7 Reserved R 0 Reserved

4.8 Register 41h: Interrupt Status Register 1

LM85

41h R Interrupt Status 1 ERR ZN3 ZN2 ZN1 5V 3.3V V

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

2.5V 00h

CCP

Default Value

The Interrupt Status Register 1 bits will be automatically set, by the LM85, whenever a fault condition is detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers. ZN3 and ZN1 bits will be set when a diode fault condition, such as a disconect or short, is detected. More than one fault may be indicated in the interrupt register when read. This register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM85 after it is read by software, if the fault condition is no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists

This register is read only — a write to this register has no effect.

Bit Name R/W Default Description

0 2.5V_Error R 0 The LM85 automatically sets this bit to 1 when the 2.5V input voltage is

less than or equal to the limit set in the 2.5V Low Limit register or greater than the limit set in the 2.5V High Limit register.

_Error R 0 The LM85 automatically sets this bit to 1 when the V

CCP

less than or equal to the limit set in the V than the limit set in the V

High Limit register.

CCP

Low Limit register or greater

CCP

input voltage is

CCP

2 3.3V_Error R 0 The LM85 automatically sets this bit to 1 when the 3.3V input voltage is

less than or equal to the limit set in the 3.3V Low Limit register or greater than the limit set in the 3.3V High Limit register.

3 5V_Error R 0 The LM85 automatically sets this bit to 1 when the 5V input voltage is less

than or equal to the limit set in the 5V Low Limit register or greater than the limit set in the 5V High Limit register.

4 Zone 1 Limit

Exceeded

R 0 The LM85 automatically sets this bit to 1 when the temperature input

measured by the Remote1− and Remote1+ inputs is less than or equal to the limit set in the Processor (Zone1) Low Temp register or more than the limit set in the Processor (Zone1) High Temp register. This bit will be set when a diode fault is detected.

5 Zone 2 Limit

Exceeded

R 0 The LM85 automatically sets this bit to 1 when the temperature input

measured by the internal temperature sensor is less than or equal to the limit set in the Internal (Zone2) Low Temp register or greater than the limit set in the Internal (Zone2) High Temp register.

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Functional Description (Continued)

LM85

Bit Name R/W Default Description

6 Zone 3 Limit

Exceeded

R 0 The LM85 automatically sets this bit to 1 when the temperature input

measured by the Remote2− and Remote2+ inputs is less than or equal to the limit set in the Internal (Zone2) Low Temp register or greater than the limit set in the Remote (Zone3) High Temp register. This bit will be set when a diode fault is detected.

7 Error in Status

R 0 If there is a set bit in Status Register 2, this bit will be set to 1.

4.9 Register 42h: Interrupt Status Register 2

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

42h R Interrupt Status Register 2 ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 RES 12V 00h

The Interrupt Status Register 2 bits will be automatically set, by the LM85, whenever a fault condition is detected. Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed droping below minimum set by the tachometer minimum register, the 12V input voltage going outside the window set by its limit registers. Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM85 after it is ready by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no longer exists

This register is read only — a write to this register has no effect.

Bit Name R/W Default Description

0 +12V_Error R 0 The LM85 automatically sets this bit to 1 when the 12V input voltage either

falls below the limit set in the 12V Low Limit register or exceeds the limit set in the 12V High Limit register.

1 Reserved R 0 Reserved

2 Fan1 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH1 input reading is

above the value set in the Tach1 Minimum MSB and LSB registers.

3 Fan2 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH2 input reading is

above the value set in the Tach2 Minimum MSB and LSB registers.

4 Fan3 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH3 input reading is

above the value set in the Tach3 Minimum MSB and LSB registers.

5 Fan4 Stalled R 0 The LM85 automatically sets this bit to 1 when the TACH4 input reading is

above the value set in the Tach4 Minimum MSB and LSB registers.

6 Remote Diode

1 Fault

R 0 The LM85 automatically sets this bit to 1 when there is either a short or

open circuit fault on the Remote1+ or Remote1− thermal diode input pins. A diode fault will also set bit 4, Diode 1 Zone Limit bit, of Interrupt Status Register 1.

7 Remote Diode

2 Fault

R 0 The LM85 automatically sets this bit to 1 when there is either a short or

open circuit fault on the Remote2+ or Remote2− thermal diode input pins. A diode fault will also set bit 6, Diode 2 Zone Limit bit, of Interrupt Status Register 1.

4.10 Register 43h: VID

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

43h R VID0–4 RES RES RES VID4 VID3 VID2 VID1 VID0

The VID register contains the values of LM85 VID0–VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct values to place in the V

Low Limit and V

CCP

High Limit registers.

CCP

This register is read only — a write to this register has no effect.

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Default Value

Functional Description (Continued)

4.11 Registers 44-4Dh: Voltage Limit Registers

LM85

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

44h R/W 2.5V Low Limit 7 6543210 00h

45h R/W 2.5V High Limit 7 6543210 FFh

46h R/W V

47h R/W V

Low Limit 7 6543210 00h

CCP

High Limit 7 6543210 FFh

CCP

48h R/W 3.3V Low Limit 7 6543210 00h

49h R/W 3.3V High Limit 7 6543210 FFh

4Ah R/W 5V Low Limit 7 6543210 00h

4Bh R/W 5V High Limit 7 6543210 FFh

4Ch R/W 12V Low Limit 7 6543210 00h

4Dh R/W 12V High Limit 7 6543210 FFh

If a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the voltage low limit register, the corresponding bit will be set automatically by the LM85 in the interrupt status registers (41-42h). Voltages are presented in the registers at

⁄4full scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as

shown in Table 2. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.

TABLE 2. Voltage Limits vs Register Setting

Input Nominal

Voltage

Maximum Voltage

Minimum Voltage

2.5V 2.5V C0h 3.32V FFh 0V 00h

CCP

2.25V C0h 3.00V FFh 0V 00h

3.3V 3.3V C0h 4.38V FFh 3.0V AFh

5V 5.0V C0h 6.64V FFh 0V 00h

12V 12.0V C0h 16.00V FFh 0V 00h

4.12 Registers 4E-53h: Temperature Limit Registers

4Eh R/W Processor (Zone1)

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

7 6543210 81h

Low Temp

4Fh R/W Processor (Zone1)

7 6543210 7Fh

High Temp

50h R/W Processor (Zone2)

7 6543210 81h

Low Temp

51h R/W Processor (Zone2)

7 6543210 7Fh

High Temp

52h R/W Processor (Zone3)

7 6543210 81h

Low Temp

53h R/W Processor (Zone3)

7 6543210 7Fh

High Temp

If an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automatically by the LM85 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote1− and Remote1+ inputs exceeds the Processor (Zone1) High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 3.

Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.

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Functional Description (Continued)

LM85

TABLE 3. Temperature Limits vs Register Settings

Temperature Reading (Decimal) Reading (Hex)

−127˚C −127 81h

4.13 Registers 54-5Bh: Fan Tachometer Low Limit

. . .

−50˚C −50 CEh

. . .

0˚C 0 00h

. . .

50˚C 50 32h

. . .

127˚C 127 7Fh

. . .

54h 55h

56h 57h

58h 59h

5Ah 5Bh

The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the Interrupt Status Register 2 register. InAuto Fan Control mode, the fan can run at low speeds, so care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt Status Register 2 if the current value in Current PWM Duty registers is 00h or if the fan 1 disabled via the Fan Configuration Register. Interrupts will never be generated for a fan if its minimum is set to FF FFh.

Given the insignificance of Bit 0 and Bit 1, these bits could be programmed to remember which fan is which, as follows.

Setting the Ready/Lock/Start/Override register Lock bit has no effect these registers.

Read/ Write

R/W R/W

Tach1 Minimum LSB Tach1 Minimum MSB715

Tach2 Minimum LSB Tach2 Minimum MSB715

Tach3 Minimum LSB Tach3 Minimum MSB715

Tach4 Minimum LSB Tach4 Minimum MSB715

Fan Bit 1 Bit 0

CPU 0 0

Memory 0 1

Chassis Front 1 0

Chassis Rear 1 1

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

6 14

5 13

4 12

3 11

2 10

1 9

0 8

Default Value

FFh FFh

4.14 Registers 5C-5Eh: Fan Configuration

5Ch R/W Fan1 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

5Dh R/W Fan2 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

5Eh R/W Fan3 Configuration ZON2 ZON1 ZON0 INV RES SPIN2 SPIN1 SPIN0 62h U

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Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Lock?

Functional Description (Continued)

This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

Bits [7:5] Zone/Mode

Bits [7:5] of the Fan Configuration registers associate each fan with a temperature sensor. When in Auto Fan Mode the fan will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If ‘Hottest’ option is selected (101 or 110), the fan will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. When in manual control mode, the Current PWM duty registers (30h-32h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers. When the fan is disabled (100) the corresponding PWM output should be driven low (or high, if inverted).

Zone 1: External Diode 1 (processor) Zone 2: Internal Sensor Zone 3: External Diode 2

TABLE 4. Fan Zone Setting

ZON[2:0] Fan Configuration

000 Fan on zone 1 auto

001 Fan on zone 2 auto

010 Fan on zone 3 auto

011 Fan always on full

100 Fan disabled

101 Fan controlled by hottest of zones 2, 3

110 Fan controlled by hottest of zones 1, 2, 3

111 Fan manually controlled (Test Mode)

LM85

Bit [4] PWM Invert

Bit [4] inverts the PWM output. If set to 0, 100% duty cycle will yield an output that is always high. If set to 1, 100% duty cycle will yield an output that is always low.

Bit [3] Reserved Bits [2:0] Spin Up

Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed.

TABLE 5. Fan Spin-Up Register

SPIN[2:0] Spin Up Time

000 0 sec

001 100 ms

010 250 ms

011 400 ms

100 700 ms

101 1000 ms

110 2000 ms

111 4000 ms

4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency

5Fh R/W Zone1 Range/Fan1

60h R/W Zone2 Range/Fan2

61h R/W Zone3 Range/Fan3

Read/ Write

Frequency

Bit 7 (MSB)

RAN3 RAN2 RAN1 RAN0 RES FRQ2 FRQ1 FRQ0 C4h U

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Lock?

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Functional Description (Continued)

LM85

In Auto Fan Mode, when the temperature for a zone is above the Temperature Limit (Registers 67-69h) and below its Absolute Temperature Limit (Registers 6A-6Ch), the speed of a fan assigned to that zone is determined as follows.

When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be Fan PWM Minimum. Between Fan Temp Limit and (Fan Temp Limit + Range), the PWM duty cycle will increase linearly according to the temperature as shown in the figure below. The PWM duty cycle will be 100% at (Fan Temp Limit + Range).

20035306

FIGURE 1. Fan Activity above Fan Temp Limit

Example for PWM1 assigned to Zone 1:

– Zone 1 Fan Temp Limit (Register 67h) is set to 50˚C (32h). – Range (Register 5Fh) is set to 8˚C (6xh).

– Fan 1 PWM Minimum (Register 64h) is set to 50% (32h). In this case, the PWM1 duty cycle will be 50% at 50˚C. Since (Zone 1 Fan Temp Limit) + (Zone 1 Range) = 50˚C + 8˚C = 58˚C, the fan will run at 100% duty cycle when the temperature

of the Zone 1 sensor reaches 58˚C. Since the midpoint of the fan control range is 54˚C, and the median duty cycle is 75% (Halfway between the PWM Minimum and

100%), PWM1 duty cycle would be 75% at 54˚C. Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%.

PWM frequency bits [3:0]

The PWM frequency bits [3:0] determine the PWM frequency for the fan. PWM Frequency Selection (Default = 011 = 30.04 Hz)

TABLE 6. Register Setting vs PWM Frequency

Freq [2:0] PWM Frequency (Exact frequencies vary by

manufacturer)

000 10 Hz 10.01 Hz

001 15 Hz 15.02 Hz

010 23 Hz 23.14 Hz

011 30 Hz 30.04 Hz

100 38 Hz 38.16 Hz

101 47 Hz 47.06 Hz

110 62 Hz 61.38 Hz

111 94 Hz 94.12 Hz

National Actual PWM Frequency

Range Selection RAN [3:0]

RAN [3:0] Range (˚C)

0000 2

0001 2.5

0010 3.33

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Functional Description (Continued)

RAN [3:0] Range (˚C)

0011 4

0100 5

0101 6.67

0110 8

0111 10

1000 13.33

1001 16

1010 20

1011 26.67

1100 32

1101 40

1110 53.33

1111 8 0

4.16 Registers 62, 63h: Min/Off, Spike Smoothing

LM85

62h R/W Min/Off, Zone1 Spike Smoothing OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00h U

63h R/W Zone2, Zone3 Spike Smoothing ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E ZN3-2 ZN3-1 ZN3-0 00h U

The Off/Min Bits [7:5] specify whether the duty cycle will be 0% or Minimum Fan Duty when the measured temperature falls below the Temperature LIMIT register setting (see table below). OFF1 applies to fan 1, OFF2 applies to fan 2, and OFF3 applies to fan

3. If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by

the LM85. If these spikes are not ignored, the CPU fan (if connected to LM85) may turn on prematurely and produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled.

When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the temperature — not the ‘smoothed out’ value.

These registers become ready only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect.

Read/

Write

Name

ZN1E, ZN2E, and ZN3E enable temperature smoothing for zones 1, 2, and 3 respectively. ZN1-2, ZN1-1, and ZN1-0 control smoothing time for Zone 1. ZN2-2, ZN2-1, and ZN2-0 control smoothing time for Zone 2. ZN3-2, ZN3-1, and ZN3-0 control smoothing time for Zone 3.

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Lock?

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Functional Description (Continued)

LM85

FIGURE 2. What LM85 Auto Fan Control Sees With and Without Spike Smoothing

ZN-X[2:0] Spike Smoothed Over

000 35 seconds

001 17.6 seconds

010 11.8 seconds

011 7.0 seconds

100 4.4 seconds

101 3.0 seconds

110 1.6 seconds

111 .8 seconds

20035307

TABLE 7. Spike Smoothing

TABLE 8. PWM Output Below Limit Depending on Value of Off/Min

Off/Min PWM Action

0 At 0% duty below LIMIT

1 At Min PWM Duty below LIMIT

4.17 Registers 64-66h: Minimum PWM Duty Cycle

64h R/W Fan1 PWM Minimum 7 6543210 80hU

65h R/W Fan2 PWM Minimum 7 6543210 80hU

66h R/W Fan3 PWM Minimum 7 6543210 80hU

These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting.

Read/ Write

Bit 7 (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Lock?

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Functional Description (Continued)

TABLE 9. PWM Duty vs Register Setting

Current Duty Value (Decimal) Value (Hex)

0% 0 00h

0.3922% 1 01h

. . .

25.098% 64 40h

. . .

50.196% 128 80h

. . .

100% 255 FFh

4.18 Registers 67-69h: Temperature Limit

LM85

. . .

67h R/W Zone1 Fan Temp Limit 7 6 5 43210 5AhU

68h R/W Zone2 Fan Temp Limit 7 6 5 43210 5AhU

69h R/W Zone3 Fan Temp Limit 7 6 5 43210 5AhU

These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the algorithm set forth in the Auto Fan Range, PWM Frequency register description. Default = 90˚C = 5Ah

Read/ Write

Bit 7 (MSB)

TABLE 10. Temperature Limit vs Register Setting

Temperature Reading (Decimal) Reading (Hex)

−127˚C −127 81h

. . .

−50˚C −50 CEh

. . .

0˚C 0 00h

. . .

50˚C 50 32h

. . .

127˚C 127 7Fh

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

. . .

(LSB)

Default Value

Lock?

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Functional Description (Continued)

LM85

4.19 Registers 6A-6Ch: Absolute Temperature Limit

6Ah R/W Zone1 Absolute Temp Limit 7 654321 0 64h U

6Bh R/W Zone2 Absolute Temp Limit 7 654321 0 64h U

6Ch R/W Zone3 Absolute Temp Limit 7 654321 0 64h U

For the LM85B in the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of the PWM outputs will incresase its duty cycle to 100%. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. If set to 80h (-128˚C), the feature is disabled. Default=100˚C=64h

For the LM85C in the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, only the PWM output associated with the Absolute Temperature Limit will go to 100%.

These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. After power up the default values are used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to these registers are possible.

Read/

Write

Name

TABLE 11. Absolute Limit vs Register Setting

Temperature Reading (Decimal) Reading (Hex)

−127˚C −127 81h

−50˚C −50 CEh

0˚C 0 00h

50˚C 50 32h

127˚C 127 7Fh

Bit 7

(MSB)

. . .

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

. . .

Default

(LSB)

. . .

Value

Lock?

4.20 Registers 6D-6Eh: Zone Hysteresis Registers

6Dh R/W Zone1 and Zone2 Hysteresis H1-3 H1-2 H1-1 H1-0 H2-3 H2-2 H2-1 H2-0 44h U

6Eh R/W Zone3 Hysteresis H3-3 H3-2 H3-1 H3-0 RES RES RES RES 40h U

If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur:

These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to thses registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

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Read/ Write

– The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit.

– The Hysteresis registers control this amount. See below table for details.

Bit 7 (MSB)

TABLE 12. Hysteresis Settings

Setting HYSTERESIS

0h 0˚C

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default Value

Lock?

Functional Description (Continued)

TABLE 12. Hysteresis Settings (Continued)

Setting HYSTERESIS

. . .

5h 5˚C

. . .

Fh 15˚C

4.21 Register 6Fh: Test Register

LM85

. . .

6Fh R/W Test Register RES RES RES RES RES RES RES XEN 00h

If the XEN bit is set high, the part will be placed into XOR tree test mode. Clearing the bit (writinga0totheXENbit) brings the part out of XOR tree test mode.

This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

4.22 Registers 70-7Fh: Vendor Specific Registers

These registers are for vendor specific features, including test registers. They will not default to a specific value on power up.

4.22.1 Register 74h: Tachometer Monitor Mode

74h R/W Tach Monitor Mode RES RES T3/4-1 T3/4-0 T2-1 T2-0 T1-1 T1-0 00h

Each fan TACH input has 4 possible modes of operation. The modes for TACH3 and TACH4 share control bits T3/4-[1:0]; TACH2 is controlled by T2-[1:0]; TACH1 is controlled by T1-[1:0]. The result reported in all modes is based on 2 pulses per revolution. In order for modes 2 and 3 to function properly it is required that the:

PWM1 output must control the fan that has it’s tachometer output connected to the TACH1 LM85 input. PWM2 output must control the fan that has it’s tachometer output connected to the TACH2 LM85 input. PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4 LM85 inputs.

Setting (Tn[1:0]) Mode Function

Read/ Write

Read/

Write

00 0 Traditional tach input monitor, false readings when under minimum detctable RPM

01 1 Traditional tach input monitor, FFFFh reading when under minimum detectable RPM

10 2 Most accurate readings, FFFFh reading when under minimum detectable RPM

11 3 Least effect on programmed PWM of Fan, FFFFh reading when under minimum detectable RPM

Name

Bit 7 (MSB)

Bit 7

(MSb)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSb)

Default

Value

Default Value

Lock?

Mode 0: This mode uses the conventional method for fan tachometer pulse detection and does not include any circuitry to

•

compensate for PWM Fan drive. This mode should be used when PWM drive is not used to power the fan. This mode may report a false RPM reading when under minimum detectable RPM as shown in the follwing table.

Mode 1: This mode uses the convertional method for fan tach detection. The reading will be FFFFh if it is below minimum

•

detectable RPM. Mode 2: This mode is optimized for accurate RPM readings and activates circuitry that extends the lower side of the RPM

•

reading as shown in the following table. Mode 3: This mode minimizes the effect on the RPM setting and activates circuitry that extends the lower side of the RPM

•

reading as shown in the following table.

PWM Frequency Mode 0 and 1 Minimum RPM Mode 2 and 3 Minimum RPM

10.01 841 210

15.02 1262 315

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Functional Description (Continued)

LM85

23.14 1944 420

30.04 2523 420

38.16 3205 420

47.06 3953 420

61.38 5156 420

94.12 7906 420

This register is not effected when the Ready/Lock/Start/Override register Lock bit is set. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.

4.22.2 Register 75h: Fan Spin-up Mode

75h R/W Fan Spin-up Mode RES RES RES RES RES PWM3 SU PWM2 SU PWM1 SU 7h U

The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed by the Fan Configuration register has elapsed. When set to a 1, the spin-up time will terminate early if the TACH reading exceeds the Tach Minimum value or after the time programmed by the Fan Configuration register has elapsed, whichever occurs first.

4.23 Undefined Registers

Any reads to undefined registers will always return 00h. Writes to undefined registers will have no effect and will not return an error.

5.0 XOR TEST MODE

The LM85 incorporates a XOR tree test mode. When the test mode is enabled by setting the “XEN” bit high in the Test Register at address 6Fh via the SMBus, the part will enter XOR test mode.

Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK are not to be included in the test tree.

Read/

Write

Name

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

Default

Value

Lock?

6.0 DIFFERENCES BETWEEN THE LM85BIMQ AND LM85CIMQ It is highly recommended that new designs use the LM85BIMQ.

Item No. Description LM85CIMQ LM85BIMQ

1 Voltage Monitoring Accuracy +3.5% to −0.5% of Full Scale

2 PWM Output logic LOW loading 3mA at 0.4V 8mA at 0.4V

3 LSB and MSB Fan TACH value

registers (registers 28h, 29h; 2Ah, 2Bh; 2Ch, 2Dh; 2Eh, 2Fh)

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Tach value registers must be read LSB followed by MSB. Reading the LSB latches the MSB. For example: if you read the LSB then the MSB, subsequent reads of just the MSB register will yield the old result. Internally, the TACH result is being updated but there is no read access unless the LSB register is read before an MSB.

2% of Full Scale

Tach value registers must be read LSB followed by MSB. Reading the LSB latches the MSB until read. After the MSB is read it will be updated with a new value, without requiring a read of the LSB register.

20035308

Functional Description (Continued)

Item No. Description LM85CIMQ LM85BIMQ

4 Overide bit (register 40h bit 3)

function with disabled PWM output (Fan configuration registers 5Ch-5Eh, bits fan_config[7:5]=ZON[2:0]=100

5 Auto Fan mode and Absolute

Temperature Limit function

6 Register 3Fh Device ID default 60h 62h

The override bit has no effect when the PWM output is disabled.

Only the PWM output associated with the zone that has exceeded its Absolute Limit will increase to 100%.

The overide bit has precedance over all of the PWM output dissable bits. Therefore, if a PWM output is dissabled, setting the override bit will set the PWM output to 100%.

When one zone exceeds its Absolute Limit all PWM outputs wil increase to 100%.

Revision History

Date Revision

8/2002 Added LM85BIMQ functional differences and specifications.

3/2003 Updated Register 74h, Tachometer Monitor Mode description.

LM85

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Physical Dimensions inches (millimeters)

unless otherwise noted

LM85 Hardware Monitor with Integrated Fan Control

24-Lead Molded QSOP Package,

Order Number LM85BIMQ, LM86BIMQX, LM85CIMQ or LM85CIMQX

NS Package Number MQA24

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

labeling, can be reasonably expected to result in a significant injury to the user.

National Semiconductor Americas Customer Support Center

Email: new.feedback@nsc.com Tel: 1-800-272-9959

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Rainbow Electronics LM85 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Features

Key Specifications

Applications

Block Diagram

Connection Diagram

Pin Descriptions

Absolute Maximum Ratings (Notes 1,

DC Electrical Characteristics

AC Electrical Characteristics

Functional Description

1.0 SMBUS

1.1 Addressing

2.0 FAN REGISTER DEVICE SET-UP

3.0 AUTO FAN CONTROL OPERATING MODE

4.0 REGISTER SET

4.1 Register 20-24h: Voltage Reading

4.2 Register 25-27h: Temperature Reading

TABLE 1. Temperature vs Register Reading

4.3 Register 28-2Fh: Fan Tachometer Reading

4.4 Register 30-32h: Current PWM Duty

4.5 Register 3Eh: Company ID

4.6 Register 3Fh: Version/Stepping

4.7 Register 40h: Ready/Lock/Start/Override

4.8 Register 41h: Interrupt Status Register 1

4.9 Register 42h: Interrupt Status Register 2

4.10 Register 43h: VID

4.11 Registers 44-4Dh: Voltage Limit Registers

TABLE 2. Voltage Limits vs Register Setting

4.12 Registers 4E-53h: Temperature Limit Registers

TABLE 3. Temperature Limits vs Register Settings

4.13 Registers 54-5Bh: Fan Tachometer Low Limit

4.14 Registers 5C-5Eh: Fan Configuration

TABLE 4. Fan Zone Setting

TABLE 5. Fan Spin-Up Register

4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency

FIGURE 1. Fan Activity above Fan Temp Limit

TABLE 6. Register Setting vs PWM Frequency

4.16 Registers 62, 63h: Min/Off, Spike Smoothing

FIGURE 2. What LM85 Auto Fan Control Sees With and Without Spike Smoothing

TABLE 7. Spike Smoothing

TABLE 8. PWM Output Below Limit Depending on Value of Off/Min

4.17 Registers 64-66h: Minimum PWM Duty Cycle

TABLE 9. PWM Duty vs Register Setting

4.18 Registers 67-69h: Temperature Limit

TABLE 10. Temperature Limit vs Register Setting

4.19 Registers 6A-6Ch: Absolute Temperature Limit

TABLE 11. Absolute Limit vs Register Setting

4.20 Registers 6D-6Eh: Zone Hysteresis Registers

TABLE 12. Hysteresis Settings

4.21 Register 6Fh: Test Register

4.22 Registers 70-7Fh: Vendor Specific Registers

4.22.1 Register 74h: Tachometer Monitor Mode

4.22.2 Register 75h: Fan Spin-up Mode

4.23 Undefined Registers

5.0 XOR TEST MODE

6.0 DIFFERENCES BETWEEN THE LM85BIMQ AND LM85CIMQ It is highly recommended that new designs use the LM85BIMQ.

Revision History

Physical Dimensions inches (millimeters)