Rainbow Electronics HT49R70A-1 User Manual

Features

Operating voltage: 3.0V~5.5V

8 input lines

16 bidirectional I/O lines

Two external interrupt input

One 8-bit and one 16-bit programmable timer/event counter with PFD (programmable frequency divider) function

LCD driver with 41´3or40´4 segments

8K´16 program memory EPROM

224´8 data memory RAM

Real Time Clock (RTC)

8-bit prescaler for RTC

General Description

The HT49R70A-1 is an 8-bit high performance single chip MCU. Its single cycle instruction and two-stage pipeline architecture make it suitable for high speed ap plications. The device is also suitable for use in multiple

HT49R70A-1

8-Bit LCD Type OTP MCU

Watchdog Timer

Buzzer output

On-chip crystal, RC and 32768Hz crystal oscillator

HALT function and wake-up feature reduce power consumption

8-level subroutine nesting

Bit manipulation instruction

16-bit table read instruction

Up to 0.5ms instruction cycle with 8MHz system clock

63 powerful instructions

All instructions in 1 or 2 machine cycles

100-pin QFP package

LCD low power applications such as scales, leisure products, high-level household appliances, hand held LCD products, and battery operated systems in particu

lar.

Rev. 1.00 1 December 4, 2001

Block Diagram

P r o g r a m E P R O M

I n s t r u c t i o n

R e g i s t e r

P r o g r a m

C o u n t e r

HT49R70A-1

/ 4

M U X

W D T O S C

S Y S

R T C O u t P B 2 / T M R 0 P B 3 / T M R 1 T M R 0 O V

S Y S

T i m e B a s e O u t f

T 1 D

/ 4

S Y S

R T C O S C

O S C 3 O S C 4

S T A C K

I n t e r r u p t

C i r c u i t

I N T C

T M R 0 C

T M R 0

P F D 0

T M R 1 C

T M R 1

P F D 1

M U X

R T C

M P

D A T A

M e m o r y

W D T

T i m e B a s e

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t i o n

O S C 2 O S C 4

O S C 1 R E S

V D D V S S O S C 3

C O M 0 ~ C O M 2

M U X

A L U

S h i f t e r

A C C

L C D D R I V E R

C O M 3 / S E G 4 0

S T A T U S

L C D

M e m o r y

S E G 0 ~ S E G 3 9

P C

P O R T B

P C 0 ~ P C 7

P B 0 / I N T 0 P B 1 / I N T 1

P B

P B 2 / T M R 0 P B 3 / T M R 1 P B 4 ~ P B 7

B P

P O R T A

P A 0 / B Z P A 1 / B Z

P A

P A 2 P A 3 / P F D P A 4 ~ P A 7

E N / D I S

H A L T

L V D / L V R

Rev. 1.00 2 December 4, 2001

Pin Assignment

HT49R70A-1

P A 3 / P F D

P A 0 / B Z

P A 1 / B Z

O S C 1

P A 4

R E S

P A 2

O S C 4

O S C 3

O S C 2

S E G 0

S E G 1

S E G 2

S E G 3

S E G 4

S E G 5

S E G 6

S E G 7

V D D

S E G 8

P B 0 / I N T 0

P B 1 / I N T 1 P B 2 / T M R 0 P B 3 / T M R 1

V S S

P A 5

P A 6 P A 7

P B 4 P B 5 P B 6 P B 7 P C 0 P C 1 P C 2 P C 3 P C 4 P C 5 P C 6 P C 7

1 2

N C

7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5

N C

2 6

N C

2 7

N C

2 8

N C

2 9

N C

3 0

3 1

3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0

V 2

V 1

V L C D

C O M 0

C 2

C 1

H T 4 9 R 7 0 A - 1 1 0 0 Q F P - A

C O M 3 / S E G 4 0

S E G 3 9

C O M 2

C O M 1

S E G 3 8

S E G 3 7

S E G 3 6

S E G 3 5

S E G 3 4

S E G 3 3

8 18 28 38 48 58 68 78 88 99 09 19 29 39 49 59 69 79 89 91 0 0

8 0

S E G 9

7 9

S E G 1 0

7 8

S E G 1 1

7 7

N C N C

7 6

N C

7 5

S E G 1 2

7 4 7 3

S E G 1 3

7 2

S E G 1 4 S E G 1 5

7 1

S E G 1 6

7 0

S E G 1 7

6 9

S E G 1 8

6 8

S E G 1 9

6 7

S E G 2 0

6 6

S E G 2 1

6 5

S E G 2 2

6 4

S E G 2 3

6 3

S E G 2 4

6 2

S E G 2 5

6 1

S E G 2 6

6 0

S E G 2 7

5 9

S E G 2 8

5 8

S E G 2 9

5 7

N C

5 6

N C

5 5

N C

5 4

N C

5 3

N C

5 2

N C

5 1

S E G 3 2

S E G 3 1

N C

S E G 3 0

Rev. 1.00 3 December 4, 2001

Pin Description

Pin Name I/O Options Description

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trig PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7

PC0~PC7 I/O

VSS

VLCD I

V1,V2,C1,C2 I

SEG40/COM3 COM2~COM0

SEG39~SEG0 O

OSC4 OSC3

VDD

OSC2 OSC1

RES

I/O

¾¾

O 1/3 or 1/4 Duty

¾¾

Wake-up Pull-high

CMOS or

Pull-high

CMOS or

System Clock

Crystal or RC

or None

NMOS

or None

NMOS

RTC or

ger input capability. Each bit on port can be configured as a wake-up input by

options. PA0~PA3 can be configured as a CMOS output or NMOS input/out

put with or without pull-high resistor by options. PA4~PA7 are always

pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O

pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD

output also by options.

PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each bit on port are

pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input pins or as

external interrupt control pins (INT0

plication. PB2 and PB3 can be set as an input pin or as a timer/event counter

input pin TMR0 and TMR1 also by software application.

PC0~PC7 constitute an 8-bit bidirectional input/output port with a Schmitt trig

ger input capability. On the port, such can be configured as CMOS output or

NMOS input/output with or without pull-high resistor by options.

Negative power supply, ground

LCD power supply

Voltage pump

SEG40 can be set as a segment or as a common output driver for LCD panel

by options. COM2~COM0 are outputs for LCD panel plate.

LCD driver outputs for LCD panel segments

Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purposes or to a system clock source (depending

on the options).

No built-in capacitor

Positive power supply

OSC1 and OSC2 are connected to an RC network or a crystal (by options) for

the internal system clock. In the case of RC operation, OSC2 is the output ter-

minal for 1/4 system clock.

The system clock may come from the RTC oscillator. If the system clock co

mes from RTCOSC, these two pins can be floating.

Schmitt trigger reset input, active low

HT49R70A-1

) and (INT1) respectively, by software ap

Absolute Maximum Ratings

Supply Voltage ...................................VSS-0.3V to 5.5V

Input Voltage..............................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.

Rev. 1.00 4 December 4, 2001

-0.3V to VDD+0.3V

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-40°Cto85°C

HT49R70A-1

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

STB2

STB3

STB4

STB5

STB6

STB7

IL1

IH1

IL2

IH2

LVR

LVD

Note:

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (f

Standby Current (*fS=T1)

Standby Current (*fS=32.768kHz OSC)

Standby Current (*fS=WDT RC OSC)

Standby Current (*fS=32.768kHz OSC)

Standby Current (*fS=WDT RC OSC)

Input Low Voltage for I/O Ports, TMR and INT

Input High Voltage for I/O Ports, TMR and INT

Input Low Voltage (RES)

Input High Voltage (RES)

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance of I/O Ports and INT0

, INT1

Low Voltage Reset Voltage

Low Voltage Detector Voltage

² please refer to clock option of WDT (page 12)

²*f

=32768Hz)

SYS

Test Conditions

Conditions

¾¾

No load, f

No load

No load, system HALT LCD off at HALT

No load, system HALT LCD on at HALT, C type

No load, system HALT

LCD on at HALT

R type, 1/2bias

No load, system HALT

LCD on at HALT

R type, 1/3bias

No load, system HALT

LCD on at HALT

R type, 1/2bias

No load, system HALT

LCD on at HALT

R type, 1/3bias

=0.1V

=0.9V

LVD voltage 3.3V option 2.7 3.2 3.6 V

LVD voltage 3.3V option 3.0 3.3 3.6 V

SYS

=4MHz

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

¾ ¾

Min. Typ. Max. Unit

3.0

2.0 3.0 mA

5.0 8.0 mA

1.8 2.7 mA

4.6 7.5 mA

1.2 2 mA

¾ ¾

47mA

¾¾ ¾¾ ¾4 ¾14 ¾ ¾ ¾

0.8V

0.9V

610

17 30

34 60

13 25

28 50

14 25

26 50

10 20

19 40

¾ ¾ ¾

0.2V

0.4V

612

10 25

-2 -4 ¾

-5 -8 ¾

40 60 80

10 30 50

Ta=25°C

5.5 V

¾ ¾

mA mA mA mA mA mA mA

kW kW

Rev. 1.00 5 December 4, 2001

HT49R70A-1

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

SYS3

RTCOSC

TIMER

WDTOSC

RES

SST

INT

Note: t

System Clock (Crystal OSC)

System Clock (RC OSC)

System Clock (32768Hz Crystal OSC)

RTC Frequency

Timer I/P Frequency (TMR0/TMR1)

Watchdog Oscillator

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

= 1/f

SYS

Test Conditions

Conditions

¾¾ ¾

¾¾

Power-up or wake-up

from HALT

¾¾

Min. Typ. Max. Unit

400

32768

45 90 180

35 65 130

¾¾ms

1024

¾¾ms

Ta=25°C

4000 kHz

8000 kHz

4000 kHz

8000 kHz

4000 kHz

8000 kHz

SYS

Rev. 1.00 6 December 4, 2001

Functional Description

Execution flow

The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is inter nally divided into four non-overlapping clocks. One in struction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de coding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each in struction to be effectively executed in a cycle. If an in struction changes the value of the program counter, two cycles are required to complete the instruction.

Program counter - PC

The program counter (PC) is 13 bits wide and it controls the sequence in which the instructions stored in the pro gram ROM are executed. The contents of the PC can specify a maximum of 8192 addresses.

HT49R70A-1

After accessing a program memory word to fetch an in struction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the

next instruction code.

When executing a jump instruction, conditional skip ex ecution, loading a PCL register, a subroutine call, an ini tial reset, an internal interrupt, an external interrupt, or

returning from a subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth erwise proceed to the next instruction.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per forms a short jump. The destination is within 256 loca tions.

S y s t e m C l o c k

O S C 2 ( R C o n l y )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 )

Execution flow

Mode

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0000000000000

External Interrupt 0 0000000000100

External Interrupt 1 0000000001000

Timer/Event Counter 0 overflow 0000000001100

Timer/Event Counter 1 overflow 0000000010000

Time Base Interrupt 0000000010100

RTC Interrupt 0000000011000

Skip PC+2

Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *12~*0: Program counter bits S12~S0: Stack register bits

#12~#0: Instruction code bits @7~@0: PCL bits

Rev. 1.00 7 December 4, 2001

When a control transfer takes place, an additional dummy cycle is required.

Program memory - EPROM

The program memory (EPROM) is used to store the pro gram instructions which are to be executed. It also con tains data, table, and interrupt entries, and is organized into 8192´16 bits which are addressed by the PC and table pointer.

Certain locations in the ROM are reserved for special usage:

Location 000H

Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.

Location 004H Location 004H is reserved for the external interrupt service program. If the INT0

input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

0 1 0 H

0 1 4 H

0 1 8 H

n 0 0 H n F F H

1 F F F H

D e v i c e i n i t i a l i z a t i o n p r o g r a m

E x t e r n a l i n t e r r u p t 0 s u b r o u t i n e

E x t e r n a l i n t e r r u p t 1 s u b r o u t i n e

T i m e r / e v e n t c o u n t e r 0 i n t e r r u p t s u b r o u t i n e

T i m e r / e v e n t c o u n t e r 1 i n t e r r u p t s u b r o u t i n e

T i m e B a s e I n t e r r u p t

R T C I n t e r r u p t

L o o k - u p t a b l e ( 2 5 6 w o r d s )

1 6 b i t s

N o t e : n r a n g e s f r o m 0 t o 1 F

P r o g r a m R O M

Program memory

HT49R70A-1

Location 008H Location 008H is reserved for the external interrupt service programalso. If the INT1 and the interrupt is enabled, and the stack is not full,

the program begins execution at location 008H.

Location 00CH Location 00CH is reserved for the Timer/Event Coun ter 0 interrupt service program. If a timer interrupt re sults from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro gram begins execution at location 00CH.

Location 010H Location 010H is reserved for the Timer/Event Coun ter 1 interrupt service program. If a timer interrupt re sults from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro gram begins execution at location 010H.

Location 014H Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.

Location 018H Location 018H is reserved for the real time clock inter rupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H.

Table location Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the ta ble word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the ta ble location. Before accessing the table, the location should be placed in TBLP. All the table related instruc tions require 2 cycles to complete the operation. These areas may function as a normal ROM depend ing upon the user's requirements.

input pinis activated,

Instruction(s)

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *12~*0: Table location bits P12~P8: Current program counter bits

@7~@0: Table pointer bits

Rev. 1.00 8 December 4, 2001

HT49R70A-1

Stack register - STACK

The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its acti vated level is indexed by a stack pointer (SP) and is nei ther readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subrou tine or interrupt routine, signaled by a return instruction (RET or ), the contents of the PC is restored to its previ ous value from the stack. After chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac knowledgment is still inhibited. Once the SP is decre mented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the program mer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent six return addresses are stored).

Data memory - RAM

The data memory (RAM) is designed with 245´8 bits, and is divided into two functional groups, namely; special function registers and general purpose data memory, most of which are readable/writeable, although some are read only.

Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Inter rupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a Timer/Event Counter 0 con trol register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), I/O registers (PA;12H, PB;14H, PC;16H), and Interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction com mands.

The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Ex cept some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i² and ²CLR [m].i² They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H).

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

0 0 H 0 1 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

0 2 H 0 3 H 0 4 H

0 5 H

0 6 H 0 7 H 0 8 H

0 9 H

0 A H

0 B H 0 C H 0 D H 0 E H

0 F H

1 0 H 1 1 H

1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H

1 8 H

1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H

2 0 H

F F H

M P 0

M P 1

B P

A C C

P C L

T B L P T B L H

R T C C

S T A T U S

I N T C 0

T M R 0 T M R 0 C T M R 1 H

T M R 1 L T M R 1 C

P A

P B

P C

I N T C 1

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 2 2 4 B y t e s )

RAM mapping

Indirect addressing register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1(03H) respectively. Reading lo cation 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation.

The function of data movement between two indirect ad dressing registers is not supported. The memory pointer

registers, MP0andMP1,are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and

LCD display memory.

S p e c i a l P u r p o s e

D A T A M E M O R Y

: U n u s e d .

R e a d a s " 0 "

Rev. 1.00 9 December 4, 2001

HT49R70A-1

Accumulator - ACC

The accumulator (ACC) is related to the ALU opera tions. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic opera tions and provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data operation but also changes the status register.

Status register - STATUS

The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

Except for the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations.

On entering the interrupt sequence or executing the subroutine call, the status register will not be automati

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.

Interrupts

The HT49R70A-1 provides two external interrupts, two

internal timer/event counter interrupts, an internal time

base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and inter rupt control register 1 (INTC1;1EH) both contain the in terrupt control bits that are used to set the enable/disable status and interrupt request flags.

Once an interrupt subroutine is serviced, other inter rupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this in terval, but only the interrupt request flag will be re corded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow in terrupt nesting. Once the stack is full, the interrupt re quest will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full.

All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service pro

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC 1

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV 3

PD 4

TO 5

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the ²CLR WDT² instruction. PD is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

Unused bit, read as ²0²

Status register

Rev. 1.00 10 December 4, 2001

HT49R70A-1

gram which corrupts the desired control sequence, the contents should be saved in advance.

External interrupts are triggered by a high to low transi tion of INT0 flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts.

The internal Timer/Event Counter 0 interrupt is initial ized by setting the Timer/Event Counter 0 interrupt re quest flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is en abled, and the stack is not full, and the T0F bit is set, a subroutine calltolocation 0CH occurs. The related inter rupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its sub routine call location is 10H.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of

or INT1, and the related interrupt request

INTC1), that is caused by a regular real time clock sig nal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location

18H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter rupts.

During the execution of an interrupt subroutine, other in terrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related in terrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI sets the EMI bit and enables an

interrupt service, but RET does not.

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 0 1 04H

b External interrupt 1 2 08H

c Timer/Event Counter0overflow 3 0CH

d Timer/Event Counter 1 overflow 4 10H

e Time base interrupt 5 14H

f Real time clock interrupt 6 18H

0 EMI Control the master (global) interrupt (1=enabled; 0=disabled)

1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled)

2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled)

INTC0

(0BH)

INTC1

(1EH)

Rev. 1.00 11 December 4, 2001

3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)

5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)

6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

1 ETBI Control the time base interrupt (1=enabled; 0:disabled)

2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled)

4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

5 TBF Time base request flag (1=active; 0=inactive)

6 RTF Real time clock request flag (1=active; 0=inactive)

¾ Unused bit, read as ²0²

INTC register

HT49R70A-1

The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external inter rupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and en able master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.

It is recommended that a program should not use the ²CALL subroutine²within the interrupt subroutine. It¢sbe cause interrupts often occur in an unpredictable manner or require to be serviced immediately in some applica tions. During that period, if only one stack is left, and enabling theinterruptisnotwellcontrolled,operationofthe ²call² in the interrupt subroutine may damage the original control sequence.

Oscillator configuration

The HT49R70A-1 provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ig nores external signal in order to conserve power. The 32768Hz crystal oscillator (system oscillator) still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the system oscillator or oscillator) is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode.

Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required,

and the range of the resistance should be from 40kW to 680kW. The system clock, divided by 4, is available on

OSC2 with pull-high resistor, which can be used to syn chronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.

On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A reso nator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are re quired.

There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscil lator can be applied. The crystal should be connected

between OSC3 and OSC4.

The RTC oscillator circuit can be controlled to oscillate

quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is

recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds.

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by options to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC os cillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all exe cutions related to the WDT lead to no operation.

O S C 3

O S C 4

3 2 7 6 8 H z C r y s t a l / R T C O s c i l l a t o r

O S C 1

/ 4

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

S Y S

O S C 1

D D

O S C 2

System oscillator

Rev. 1.00 12 December 4, 2001

S y s t e m C l o c k / 4

HT49R70A-1

R T C O S C

W D T O S C

3 2 7 6 8 H z

1 2 k H z

R O M C o d e

O p t i o n

D i v i d e r

W D T C l e a r

Watchdog Timer

The WDT time-out period is fixed as fS/216.

If the WDT clock source chooses the internal WDT oscil lator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the ²HALT² instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic.

When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recom mended, since the HALT can stop the system clock.

The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES

), software instruction,

and a ²HALT² instruction. There are two types of software instructions; ²CLR WDT² and the other set -²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one type of instruction can be active at a time depending on the options -²CLR WDT² times selection option. If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² in struction clears the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e., CLR WDT times

D i v i d e r

C K TRC K T

T i m e - o u t R e s e t fS/ 2

equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the

chip due to time-out.

Multi-function timer

The HT49R70A-1 provides a multi-function timer for the WDT , time base and RTC but with different time-out pe riods. The multi-function timer consists of an 8-stage di vider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock

(i.e.., system clock divided by 4). The multi-function

timer also provides a selectable frequency signal (ranges from f

/22to fS/28) for LCD driver circuits, and a

selectable frequency signal (ranging from f for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD driver circuits to have proper display.

Time base

The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from f

/212to fS/215selected by options. If time

base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is en abled, and the stack is not full, a subroutine call to loca

tion 14H occurs. The time base time-out signal can also

be applied as a clock source of the Timer/Event Counter 1 so as to get a longer time-out period.

1 6

/22to fS/29)

f s

D i v i d e r P r e s c a l e r

R O M C o d e O p t i o n

L C D D r i v e r ( f B u z z e r ( f

/ 22~ fS/ 28)

/ 22~ fS/ 29)

R O M C o d e

O p t i o n

T i m e B a s e I n t e r r u p t

1 2

~ fS/ 2

1 5

fS/ 2

Time base

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