Rainbow Electronics HT24LC16 User Manual
CMOS 16K 2-Wire Serial EEPROM
Features
·
Operating voltage: 2.2V~5.5V
·
Low power consumption
-
Operation: 5mA max.
-
Standby: 5mA max.
·
Internal organization: 2048´8
·
2-wire Serial Interface
·
Write cycle time: 5ms max.
·
Automatic erase-before-write operation
General Description
The HT24LC16 is an 16K-bit serial read/write
non-volatile memory device using the CMOS floating
gate process. Its 16384 bits of memory are organized
into 2048 words and each word is 8 bits. The device is
optimized for use in many industrial and commercial ap
Block Diagram Pin Assignment
·
Partial page write allowed
·
16-byte Page Write Mode
·
Write operation with built-in timer
·
Hardware controlled write protection
·
40-year data retention
·
106rewrite cycles per word
·
Commerical temperature range (0°Cto+70°C)
·
8-pin DIP/SOP package
plications where low power and low voltage operation
are essential. Up to only one HT24LC16 device may be
connected to the same 2-wire bus. The HT24LC16 is
guaranteed for 1M erase/write cycles and 40-year data
-
retention.
HT24LC16
S C L
S D A
W P
A 0 ~ A 2
V C C
V S S
I / O
C o n t r o l
L o g i c
M e m o r y
C o n t r o l
L o g i c
A d d r e s s
C o u n t e r
H V P u m p
X
D
E E P R O M
A r r a y
E
C
P a g e B u f f e r
Y D E C
S e n s e A M P
R / W C o n t r o l
Pin Description
Pin Name I/O Description
A0~A2
SDA
SCL
WP
VSS
VCC
I Address input
I/O Serial data
I Serial clock input
I Write protect
¾
¾
Negative power supply, ground
Positive power supply
A 0
1
A 1
2
3
A 2
4
V S S
H T 2 4 L C 1 6
8 D I P - A / S O P - A
V C C
8
W P
7
6
S C L
5
S D A
Rev. 1.20 1 November 4, 2002
HT24LC16
Absolute Maximum Ratings
Operating Temperature (Commercial) ........................................................................................................ 0°Cto70°C
Storage Temperature ............................................................................................................................ -50°Cto125°C
Applied VCC Voltage with Respect to VSS ............................................................................................... -0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS
........................................................................................................
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
-0.3V to VCC+0.3V
-
D.C. Characteristics
Symbol Parameter
V
I
CC1
I
CC2
V
V
V
I
LI
I
LO
I
STB1
I
STB2
C
C
CC
IL
IH
OL
IN
OUT
Operating Voltage
Operating Current 5V Read at 100kHz
Operating Current 5V Write at 100kHz
Input Low Voltage
Input High Voltage
Output Low Voltage 2.4V
Input Leakage Current 5V
Output Leakage Current 5V
Standby Current 5V
Standby Current 2.4V
Input Capacitance (See Note)
Output Capacitance (See Note)
Note: These parameters are periodically sampled but not 100% tested
Test Conditions
V
CC
Conditions
¾¾
¾¾ -1 ¾
¾¾
=2.1mA
I
OL
=0 or V
V
IN
=0 or V
V
OUT
=0 or V
V
IN
=0 or V
V
IN
¾ f=1MHz 25°C ¾¾
¾ f=1MHz 25°C ¾¾
A.C. Characteristics
Symbol Parameter Remark
f
SK
t
HIGH
t
LOW
t
R
t
F
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time Note
SDA and SCL Fall Time Note
START Condition Hold Time
START Condition Setup Time
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Data Input Hold Time
Data Input Setup Time
STOP Condition Setup Time
¾¾
¾
¾
¾
¾
¾
Min. Typ. Max. Unit
2.2
¾¾
¾¾
0.7V
CC
¾¾
CC
CC
CC
CC
¾¾
¾¾
¾¾
¾¾
Standard Mode*
Min. Max. Min. Max.
100
4000
4700
¾
¾
4000
4000
0
200
4000
¾
¾
1000
300
¾
¾
¾
¾
¾
¾
¾
V
600
1200
600
600
100
600
Ta=0°Cto70°C
5.5 V
2mA
5mA
0.3V
CC
V
+0.5
CC
0.4 V
1
1
5
4
6pF
8pF
Ta=0°Cto70°C
=5V±10%
CC
400 kHz
¾
¾
¾
300 ns
¾
300 ns
¾
¾
¾
0
¾
¾
¾
V
V
mA
mA
mA
mA
Unit
ns
ns
ns
ns
ns
ns
ns
Rev. 1.20 2 November 4, 2002
HT24LC16
Symbol Parameter Remark
t
AA
Output Valid from Clock
¾¾
Time in which the bus must be
t
BUF
Bus Free Time
free before a new transmis
sion can start
t
SP
t
WR
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
Noise suppression time
¾¾5¾
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means V
=2.2V to 5.5V
CC
For relative timing, refer to timing diagrams
Functional Description
·
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
·
A0, A1, A2
The HT24LC16 does not use the device address pins
which limits the number of devices on a single bus to
one. The A0, A1 and A2 pins have no connection.
·
Write protect (WP)
The HT24LC16 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
, the write protection feature is enabled and oper
V
CC
ates as shown in the following table.
WP Pin Status Protect Array
At V
At V
CC
SS
Full Array (16K)
Normal Read/Write Operations
Memory organization
Internally organized with 2048 8-bit words, the 16K re
quires an 11-bit data word address for random word ad
dressing.
Device operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
-
S D A
S C L
Device addressing
The 16K EEPROM devices require an 8-bit device ad
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 16K does not use any device address bits but in
stead the 3 bits are used for memory page addressing.
These page addressing bits on the 16K devices should
be considered the most significant bits of the data word
address which follows. The A0, A1 and A2 pins have no
connection.
Standard Mode*
V
CC
=5V±10%
Min. Max. Min. Max.
4700
-
S t a r t
c o n d i t i o n
¾
3500
¾
100
A d d r e s s o r
a c k n o w l e d g e
v a l i d
¾
1200
¾
D a t a a l l o w e d
t o c h a n g e
Unit
900 ns
ns
¾
50 ns
5ms
S t o p
c o n d i t i o n
-
-
Rev. 1.20 3 November 4, 2002
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
1 0
D e v i c e A d d r e s s
R / W1 0 A 2 A 1 A 0
Write operations
·
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
·
Page write
The 16K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
zero after each data word received. The
microcontroller must terminate the page write sequence
with a stop condition (refer to Page write timing).
The data word address lower four bits are internally in
cremented following the receipt of each data word.
The higher data word address bits are not incre
mented, retaining the memory page row location.
HT24LC16
·
Acknowledge polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com
mand has been issued from the master, the device ini
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W=0). If the device is still busy
with the write cycle, then no ACK will be returned. If
the cycle is completed, then the device will return the
ACK and the master can then proceed with the next
read or write command.
-
-
S e n d W r i t e C o m m a n d
S e n d S t o p C o n d i t i o n
t o I n i t i a t e W r i t e C y c l e
S e n d S t a r t
S e n d C o n t r o l B y t e
w i t h R / W = 0
( A C K = 0 ) ?
Y e s
N e x t O p e r a t i o n
N o
Acknowledge polling flow
-
-
-
-
W o r d a d d r e s s D A T A
A C K A C K
P
S t o p
S D A
S
S t a r t
D e v i c e a d d r e s s
A 2 A 1 A 0
R / W
A C K
Byte write timing
D e v i c e a d d r e s s W o r d a d d r e s s D A T A n
S
S D A
S t a r t
A C K
A C K
D A T A n + 1 D A T A n + x
A C K
P
A C K
S t o p
Page write timing
Rev. 1.20 4 November 4, 2002
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