Rainbow Electronics HT24LC04 User Manual
CMOS 4K 2-Wire Serial EEPROM
Features
·
Operating voltage: 2.2V~5.5V
·
Low power consumption
-
Operation: 5mA max.
-
Standby: 5mA max.
·
Internal organization: 512´8
·
2-wire serial interface
·
Write cycle time: 5ms max.
·
Automatic erase-before-write operation
General Description
The HT24LC04 is a 4K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 4096 bits of memory are organized into 512 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
Block Diagram Pin Assignment
·
Partial page write allowed
·
16-byte page write modes
·
Write operation with built-in timer
·
Hardware controlled write protection
·
40-year data retention
·
106erase/write cycles per word
·
Commerical temperature range (0°Cto+70°C)
·
8-pin DIP/SOP package
low power and low voltage operation are essential. Up
to four HT24LC04 devices may be connected to the
same two-wire bus. The HT24LC04 is guaranteed for
1M erase/write cycles and 40-year data retention.
HT24LC04
S C L
S D A
A 0 ~ A 2
V C C
V S S
1
I / O
C o n t r o l
L o g i c
M e m o r y
W P
C o n t r o l
L o g i c
A d d r e s s
C o u n t e r
H V P u m p
X
E E P R O M
D
A r r a y
E
C
P a g e B u f
Y D E C
S e n s e A M P
R / W C o n t r o l
A 0
2
A 1
3
A 2
4
V S S
H T 2 4 L C 0 4
8 D I P - A / S O P - A
8
V C C
7
W P
6
S C L
5
S D A
Rev. 1.20 1 November 5, 2002
HT24LC04
Pin Description
Pin No. Pin Name I/O Description
1~3 A0~A2 I Address inputs
4 VSS
5 SDA I/O Serial data inputs/output
6 SCL I Serial clock data input
7 WP I Write protect
8 VCC
Absolute Maximum Ratings
Operating Temperature (Commercial) ........................................................................................................ 0°Cto70°C
Storage Temperature ............................................................................................................................-50°Cto125°C
Applied V
Applied Voltage on any Pin with Respect to VSS
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
Voltage with Respect to VSS ..................................................................................VSS-0.3V to VCC+6.0V
CC
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
Negative power supply
¾
Positive power supply
¾
.................................................................................................VSS
-0.3V to VCC+0.3V
-
D.C. Characteristics
Symbol Parameter
V
I
CC1
I
CC2
V
V
V
I
LI
I
LO
I
STB1
I
STB2
C
C
CC
IL
IH
OL
IN
OUT
Operating Voltage
Operating Current 5V Read at 100kHz
Operating Current 5V Write at 100kHz
Input Low Voltage
Input High Voltage
Output Low Voltage 2.4V
Input Leakage Current 5V
Output Leakage Current 5V
Standby Current 5V
Standby Current 2.4V
Input Capacitance (See Note)
Output Capacitance (See Note)
Note: These parameters are periodically sampled but not 100% tested
Test Conditions
V
CC
Conditions
¾¾
¾¾ -1 ¾
¾¾
=2.1mA
I
OL
=0 or V
V
IN
=0 or V
V
OUT
=0 or V
V
IN
=0 or V
V
IN
f=1MHz 25
¾
f=1MHz 25
¾
CC
CC
CC
Ta=0°Cto70°C
Min. Typ. Max. Unit
2.2
¾
¾¾
¾¾
0.7V
CC
¾
¾¾
¾¾
CC
¾¾
¾¾
¾¾
C
°
C
°
¾¾
¾¾
5.5 V
2mA
5mA
0.3V
V
CC
+0.5
CC
V
V
0.4 V
1
1
5
4
mA
mA
mA
mA
6pF
8pF
Rev. 1.20 2 November 5, 2002
HT24LC04
A.C. Characteristics
Symbol Parameter
f
SK
t
HIGH
t
LOW
t
R
t
F
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
t
BUF
t
SP
t
WR
Clock Frequency
Clock High Time 4000
Clock Low Time 4700
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time 4000
START Condition Setup Time 4000
Data Input Hold Time 0
Data Input Setup Time 200
STOP Condition Setup Time 4000
Output Valid from Clock
Bus Free Time 4700
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
Standard Mode*
Min. Max. Min. Max.
¾
100
¾
¾
1000
¾
¾
300
¾
¾
¾
¾
¾
3500
¾
¾
¾
¾
100
5
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means V
=2.2V to 5.5V
CC
For relative timing, refer to timing diagrams
V
CC
¾
600
1200
¾
¾
600
600
0
100
600
¾
1200
¾
¾
=5V±10%
Ta=0°Cto70°C
Unit Remark
400 kHz
ns
¾
ns
¾
¾
¾
¾
300 ns Note
300 ns Note
¾
¾
¾
¾
¾
900 ns
clock pulse is generated
Only relevant for repeated
ns
START condition
ns
ns
ns
¾
¾
¾
¾
After this period the first
ns
Time in which the bus
ns
¾
must be free before a new
transmission can start
50 ns Noise suppression time
5ms
¾
Functional Description
·
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
·
A0, A1, A2
The HT24LC04 uses the A2 and A1 inputs for hard
wire addressing and a total of four 4K devices may be
addressed on a single bus system. The A0 pin is not
connected. (The device addressing is discussed in
detail under the Device Addressing section).
·
Write protect (WP)
The HT24LC04 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
Rev. 1.20 3 November 5, 2002
V
. When the write protect pin is connected to Vcc,
SS
the write protection feature is enabled and operates
as shown in the following table.
WP Pin Status Protect Array
At V
At V
CC
SS
Full Array (4K)
Normal Read/Write Operations
Memory organization
·
HT24LC04, 4K Serial EEPROM
Internally organized with 512 8-bit words, random
word addressing requires a 9-bit data word address.
Device operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
HT24LC04
·
Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re
fer to Start and Stop Definition Timing Diagram).
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re
ceived each word. This happens during the ninth
clock cycle.
D a t a a l l o w e d
t o c h a n g e
S D A
S C L
S t a r t
c o n d i t i o n
A d d r e s s o r
a c k n o w l e d g e
v a l i d
S t o p
c o n d i t i o n
Device addressing
The 4K EEPROM devices require an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to diagram showing the
Device Address). This is common to all the EEPROM
device.
The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits
must compare to their corresponding hard-wired input
pins.
The 4K EEPROM only use the A2 and A1 device ad
dress bits with the third bit as a memory page address
bit. The two device address bits must compare to their
corresponding hardwired input pins. The A0 pin is not
connected.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
-
1 0
D e v i c e A d d r e s s
Write operations
·
Byte write
-
A write operation requires an 8-bit data word address
following the device address word and acknowledg
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
·
Page write
The 4K device is capable of 16-byte page writes.
A page write is initiated the same as byte write, but the
microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the
EEPROM acknowledges the receipt of the first data
word, the microcontroller can transmit up to fifteen
more data words. The EEPROM will respond with a
zero after each data word received. The
microcontroller must terminate the page write sequence with a stop condition.
The dataword address lower four bits are internallyin
cremented following the receipt of each data word.
The higher data word address bits are not incre
mented, retaining the memory page row location (re
fer to Page write timing).
R / W1 0 A 2 A 1 A 0
-
-
-
-
-
D e v i c e a d d r e s s W o r d a d d r e s s D A T A
S D A
S t a r t
A 1 A 0S P
A 2
R / W
A C K
A C K A C K
S t o p
Byte write timing
A C K
D A T A n
D A T A n + 1 D A T A n + x
P
A C K A C K
S t o p
D e v i c e a d d r e s s W o r d a d d r e s s
S D A
S
S t a r t
A C K
Page write timing
Rev. 1.20 4 November 5, 2002
Loading...