Rainbow Electronics HT24LC02 User Manual
CMOS 2K 2-Wire Serial EEPROM
Features
·
Operating voltage: 2.2V~5.5V
·
Low power consumption
-
Operation: 5mA max.
-
Standby: 5mA max.
·
Internal organization: 256´8
·
2-wire serial interface
·
Write cycle time: 5ms max.
·
Automatic erase-before-write operation
General Description
The HT24LC02 is a 2K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 2048 bits of memory are organized into 256 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
Block Diagram Pin Assignment
·
Partial page write allowed
·
8-byte Page write modes
·
Write operation with built-in timer
·
Hardware controlled write protection
·
40-year data retention
·
106erase/write cycles per word
·
Commerical temperature range (0°Cto+70°C)
·
8-pin DIP/SOP/TSSOP package
low power and low voltage operation are essential. Up
to eight HT24LC02 devices may be connected to the
same 2-wire bus. The HT24LC02 is guaranteed for 1M
erase/write cycles and 40-year data retention.
HT24LC02
S C L
S D A
W P
A 0 ~ A 2
V C C
V S S
I / O
C o n t r o l
L o g i c
M e m o r y
C o n t r o l
L o g i c
A d d r e s s
C o u n t e r
H V P u m p
X
D
E E P R O M
E
A r r a y
C
P a g e B u f
Y D E C
S e n s e A M P
R / W C o n t r o l
Pin Description
Pin Name I/O Description
A0~A2 I Address inputs
SDA I/O Serial data inputs/output
SCL I Serial clock data input
WP I Write protect
VSS
VCC
Negative power supply, ground
¾
Positive power supply
¾
V S S
A 0
1
A 1
2
A 2
3
4
V C C
8
W P
7
S C L
6
S D A
5
H T 2 4 L C 0 2
8 D I P - A / S O P - A / T S S O P - A
Rev. 1.10 1 November 5, 2002
HT24LC02
Absolute Maximum Ratings
Operating Temperature (Commercial)..........................................................................................................0°Cto70°C
Storage Temperature.............................................................................................................................-50°Cto125°C
Applied VCC Voltage with Respect toVSS ................................................................................................-0.3V to 6.0V
Applied Voltage on any Pin withRespect to VSS ..............................................................................-0.3V to V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
CC
+0.3V
-
D.C. Characteristics
Symbol Parameter
V
I
CC1
I
CC2
V
V
V
I
LI
I
LO
I
STB1
I
STB2
C
C
CC
IL
IH
OL
IN
OUT
Operating Voltage
Operating Current 5V Read at 100kHz
Operating Current 5V Write at 100kHz
Input Low Voltage
Input High Voltage
Output Low Voltage 2.4V
Input Leakage Current 5V
Output Leakage Current 5V
Standby Current 5V
Standby Current 2.4V
Input Capacitance (See Note)
Output Capacitance (See Note)
Note: These parameters are periodically sampled but not 100% tested
Test Conditions
V
CC
Conditions
¾¾
¾¾ -1 ¾
¾¾
=2.1mA
I
OL
=0 or V
V
IN
V
OUT
V
IN
V
IN
=0 or V
=0 or V
=0 or V
CC
CC
CC
CC
¾ f=1MHz 25°C ¾¾
¾ f=1MHz 25°C ¾¾
Ta=0°Cto70°C
Min. Typ. Max. Unit
2.2
¾
¾¾
¾¾
0.7V
CC
¾
¾¾
¾¾
¾¾
¾¾
¾¾
5.5 V
2mA
5mA
0.3V
CC
V
+0.5
CC
0.4 V
1
1
5
4
6pF
8pF
V
V
mA
mA
mA
mA
Rev. 1.10 2 November 5, 2002
HT24LC02
A.C. Characteristics
Symbol Parameter Remark
f
SK
t
HIGH
t
LOW
t
r
t
f
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time Note
SDA and SCL Fall Time Note
¾¾
¾
¾
After this period the
t
HD:STA
START Condition Hold Time
first clock pulse is
generated
Only relevant for
t
SU:STA
START Condition Setup Time
repeated START
condition
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
Data Input Hold Time
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
¾
¾
¾
¾¾
Time in which the bus
t
BUF
Bus Free Time
must be free before a
new transmission can
start
t
SP
t
WR
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
Noise suppression
time
¾¾5¾
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means V
=2.2V to 5.5V
CC
For relative timing, refer to timing diagrams
Standard Mode*
Ta=0°Cto70°C
V
=5V±10%
CC
Min. Max. Min. Max.
4000
4700
¾
¾
4000
4000
0
200
4000
4700
¾
100
¾
¾
1000
300
¾
¾
¾
¾
¾
3500
¾
100
¾
600
1200
¾
¾
600
600
100
600
¾
1200
¾
0
400 kHz
¾
¾
300 ns
300 ns
¾
¾
¾
¾
¾
900 ns
¾
50 ns
5ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.10 3 November 5, 2002
Functional Description
HT24LC02
·
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
·
A0, A1, A2
The A2, A1 and A0 pins are device address inputs that
are hard wired for the HT24LC02. As many as eight
2K devices may be addressed on a single bus system
(the device addressing is discussed in detail under the
Device Addressing section).
·
Write protect (WP)
The HT24LC02 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
V
. When the write protect pin is connected to Vcc,
SS
the write protection feature is enabled and operates
as shown in the following table.
WP Pin
Status
At V
CC
At V
SS
Full Array (2K)
Normal Read/Write Operations
Protect Array
Memory organization
·
HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words, the 2K requires an 8-bit data word address for random word ad
dressing.
Device operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re
fer to Start and Stop Definition Timing Diagram).
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re
ceived each word. This happens during the ninth clock
cycle.
D a t a a l l o w e d
t o c h a n g e
S D A
S C L
S t a r t
c o n d i t i o n
A d d r e s s o r
a c k n o w l e d g e
v a l i d
Device addressing
The 2K EEPROM devices all require an 8-bit device ad
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must
compare to their corresponding hard-wired input pins.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
-
1 0
D e v i c e A d d r e s s
Write operations
·
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
-
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
S t o p
c o n d i t i o n
R / W1 0 A 2 A 1 A 0
-
-
-
-
Rev. 1.10 4 November 5, 2002
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