HD44780U (LCD-II)
(Dot Matrix Liquid Crystal Display Controller/Driver)
Description
The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,
Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display
under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character
generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally
provided on one chip, a minimal system can be interfaced with this controller/driver.
A single HD44780U can display up to one 8-character line or two 8-character lines.
The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace
an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 208 5 ×
8 dot character fonts and 32 5 × 10 dot character fonts for a total of 240 different character fonts.
The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product
requiring low power dissipation.
Features
• 5 × 8 and 5 × 10 dot matrix possible
• Low power operation support:
2.7 to 5.5V
• Wide range of liquid crystal display driver power
3.0 to 11V
• Liquid crystal drive waveform
A (One line frequency AC waveform)
• Correspond to high speed MPU bus interface
2 MHz (when VCC = 5V)
• 4-bit or 8-bit MPU interface enabled
• 80 × 8-bit display RAM (80 characters max.)
• 9,920-bit character generator ROM for a total of 240 character fonts
208 character fonts (5 × 8 dot)
32 character fonts (5 × 10 dot)
1
HD44780U
• 64 × 8-bit character generator RAM
8 character fonts (5 × 8 dot)
4 character fonts (5 × 10 dot)
• 16-common × 40-segment liquid crystal display driver
• Programmable duty cycles
1/8 for one line of 5 × 8 dots with cursor
1/11 for one line of 5 × 10 dots with cursor
1/16 for two lines of 5 × 8 dots with cursor
• Wide range of instruction functions:
Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift,
display shift
• Pin function compatibility with HD44780S
• Automatic reset circuit that initializes the controller/driver after power on
• Internal oscillator with external resistors
• Low power consumption
Ordering Information
Type No. Package CGROM
HD44780UA00FS
HCD44780UA00
HD44780UA00TF
HD44780UA02FS
HCD44780UA02
HD44780UA02TF
HD44780UBxxFS
HCD44780UBxx
HD44780UBxxTF
Note: xx: ROM code No.
FP-80B
Chip
TFP-80F
FP-80B
Chip
TFP-80F
FP-80B
Chip
TFP-80F
Japanese standard font
European standard font
Custom font
2
HD44780U Block Diagram
HD44780U
RS
R/W
E
DB4 to
DB7
DB0 to
DB3
Reset
circuit
ACL
MPU
inter-
face
Input/
output
buffer
Instruction
register (IR)
8
Instruction
decoder
7
Data
8
register
(DR)
Busy
flag
OSC1 OSC2
CPG
Address
counter
7
8 8
Display
data RAM
(DDRAM)
80 × 8 bits
7
8
8
7
Timing
generator
40-bit
shift
register
40
16-bit
shift
register
40-bit
latch
circuit
Common
signal
driver
Segment
signal
driver
LCD drive
voltage
selector
CL1
CL2
M
D
COM1 to
COM16
SEG1 to
SEG40
GND
V
CC
Character
generator
Character
generator
RAM
(CGRAM)
64 bytes
(CGROM)
9,920 bits
Parallel/serial converter
V1 V2 V3 V4 V5
ROM
controller
55
and
attribute circuit
Cursor
and
blink
3
HD44780U
HD44780U Pin Arrangement (FP-80B)
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
807978777675747372717069686766
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
65
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
GND
OSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FP-80B
(Top view)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG39
SEG40
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DB7
DB6
DB5
DB4
DB3
DB2
252627282930313233343536373839
D
V1V2V3V4V5
OSC2
CL1
CL2
V
CC
M
RS
R/W
40
E
DB0
DB1 SEG38
4
HD44780U Pin Arrangement (TFP-80F)
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
80797877767574737271706968676665646362
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
61
HD44780U
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21222324252627282930313233343536373839
V1V2V3V4V5
GND
OSC1
OSC2
TFP-80F
(Top view)
CC
V
CL1
CL2
40
RS
R/W
E
DB0
DB1
DB2
DB3
D
M
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DB7
DB6
DB5
DB4
5
HD44780U
HD44780U Pad Arrangement
Chip size:
Coordinate:
Origin:
Pad size:
2 1 80 63
Y
4.90 × 4.90 mm
Pad center (µm)
Chip center
114 × 114 µm
Type code
2
2
23
HD44780U
42
X
6
HD44780U
HCD44780U Pad Location Coordinates
Coordinate Coordinate
Pad No. Function X (um) Y (um) Pad No. Function X (um) Y (um)
1 SEG22 –2100 2313 41 DB2 2070 –2290
2 SEG21 –2280 2313 42 DB3 2260 –2290
3 SEG20 –2313 2089 43 DB4 2290 –2099
4 SEG19 –2313 1833 44 DB5 2290 –1883
5 SEG18 –2313 1617 45 DB6 2290 –1667
6 SEG17 –2313 1401 46 DB7 2290 –1452
7 SEG16 –2313 1186 47 COM1 2313 –1186
8 SEG15 –2313 970 48 COM2 2313 –970
9 SEG14 –2313 755 49 COM3 2313 –755
10 SEG13 –2313 539 50 COM4 2313 –539
11 SEG12 –2313 323 51 COM5 2313 –323
12 SEG11 –2313 108 52 COM6 2313 –108
13 SEG10 –2313 –108 53 COM7 2313 108
14 SEG9 –2313 –323 54 COM8 2313 323
15 SEG8 –2313 –539 55 COM9 2313 539
16 SEG7 –2313 –755 56 COM10 2313 755
17 SEG6 –2313 –970 57 COM11 2313 970
18 SEG5 –2313 –1186 58 COM12 2313 1186
19 SEG4 –2313 –1401 59 COM13 2313 1401
20 SEG3 –2313 –1617 60 COM14 2313 1617
21 SEG2 –2313 –1833 61 COM15 2313 1833
22 SEG1 –2313 –2073 62 COM16 2313 2095
23 GND –2280 –2290 63 SEG40 2296 2313
24 OSC1 –2080 –2290 64 SEG39 2100 2313
25 OSC2 –1749 –2290 65 SEG38 1617 2313
26 V1 –1550 –2290 66 SEG37 1401 2313
27 V2 –1268 –2290 67 SEG36 1186 2313
28 V3 –941 –2290 68 SEG35 970 2313
29 V4 –623 –2290 69 SEG34 755 2313
30 V5 –304 –2290 70 SEG33 539 2313
31 CL1 –48 –2290 71 SEG32 323 2313
32 CL2 142 –2290 72 SEG31 108 2313
33 V
34 M 475 –2290 74 SEG29 –323 2313
35 D 665 –2290 75 SEG28 –539 2313
36 RS 832 –2290 76 SEG27 –755 2313
37 R/W 1022 –2290 77 SEG26 –970 2313
38 E 1204 –2290 78 SEG25 –1186 2313
39 DB0 1454 –2290 79 SEG24 –1401 2313
40 DB1 1684 –2290 80 SEG23 –1617 2313
CC
309 –2290 73 SEG30 –108 2313
7
HD44780U
Pin Functions
No. of
Signal
RS 1 I MPU Selects registers.
R/W 1 I MPU Selects read or write.
E 1 I MPU Starts data read/write.
DB4 to DB7
DB0 to DB3 4 I/O MPU Four low order bidirectional tristate data bus pins.
CL1 1 O Extension driver Clock to latch serial data D sent to the extension
CL2 1 O Extension driver Clock to shift serial data D
M 1 O Extension driver Switch signal for converting the liquid crystal
D 1 O Extension driver Character pattern data corresponding to each
COM1 to COM16 16 O LCD Common signals that are not used are changed
SEG1 to SEG40 40 O LCD Segment signals
V1 to V5 5 — Power supply Power supply for LCD drive
VCC, GND 2 — Power supply VCC: 2.7V to 5.5V, GND: 0V
OSC1, OSC2 2 — Oscillation
Lines I/O
4 I/O MPU Four high order bidirectional tristate data bus
Device
Interfaced with Function
0: Instruction register (for write) Busy flag:
address counter (for read)
1: Data register (for write and read)
0: Write
1: Read
pins. Used for data transfer and receive between
the MPU and the HD44780U. DB7 can be used
as a busy flag.
Used for data transfer and receive between the
MPU and the HD44780U.
These pins are not used during 4-bit operation.
driver
drive waveform to AC
segment signal
to non-selection waveforms. COM9 to COM16
are non-selection waveforms at 1/8 duty factor
and COM12 to COM16 are non-selection
waveforms at 1/11 duty factor.
V
–V5 = 11 V (max)
CC
When crystal oscillation is performed, a resistor
resistor clock
must be connected externally. When the pin input
is an external clock, it must be input to OSC1.
8
HD44780U
Function Description
Registers
The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for display
data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU.
The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be
read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into
DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data
from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored
into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then
completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is
sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can
be selected (Table 1).
Busy Flag (BF)
When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not
be accepted. When RS = 0 and R/ W = 1 (Table 1), the busy flag is output to DB7. The next instruction
must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either
DDRAM or CGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1
(decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 1).
Table 1 Register Selection
RS R/W Operation
0 0 IR write as an internal operation (display clear, etc.)
0 1 Read busy flag (DB7) and address counter (DB0 to DB6)
1 0 DR write as an internal operation (DR to DDRAM or CGRAM)
1 1 DR read as an internal operation (DDRAM or CGRAM to DR)
9
HD44780U
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended
capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for
display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses
and positions on the liquid crystal display.
The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal.
• 1-line display (N = 0) (Figure 2)
When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the HD44780, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
AC
(hexadecimal)
Display position
(digit)
DDRAM
address
(hexadecimal)
High order
bits
AC6AC5 AC4 AC3AC2 AC1AC0
Low order
bits
Figure 1 DDRAM Address
123 45 7980
00 01 02 03 04 4E 4F
Figure 2 1-Line Display
Display
position
DDRAM
address
For
shift left
For
shift right
12345678
00 01 02 03 04 05 06 07
01 02 03 04 05 06 07 08
00 01 02 03 04 05 06
4F
Example: DDRAM address 4E
1001110
. . . . . . . . . . . . . . . . . .
10
Figure 3 1-Line by 8-Character Display Example
HD44780U
• 2-line display (N = 1) (Figure 4)
Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed
from the head. Note that the first line end address and the second line start address are not
consecutive. For example, when just the HD44780 is used, 8 characters × 2 lines are displayed. See
Figure 5.
When display shift operation is performed, the DDRAM address shifts. See Figure 5.
Display
position
DDRAM
address
(hexadecimal)
123 45 3940
00 01 02 03 04 26 27
40 41 42 43 44 66 67
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
Figure 4 2-Line Display
Display
position
DDRAM
address
For
shift left
For
shift right
12345678
00 01 02 03 04 05 06 07
40 41 42 43 44 45 46 47
01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48
00 01 02 03 04 05 06
27
40 41 42 43 44 45 46
67
Figure 5 2-Line by 8-Character Display Example
11
HD44780U
Case 2: For a 16-character × 2-line display, the HD44780 can be extended using one 40-output
extension driver. See Figure 6.
When display shift operation is performed, the DDRAM address shifts. See Figure 6.
Display
position
DDRAM
address
For
shift left
For
shift right
1 2345678910111213141516
00 01 02 03 04 05 06 07 08 09 0A 0B0C0D0E0F
40 41 42 43 44 45 46 47 48 49 4A 4B4C4D4E4F
HD44780U display Extension driver
display
0201 0304 05 06 07 08 09 0A 0B0C0D0E0F10
4142 43 44 45 46 47 48 49 4A 4B4C4D4E 4F 50
00 01 02 03 04 05 06 07 08 09 0A 0B0C0D0E27
40 41 42 43 44 45 46 47 48 49 4A 4B4C4D4E67
Figure 6 2-Line by 16-Character Display Example
12
HD44780U
Character Generator ROM (CGROM)
The character generator ROM generates 5 × 8 dot or 5 × 10 dot character patterns from 8-bit character
codes (Table 4). It can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns. Userdefined character patterns are also available by mask-programmed ROM.
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 × 8 dots, eight
character patterns can be written, and for 5 × 10 dots, four character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the
character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns.
Areas that are not used for display can be used as general data RAM.
Modifying Character Patterns
• Character pattern development procedure
The following operations correspond to the numbers listed in Figure 7:
1. Determine the correspondence between character codes and character patterns.
2. Create a listing indicating the correspondence between EPROM addresses and data.
3. Program the character patterns into the EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which
is sent to the user.
6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples
are sent to the user for evaluation. When it is confirmed by the user that the character patterns are
correctly written, mass production of the LSI proceeds at Hitachi.
13
HD44780U
UserHitachi
Start
Computer
processing
Create character
pattern listing
No
Evaluate
character
patterns
OK?
Yes
Art work
M/T
Masking
Trial
Determine
character patterns
5
Create EPROM
address data listing
Write EPROM
EPROM → Hitachi
1
2
3
4
14
Sample
Sample
evaluation
OK?
Yes
Mass
production
Note: For a description of the numbers used in this figure, refer to the preceding page.
6
No
Figure 7 Character Pattern Development Procedure
HD44780U
• Programming character patterns
This section explains the correspondence between addresses and data used to program character patterns
in EPROM. The HD44780U character generator ROM can generate 208 5 × 8 dot character patterns and
32 5 × 10 dot character patterns for a total of 240 different character patterns.
Character patterns
EPROM address data and character pattern data correspond with each other to form a 5 × 8 or 5 ×
10 dot character pattern (Tables 2 and 3).
Table 2 Example of Correspondence between EPROM Address Data and Character Pattern
(5 × 8 Dots)
EPROM Address
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A11
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 0 0 0 1 0
Character code
Notes: 1. EPROM addresses A11 to A4 correspond to a character code.
2. EPROM addresses A3 to A0 specify a line position of the character pattern.
3. EPROM data O4 to O0 correspond to character pattern data.
4. EPROM data O5 to O7 must be specified as 0.
5. A lit display position (black) corresponds to a 1.
6. Line 9 and the following lines must be blanked with 0s for a 5 × 8 dot character fonts.
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Line
position
O4 O3 O2 O1 O0
Data
LSB
1 0 0 0 0
1 0 0 0 0
1 0 1 1 0
1 1 0 0 1
1 0 0 0 1
1 0 0 0 1
1 1 1 1 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Cursor position
15
HD44780U
Handling unused character patterns
1. EPROM data outside the character pattern area: Always input 0s.
2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.)
3. EPROM data used when the user does not use any HD44780U character pattern: According to the user
application, handled in one of the two ways listed as follows.
a. When unused character patterns are not programmed: If an unused character code is written into
DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is
due to the EPROM being filled with 1s after it is erased.)
b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused
character codes are written into DDRAM. (This is equivalent to a space.)
Table 3 Example of Correspondence between EPROM Address Data and Character Pattern
(5 × 10 Dots)
EPROM Address
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A11
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 0 1 0 0 1 0
Character code
Notes: 1. EPROM addresses A11 to A3 correspond to a character code.
2. EPROM addresses A3 to A0 specify a line position of the character pattern.
3. EPROM data O4 to O0 correspond to character pattern data.
4. EPROM data O5 to O7 must be specified as 0.
5. A lit display position (black) corresponds to a 1.
6. Line 11 and the following lines must be blanked with 0s for a 5 × 10 dot character fonts.
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Line
position
Data
LSB
O4 O3 O2 O1 O0
0 0 0 0 0
0 0 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 0 0 1
1 0 0 0 1
0 1 1 1 1
0 0 0 0 1
0 0 0 0 1
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Cursor position
16
HD44780U
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A00)
Upper 4
Lower
4 Bits
xxxx0000
Bits
0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
0001 1000 1001
CG
RAM
(1)
xxxx0001
xxxx0010
xxxx0011
xxxx0100
xxxx0101
xxxx0110
xxxx0111
xxxx1000
xxxx1001
xxxx1010
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(2)
(3)
xxxx1011
xxxx1100
xxxx1101
xxxx1110
xxxx1111
(4)
(5)
(6)
(7)
(8)
Note: The user can specify any pattern for character-generator RAM.
17
HD44780U
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A02)
Upper 4
Lower
4 Bits
xxxx0000
0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
Bits
0001 1000 1001
CG
RAM
(1)
xxxx0001
xxxx0010
xxxx0011
xxxx0100
xxxx0101
xxxx0110
xxxx0111
xxxx1000
xxxx1001
xxxx1010
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(2)
(3)
xxxx1011
xxxx1100
xxxx1101
xxxx1110
xxxx1111
18
(4)
(5)
(6)
(7)
(8)
HD44780U
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
Patterns (CGRAM Data)
For 5
× 8 dot character patterns
Character Codes
(DDRAM data)
76543210
High Low High Low High Low
0000
0000
0000
*000
*001
*111
CGRAM Address
543210
0
0
0
0
0
1
0
1
0
0
1
000
001
111
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Character Patterns
(CGRAM data)
76543210
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
0
1
0
1
1
1
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
0
Character
pattern (1)
Cursor position
Character
pattern (2)
Cursor position
Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor.
Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display.
If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be
selected by either character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
* Indicates no effect.
19
HD44780U
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
Patterns (CGRAM Data) (cont)
× 10 dot character patterns
For 5
Character Codes
(DDRAM data)
76543210
High Low High Low High Low
0000
0000 11
*00
**
*
CGRAM Address
543210
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
00
11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
Character Patterns
(CGRAM data)
76543210
*
*
*
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
*
*
*
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Character
pattern
Cursor position
Notes: 1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types).
2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the
cursor position and its display is formed by a logical OR with the cursor.
Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display.
If the 11th line data is „1“, „1“ bits will light up the 11th line regardless of the cursor presence.
Since lines 12 to 16 are not used for display, they can be used for general data RAM.
3. Character pattern row positions are the same as 5 × 8 dot character pattern positions.
4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bits 0 and 3 have no effect, the P display example above can be
selected by character codes 00H, 01H, 08H, and 09H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
* Indicates no effect.
20
HD44780U
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the
display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal
drivers. When the character font and number of lines are selected by a program, the required common
signal drivers automatically output drive waveforms, while the other common signal drivers continue to
output non-selection waveforms.
Sending serial data always starts at the display data character pattern corresponding to the last address of
the display data RAM (DDRAM).
Since serial data is latched when the display data character pattern corresponding to the starting address
enters the internal shift register, the HD44780U drives from the head display.
Cursor/Blink Control Circuit
The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will
appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC).
For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM
address 08H.
AC60AC50AC40AC31AC20AC10AC0
6
05
45
0
cursor position
8
7
07
06
47
46
cursor position
0A
9
10
11
08
09
0A
48
49
4A
AC
For a 1-line display
Display position
DDRAM address
(hexadecimal)
For a 2-line display
Display position
DDRAM address
(hexadecimal)
Note: The cursor or blinking appears when the address counter (AC) selects the character
generator RAM (CGRAM). However, the cursor and blinking become meaningless.
The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address.
100201302403504605706807908100911
1
2
3
4
5
00
01
02
03
04
40
41
42
43
44
Figure 8 Cursor/Blink Display Example
21
HD44780U
Interfacing to the MPU
The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing
interfacing with 4- or 8-bit MPUs.
• For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data
has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation,
DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3).
The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two
more 4-bit operations then transfer the busy flag and address counter data.
• For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
RS
R/W
E
DB7
DB6
DB5
DB4
IR7
IR6
IR5
IR4
Instruction register (IR)
write
IR3
IR2
IR1
IR0
Figure 9 4-Bit Transfer Example
BF
AC6
AC5
AC4
Busy flag (BF) and
address counter (AC)
read
AC3
AC2
AC1
AC0
DR7
DR6
DR5
DR4
Data register (DR)
read
DR3
DR2
DR1
DR0
22
HD44780U
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the HD44780U when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state
until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V.
1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
F = 0; 5 × 8 dot character font
3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to
initialize the HD44780U. For such a case, initial-ization must be performed by the MPU as
explained in the section, Initializing by Instruction.
Instructions
Outline
Only the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by the
MPU. Before starting the internal operation of the HD44780U, control information is temporarily stored
into these registers to allow interfacing with various MPUs, which operate at different speeds, or various
peripheral control devices. The internal operation of the HD44780U is determined by signals sent from the
MPU. These signals, which include register selection signal (RS), read/
write signal (R/W), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). There
are four categories of instructions that:
• Designate HD44780U functions, such as display format, data length, etc.
• Set internal RAM addresses
• Perform data transfer with internal RAM
• Perform miscellaneous functions
23
HD44780U
Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data
write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform
concurrently with display data write, the user can minimize system development time with maximum
programming efficiency.
When an instruction is being executed for internal operation, no instruction other than the busy flag/address
read instruction can be executed.
Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before
sending another instruction from the MPU.
Note: Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the
MPU to the HD44780U. If an instruction is sent without checking the busy flag, the time between
the first instruction and next instruction will take much longer than the instruction time itself. Refer
to Table 6 for the list of each instruc-tion execution time.
Table 6 Instructions
Code
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description f
Clear
display
Return
home
Entry
mode set
Display
on/off
control
Cursor or
display
shift
Function
set
Set
CGRAM
address
Set
DDRAM
address
Read busy
flag &
address
0000000001Clears entire display and
sets DDRAM address 0 in
address counter.
000000001—Sets DDRAM address 0 in
address counter. Also
returns display from being
shifted to original position.
DDRAM contents remain
unchanged.
00000001I/DSSets cursor move direction
and specifies display shift.
These operations are
performed during data write
and read.
0000001DCBSets entire display (D) on/off,
cursor on/off (C), and
blinking of cursor position
character (B).
0 0 0 0 0 1 S/C R/L — — Moves cursor and shifts
display without changing
DDRAM contents.
0 0 0 0 1 DL N F — — Sets interface data length
(DL), number of display lines
(N), and character font (F).
0 0 0 1 ACG ACG ACG ACG ACG ACG Sets CGRAM address.
CGRAM data is sent and
received after this setting.
0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address.
DDRAM data is sent and
received after this setting.
0 1 BF AC AC AC AC AC AC AC Reads busy flag (BF)
indicating internal operation
is being performed and
reads address counter
contents.
Execution Time
(max) (when fcp or
is 270 kHz)
OSC
1.52 ms
37 µs
37 µs
37 µs
37 µs
37 µs
37 µs
0 µs
24
Table 6 Instructions (cont)
HD44780U
Code
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description f
Write data
to CG or
DDRAM
Read data
from CG or
DDRAM
1 0 Write data Writes data into DDRAM or
1 1 Read data Reads data from DDRAM or
I/D = 1: Increment
I/D = 0: Decrement
S = 1: Accompanies display shift
S/C = 1: Display shift
S/C = 0: Cursor move
R/L = 1: Shift to the right
R/L = 0: Shift to the left
DL = 1: 8 bits, DL = 0: 4 bits
N = 1: 2 lines, N = 0: 1 line
F = 1: 5 × 10 dots, F = 0: 5 × 8 dots
BF = 1: Internally operating
BF = 0: Instructions acceptable
CGRAM.
CGRAM.
DDRAM: Display data RAM
CGRAM: Character generator
RAM
ACG: CGRAM address
ADD: DDRAM address
(corresponds to cursor
address)
AC: Address counter used for
both DD and CGRAM
addresses
Note: — indicates no effect.
* After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter
is incremented or decremented by 1. The RAM address counter is updated after the busy flag
turns off. In Figure 10, t
is the time elapsed after the busy flag turns off until the address
ADD
counter is updated.
Execution Time
(max) (when fcp or
is 270 kHz)
OSC
37 µs
t
= 4 µs*
ADD
37 µs
t
= 4 µs*
ADD
Execution time
changes when
frequency changes
Example:
When fcp or f
250 kHz,
37 µs × = 40 µs
270
250
OSC
is
Busy signal
Busy state
(DB7 pin)
Address counter
(DB0 to DB6 pins)
Note: t depends on the operation frequency
ADD
t = 1.5/(f or f ) seconds
ADD cp OSC
A A + 1
Figure 10 Address Counter Update
t
ADD
25
HD44780U
Instruction Description
Clear Display
Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into
all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to
its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to
the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode)
in entry mode. S of entry mode does not change.
Return Home
Return home sets DDRAM address 0 into the address counter, and returns the display to its original status
if it was shifted. The DDRAM contents do not change.
The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed).
Entry Mode Set
I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is
written into or read from DDRAM.
The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1.
The same applies to writing and reading of CGRAM.
S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does
not shift if S is 0.
If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when
reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display.
Display On/Off Control
D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but
can be displayed instantly by setting D to 1.
C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the
function of I/D or other specifications will not change during display data write. The cursor is displayed
using 5 dots in the 8th line for 5 × 8 dot character font selection and in the 11th line for the 5 × 10 dot
character font selection (Figure 13).
B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as
switching between all blank dots and displayed characters at a speed of 409.6-ms intervals when fcp or f
OSC
is 250 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes
according to f
or the reciprocal of fcp. For example, when fcp is 270 kHz, 409.6 × 250/270 = 379.2 ms.)
OSC
26
HD44780U
Cursor or Display Shift
Cursor or display shift shifts the cursor position or display to the right or left without writing or reading
display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor
moves to the second line when it passes the 40th digit of the first line. Note that the first and second line
displays will shift at the same time.
When the displayed data is shifted repeatedly each line moves only horizontally. The second line display
does not shift into the first line position.
The address counter (AC) contents will not change if the only action performed is a display shift.
Function Set
DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1,
and in 4-bit lengths (DB7 to DB4) when DL is 0.When 4-bit length is selected, data must be sent or
received twice.
N: Sets the number of display lines.
F: Sets the character font.
Note: Perform the function at the head of the program before executing any instructions (except for the
read busy flag and address instruction). From this point, the function set instruction cannot be
executed unless the interface data length is changed.
Set CGRAM Address
Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter.
Data is then written to or read from the MPU for CGRAM.
27
HD44780U
Clear
display
Code
RS0R/W0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0
1
RS0R/W0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0
Return
home
Entry
mode set
Display
on/off control
Cursor or
display shift
Function set
Set CGRAM
address
Code
Code
Code
Code
Code
*
RS0R/W0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1
RS0R/W0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0
RS0R/W0 DB7 0 DB6 0 DB5 0 DB4 1 DB3
RS0R/W0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 F DB1 DB0
RS0R/W0 DB7 0 DB6 1 DB5 A DB4 A DB3 A DB2 A DB1 DB0
Higher
order bit
DB2
S/CCode
R/L
order bit
DB0
I/D
DB1 DB0
*
**
AA
Lower
S
B
*
Note: Don’t care.*
Note: Don’t care.*
28
Figure 11 Instruction (1)
HD44780U
Set DDRAM Address
Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter.
Data is then written to or read from the MPU for DDRAM.
However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display),
AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line.
Read Busy Flag and Address
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating
on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction
will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same
time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by
both CG and DDRAM addresses, and its value is determined by the previous instruction. The address
contents are the same as for instructions set CGRAM address and set DDRAM address.
Table 7 Shift Function
S/C R/L
0 0 Shifts the cursor position to the left. (AC is decremented by one.)
0 1 Shifts the cursor position to the right. (AC is incremented by one.)
1 0 Shifts the entire display to the left. The cursor follows the display shift.
1 1 Shifts the entire display to the right. The cursor follows the display shift.
Table 8 Function Set
No. of
Display
NF
001 5 × 8 dots 1/8
011 5 × 10 dots 1/11
1*2 5 × 8 dots 1/16 Cannot display two lines for 5 × 10 dot character font
Note: * Indicates don’t care.
Lines Character Font
Duty
Factor Remarks
29
HD44780U
Cursor
5 8 dot
×× Alternating display
character font
5 10 dot
character font
Blink display exampleCursor display example
Figure 12 Cursor and Blinking
RS0R/W0DB71DB6ADB5ADB4ADB3
Set DDRAM
address
Higher
order bit
RS0R/W1DB7BFDB6ADB5ADB4ADB3
Read busy flag
and address
Higher
order bit
DB2ADB1ADB0
ACode
Lower
order bit
DB2ADB1ADB0
ACode
Lower
order bit
Figure 13 Instruction (2)
A
A
30
HD44780U
Write Data to CG or DDRAM
Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM.
To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM
address setting. After a write, the address is automatically incremented or decremented by 1 according to
the entry mode. The entry mode also determines the display shift.
Read Data from CG or DDRAM
Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM.
The previous designation determines whether CG or DDRAM is to be read. Before entering this read
instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first
read data will be invalid. When serially executing read instructions, the next address data is normally read
from the second read. The address set instructions need not be executed just before this read instruction
when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the
cursor shift instruction is the same as the set DDRAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1. However, display shift
is not executed regardless of the entry mode.
Note: The address counter (AC) is automatically incremented or decremented by 1 after the write
instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be
read out at this time even if read instructions are executed. Therefore, to correctly read data,
execute either the address set instruction or cursor shift instruction (only with DDRAM), then just
before reading the desired data, execute the read instruction from the second time the read
instruction is sent.
RS1R/W0DB7DDB6DDB5DDB4DDB3
Write data to
CG or DDRAM
Higher
order bits
RS1R/W1DB7DDB6DDB5DDB4DDB3
Read data from
CG or DDRAM
Higher
order bits
DB2DDB1DDB0
DCode
order bits
DB2DDB1DDB0
DCode
order bits
D
Lower
D
Lower
Figure 14 Instruction (3)
31
HD44780U
Interfacing the HD44780U
Interface to MPUs
• Interfacing to an 8-bit MPU
See Figure 16 for an example of using a I/O port (for a single-chip microcomputer) as an interface
device.
In this example, P30 to P37 are connected to the data bus DB0 to DB7, and P75 to P77 are connected to
E, R/W, and RS, respectively.
RS
R/W
E
Internal
operation
DB7
Functioning
Data Busy Busy
Instruction
write
Busy flag
check
Busy flag
check
Busy flag
check
Figure 15 Example of Busy Flag Check Timing Sequence
H8/325 HD44780U
P30 to P37
P77
P76
P75
8
DB0 to DB7
E
RS
R/W
COM1 to
COM16
SEG1 to
Figure 16 H8/325 Interface (Single-Chip Mode)
Not
busy
SEG40
Data
Instruction
write
16
LCD
40
32
HD44780U
• Interfacing to a 4-bit MPU
The HD44780U can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit
data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In
this case, the timing sequence becomes somewhat complex. (See Figure 17.)
See Figure 18 for an interface example to the HMCS4019R.
Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit
operation is selected by the program.
RS
R/W
E
Internal
operation
DB7
Note: IR7 , IR3 are the 7th and 3rd bits of the instruction.
AC3 is the 3rd bit of the address counter.
IR7 IR3 Busy AC3
Instruction
write
Functioning
Busy flag
check
Figure 17 Example of 4-Bit Data Transfer Timing Sequence
HMCS4019R HD44780
D15
D14
D13
4
R10 to R13
RS
R/W
E
DB4 to DB7
Not
busy
AC3 D7 D3
Busy flag
check
COM1 to
COM16
SEG1 to
SEG40
Instruction
write
16
LCD
40
Figure 18 Example of Interface to HMCS4019R
33
HD44780U
Interface to Liquid Crystal Display
Character Font and Number of Lines: The HD44780U can perform two types of displays, 5 × 8 dot and
5 × 10 dot character fonts, each with a cursor.
Up to two lines are displayed for 5 × 8 dots and one line for 5 × 10 dots. Therefore, a total of three
types of common signals are available (Table 9).
The number of lines and font types can be selected by the program. (See Table 6, Instructions.)
Connection to HD44780 and Liquid Crystal Display: See Figure 19 for the connection examples.
Table 9 Common Signals
Number of Lines Character Font Number of Common Signals Duty Factor
15 × 8 dots + cursor 8 1/8
15 × 10 dots + cursor 11 1/11
25 × 8 dots + cursor 16 1/16
HD44780
COM1
COM8
SEG1
SEG40
Example of a 5 × 8 dot, 8-character × 1-line display (1/4 bias, 1/8 duty cycle)
HD44780
COM1
COM11
SEG1
SEG40
Example of a 5 × 10 dot, 8-character × 1-line display (1/4 bias, 1/11 duty cycle)
34
Figure 19 Liquid Crystal Display and HD44780 Connections
HD44780U
Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1-line
display and 16 digits for a 2-line display.
The examples in Figure 19 have unused common signal pins, which always output non-selection
waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra
scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the
floating state.
HD44780
COM1
COM8
COM9
COM16
SEG1
SEG40
Example of a 5 × 8 dot, 8-character × 2-line display (1/5 bias, 1/16 duty cycle)
Figure 19 Liquid Crystal Display and HD44780 Connections (cont)
35
HD44780U
Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the
scanning lines. However, the following display examples (Figure 20) are made possible by altering the
matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display
characteristics and the number of liquid crystal display characters depend on the number of common
signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 4 characters × 2 lines
and for 16 characters × 1 line are the same as in Figure 19.
HD44780
COM1
COM8
SEG1
SEG40
COM9
COM16
5 × 8 dot, 16-character × 1-line display
(1/5 bias, 1/16 duty cycle)
Figure 20 Changed Matrix Layout Displays
36
HD44780U
Power Supply for Liquid Crystal Display Drive
Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal
display drive waveforms. The voltages must be changed according to the duty factor (Table 10).
VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides
voltages V1 to V5 (Figure 21).
Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive
Duty Factor
1/8, 1/11 1/16
Bias
Power Supply 1/4 1/5
V1 VCC–1/4 VLCD VCC–1/5 VLCD
V2 VCC–1/2 VLCD VCC–2/5 VLCD
V3 VCC–1/2 VLCD VCC–3/5 VLCD
V4 VCC–3/4 VLCD VCC–4/5 VLCD
V5 VCC–VLCD VCC–VLCD
V
CC
V1
V2
V3
V4
V5
1/4 bias
(1/8, 1/11 duty cycle)
(+5 V)
V
CC
V
CC
R
R
R
R
VR
–5 V
1/5 bias
(1/16, duty cycle)
V1
V2
V3
V4
V5
Figure 21 Drive Voltage Supply Example
VCC (+5 V)
R
R
R
R
R
VR
–5 V
VLCDVLCD
37
HD44780U
Relationship between Oscillation Frequency and Liquid Crystal Display Frame
Frequency
The liquid crystal display frame frequencies of Figure 22 apply only when the oscillation frequency is 270
kHz (one clock pulse of 3.7 µs).
1/8 duty cycle
COM1
V
CC
V1
V2 (V3)
V4
V5
1 frame = 3.7 µs × 400 × 8 = 11850 µs = 11.9 ms
Frame frequency = = 84.3 Hz
1/11 duty cycle
COM1
V
CC
V1
V2 (V3)
V4
V5
1 frame = 3.7 µs × 400 × 11 = 16300 µs = 16.3 ms
Frame frequency = = 61.4 Hz
1
1
2
1
11.9 ms
2
1
16.3 ms
400 clocks
3
1 frame
400 clocks
3
1 frame
4
4
11
8
1
2
1
2
38
1/16 duty cycle
COM1
V
CC
V1
V2
V3
V4
V5
1 frame = 3.7 µs × 200 × 16 = 11850 µs = 11.9 ms
Frame frequency = = 84.3 Hz
1
2
1
11.9 ms
200 clocks
3
1 frame
Figure 22 Frame Frequency
4
16
1
2
HD44780U
Instruction and Display Correspondence
• 8-bit operation, 8-digit × 1-line display with internal reset
Refer to Table 11 for an example of an 8-digit × 1-line display in 8-bit operation. The HD44780U
functions must be set by the function set instruction prior to the display. Since the display data RAM
can store data for 80 characters, as explained before, the RAM can be used for displays such as for
advertising when combined with the display shift operation.
Since the display shift operation changes only the display position with DDRAM contents unchanged,
the first display data entered into DDRAM can be output when the return home operation is performed.
• 4-bit operation, 8-digit × 1-line display with internal reset
The program must set all functions prior to the 4-bit operation (Table 12). When the power is turned on,
8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since
DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is completed in
two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 12). Thus, DB4 to
DB7 of the function set instruction is written twice.
• 8-bit operation, 8-digit × 2-line display
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit
of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM
address must be again set after the 8th character is completed. (See Table 13.) Note that the display shift
operation is performed for the first and second lines. In the example of Table 13, the display shift is
performed when the cursor is on the second line. However, if the shift operation is performed when the
cursor is on the first line, both the first and second lines move together. If the shift is repeated, the
display of the second line will not move to the first line. The same display will only shift within its own
line for the number of times the shift is repeated.
Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using
Internal Reset Circuit table must be satisfied. If not, the HD44780U must be initialized by
instructions. See the section, Initializing by Instruction.
39
HD44780U
Table 11 8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset
Step
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation
1 Power supply on (the HD44780U is initialized by the internal
reset circuit)
2 Function set
00001100**
3 Display on/off control
0000001110
4 Entry mode set
0000000110
5 Write data to CGRAM/DDRAM
1001001000
6 Write data to CGRAM/DDRAM
1001001001
7·
8 Write data to CGRAM/DDRAM
1001001001
9 Entry mode set
0000000111
10 Write data to CGRAM/DDRAM
1000100000
Instruction
·
·
·
·
Initialized. No display.
Sets to 8-bit operation and
selects 1-line display and 5 × 8
dot character font. (Number of
display lines and character
fonts cannot be changed after
step #2.)
_
_
H_
HI_
·
·
·
·
·
HITACHI_
HITACHI_
ITACHI _
Turns on display and cursor.
Entire display is in space mode
because of initialization.
Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CGRAM.
Display is not shifted.
Writes H. DDRAM has already
been selected by initialization
when the power was turned on.
The cursor is incremented by
one and shifted to the right.
Writes I.
Writes I.
Sets mode to shift display at
the time of write.
Writes a space.
40
HD44780U
Table 11 8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset (cont)
Step
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation
11 Write data to CGRAM/DDRAM
1001001101
12 ·
13 Write data to CGRAM/DDRAM
1001001111
14 Cursor or display shift
00000100**
15 Cursor or display shift
00000100**
16 Write data to CGRAM/DDRAM
1001000011
17 Cursor or display shift
00000111**
18 Cursor or display shift
00000101**
19 Write data to CGRAM/DDRAM
1001001101
20 ·
21 Return home
0000000010
Instruction
·
·
·
·
·
·
·
·
TACHI M_
·
·
·
·
·
MICROKO_
MICROKO _
MICROKO _
ICROCO _
MICROCO _
MICROCO_
ICROCOM_
·
·
·
·
·
HITACHI _
Writes M.
Writes O.
Shifts only the cursor position
to the left.
Shifts only the cursor position
to the left.
Writes C over K.
The display moves to the left.
Shifts the display and cursor
position to the right.
Shifts the display and cursor
position to the right.
Writes M.
Returns both display and
cursor to the original position
(address 0).
41
HD44780U
Table 12 4-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset
Step
No. RS R/W DB7 DB6 DB5 DB4 Display Operation
1 Power supply on (the HD44780U is initialized by the internal
reset circuit)
2 Function set
000010
3 Function set
000010
0000**
4 Display on/off control
000000
001110
5 Entry mode set
000000
000110
6 Write data to CGRAM/DDRAM
100100
101000
Instruction
_
_
H_
Initialized. No display.
Sets to 4-bit operation.
In this case, operation is
handled as 8 bits by initialization, and only this instruction
completes with one write.
Sets 4-bit operation and
selects 1-line display and 5 × 8
dot character font. 4-bit
operation starts from this step
and resetting is necessary.
(Number of display lines and
character fonts cannot be
changed after step #3.)
Turns on display and cursor.
Entire display is in space mode
because of initialization.
Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CGRAM.
Display is not shifted.
Writes H.
The cursor is incremented by
one and shifts to the right.
Note: The control is the same as for 8-bit operation beyond step #6.
42
Table 13 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset
HD44780U
Step
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation
1 Power supply on (the HD44780U is initialized by the internal
reset circuit)
2 Function set
00001110**
3 Display on/off control
0000001110
4 Entry mode set
0000000110
5 Write data to CGRAM/DDRAM
1001001000
6·
7 Write data to CGRAM/DDRAM
1001001001
Instruction
·
·
·
·
Initialized. No display.
Sets to 8-bit operation and
selects 2-line display and 5 × 8
dot character font.
_
_
H_
·
·
·
·
·
HITACHI_
Turns on display and cursor.
All display is in space mode
because of initialization.
Sets mode to increment the
address by one and to shift the
cursor to the right at the time of
write to the DD/CGRAM.
Display is not shifted.
Writes H. DDRAM has already
been selected by initialization
when the power was turned on.
The cursor is incremented by
one and shifted to the right.
Writes I.
8 Set DDRAM address
0011000000
HITACHI
_
Sets DDRAM address so that
the cursor is positioned at the
head of the second line.
43
HD44780U
Table 13 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset (cont)
Step
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation
9 Write data to CGRAM/DDRAM
1001001101
10 ·
11 Write data to CGRAM/DDRAM
1001001111
12 Entry mode set
0000000111
13 Write data to CGRAM/DDRAM
1001001101
14 ·
15 Return home
0000000010
Instruction
·
·
·
·
·
·
·
·
HITACHI
M_
·
·
·
·
·
HITACHI
MICROCO_
HITACHI
MICROCO_
ITACHI
ICROCOM_
·
·
·
·
·
HITACHI
_
MICROCOM
Writes M.
Writes O.
Sets mode to shift display at
the time of write.
Writes M. Display is shifted to
the left. The first and second
lines both shift at the same
time.
Returns both display and
cursor to the original position
(address 0).
44
HD44780U
Initializing by Instruction
If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by
instructions becomes necessary.
Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively.
Power on
Wait for more than 15 ms
after VCC rises to 4.5 V
RS0R/W0DB7 0DB6 0DB5 1DB4 1DB3DB2 DB1 DB0
****
Wait for more than 4.1 ms
RS0R/W0DB7 0DB6 0DB51DB4 1DB3DB2 DB1 DB0
****
Wait for more than 100 µs
RS0R/W0DB7 0DB6 0DB5 1DB4 1DB3DB2 DB1
***
RS0R/W0DB7 0DB6 0DB5 1DB4 1DB3 NDB2FDB1DB0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DB0
*
**
0
0
0
1
I/D
S
Wait for more than 40 ms
after V
rises to 2.7 V
CC
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See Table 6.)
Function set (Interface is 8 bits long. Specify the
number of display lines and character font.)
The number of display lines and character font
cannot be changed after this point.
Display off
Display clear
Entry mode set
Initialization ends
Figure 23 8-Bit Interface
45
HD44780U
Power on
Wait for more than 15 ms
after VCC rises to 4.5 V
DB70DB60DB51DB4
RS0R/W
0
Wait for more than 4.1 ms
DB70DB60DB51DB4
RS0R/W
0
Wait for more than 100 µs
DB70DB60DB51DB4
RS0R/W
0
DB70DB60DB51DB4
RS0R/W
0
0
0
0
0
0
0
0
0
0
0
0
F
N
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
Initialization ends
1
1
1
0
1
0
**
0
0
0
0
0
0
0
1
0
0
I/D
S
Wait for more than 40 ms
after V
rises to 2.7 V
CC
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See Table 6.)
Function set (Set interface to be 4 bits long.)
Interface is 8 bits in length.
Function set (Interface is 4 bits long. Specify the
number of display lines and character font.)
The number of display lines and character font
cannot be changed after this point.
Display off
Display clear
Entry mode set
46
Figure 24 4-Bit Interface
HD44780U
Absolute Maximum Ratings*
Item Symbol Value Unit Notes
Power supply voltage (1) V
Power supply voltage (2) VCC–V5 –0.3 to +13.0 V 1, 2
Input voltage Vt –0.3 to VCC +0.3 V 1
Operating temperature T
Storage temperature T
Note: * If the LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limits is strongly recommended for
normal operation. If these electrical characteristic conditions are also exceeded, the LSI will
malfunction and cause poor reliability.
–GND –0.3 to +7.0 V 1
CC
opr
stg
–30 to +75 °C
–55 to +125 °C4
47
HD44780U
DC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3)
Item Symbol Min Typ Max Unit Test Condition Notes*
Input high voltage (1)
VIH1 0.7V
(except OSC1)
Input low voltage (1)
VIL1 –0.3 — 0.55 V 6
(except OSC1)
Input high voltage (2)
VIH2 0.7V
(OSC1)
Input low voltage (2)
VIL2 — — 0.2V
(OSC1)
Output high voltage (1)
VOH1 0.75V
(DB0–DB7)
Output low voltage (1)
VOL1 — — 0.2V
(DB0–DB7)
Output high voltage (2)
VOH2 0.8V
(except DB0–DB7)
Output low voltage (2)
VOL2 — — 0.2V
(except DB0–DB7)
Driver on resistance
R
COM
— 2 20 kΩ±Id = 0.05 mA,
(COM)
Driver on resistance
R
SEG
— 2 30 kΩ±Id = 0.05 mA,
(SEG)
Input leakage current I
Pull-up MOS current
LI
–I
p
–1 — 1 µA VIN = 0 to V
10 50 120 µAV
(DB0–DB7, RS, R/W)
Power supply current I
CC
— 150 300 µAR
LCD voltage VLCD1 3.0 — 11.0 V VCC–V5, 1/5 bias 16
VLCD2 3.0 — 11.0 V VCC–V5, 1/4 bias 16
Note: * Refer to the Electrical Characteristics Notes section following these tables.
—VCCV6
CC
—VCCV15
CC
V15
CC
——V –I
CC
VI
CC
——V –I
CC
VI
CC
= 0.1 mA 7
OH
= 0.1 mA 7
OL
= 0.04 mA 8
OH
= 0.04 mA 8
OL
13
VLCD = 4 V
13
VLCD = 4 V
9
CC
= 3 V
CC
oscillation,
f
10, 14
external clock
V
= 3 V,
CC
f
= 270 kHz
OSC
48
HD44780U
AC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3)
Clock Characteristics
Item Symbol Min Typ Max Unit Test Condition Note*
External External clock frequency f
clock
External clock duty Duty 45 50 55 %
cp
operation
External clock rise time t
External clock fall time t
R
f
Clock oscillation frequency f
rcp
fcp
OSC
oscillation
Note: * Refer to the Electrical Characteristics Notes section following these tables.
Bus Timing Characteristics
Write Operation
Item Symbol Min Typ Max Unit Test Condition
Enable cycle time t
Enable pulse width (high level) PW
Enable rise/fall time tEr, t
Address set-up time (RS, R/W to E) t
Address hold time t
Data set-up time t
Data hold time t
cycE
AS
AH
DSW
H
125 250 350 kHz 11
— — 0.2 µs
— — 0.2 µs
190 270 350 kHz Rf = 75 kΩ,
V
= 3 V
CC
1000 — — ns Figure 25
450 — —
EH
——25
Ef
60 — —
20 — —
195 — —
10 — —
12
Read Operation
Item Symbol Min Typ Max Unit Test Condition
Enable cycle time t
cycE
Enable pulse width (high level) PW
Enable rise/fall time tEr, t
Address set-up time (RS, R/W to E) t
Address hold time t
Data delay time t
Data hold time t
AS
AH
DDR
DHR
1000 — — ns Figure 26
450 — —
EH
——25
Ef
60 — —
20 — —
— — 360
5——
49
HD44780U
Interface Timing Characteristics with External Driver
Item Symbol Min Typ Max Unit Test Condition
Clock pulse width High level t
Low level t
Clock set-up time t
Data set-up time t
Data hold time t
M delay time t
Clock rise/fall time t
CWH
CWL
CSU
SU
DH
DM
ct
Power Supply Conditions Using Internal Reset Circuit
Item Symbol Min Typ Max Unit Test Condition
Power supply rise time t
Power supply off time t
r CC
OFF
800 — — ns Figure 27
800 — —
500 — —
300 — —
300 — —
–1000 — 1000
— — 200
0.1 — 10 ms Figure 28
1——
50
HD44780U
DC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3)
Item Symbol Min Typ Max Unit Test Condition Notes*
Input high voltage (1)
VIH1 2.2 — V
CC
(except OSC1)
Input low voltage (1)
VIL1 –0.3 — 0.6 V 6
(except OSC1)
Input high voltage (2)
VIH2 VCC–1.0 — V
CC
(OSC1)
Input low voltage (2)
VIL2 — — 1.0 V 15
(OSC1)
Output high voltage (1)
VOH1 2.4 — — V –IOH = 0.205 mA 7
(DB0–DB7)
Output low voltage (1)
VOL1 — — 0.4 V IOL = 1.2 mA 7
(DB0–DB7)
Output high voltage (2)
VOH2 0.9 V
——V –I
CC
(except DB0–DB7)
Output low voltage (2)
VOL2 — — 0.1 V
(except DB0–DB7)
Driver on resistance
RCOM — 2 20 kΩ±Id = 0.05 mA,
(COM)
Driver on resistance
RSEG — 2 30 kΩ±Id = 0.05 mA,
(SEG)
Input leakage current I
Pull-up MOS current
LI
–I
p
–1 — 1 µA VIN = 0 to V
50 125 250 µAV
(DB0–DB7, RS, R/W)
Power supply current I
CC
— 350 600 µAR
LCD voltage VLCD1 3.0 — 11.0 V VCC–V5, 1/5 bias 16
VLCD2 3.0 — 11.0 V VCC–V5, 1/4 bias 16
Note: * Refer to the Electrical Characteristics Notes section following these tables.
V6
V15
= 0.04 mA 8
OH
VI
CC
= 0.04 mA 8
OL
13
VLCD = 4 V
13
VLCD = 4 V
9
10, 14
= 5 V
CC
oscillation,
f
CC
external clock
V
= 5 V,
CC
f
= 270 kHz
OSC
51
HD44780U
AC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3)
Clock Characteristics
Item Symbol Min Typ Max Unit Test Condition Notes*
External External clock frequency f
clock
External clock duty Duty 45 50 55 % 11
cp
operation
External clock rise time t
External clock fall time t
R
f
Clock oscillation frequency f
rcp
fcp
OSC
oscillation
Note: * Refer to the Electrical Characteristics Notes section following these tables.
Bus Timing Characteristics
Write Operation
Item Symbol Min Typ Max Unit Test Condition
Enable cycle time t
Enable pulse width (high level) PW
Enable rise/fall time tEr, t
Address set-up time (RS, R/W to E) t
Address hold time t
Data set-up time t
Data hold time t
cycE
AS
AH
DSW
H
125 250 350 kHz 11
— — 0.2 µs11
— — 0.2 µs11
190 270 350 kHz Rf = 91 kΩ
V
= 5.0 V
CC
12
500 — — ns Figure 25
230 — —
EH
——20
Ef
40 — —
10 — —
80 — —
10 — —
Read Operation
Item Symbol Min Typ Max Unit Test Condition
Enable cycle time t
cycE
Enable pulse width (high level) PW
Enable rise/fall time tEr, t
Address set-up time (RS, R/W to E) t
Address hold time t
Data delay time t
Data hold time t
AS
AH
DDR
DHR
52
500 — — ns Figure 26
230 — —
EH
——20
Ef
40 — —
10 — —
— — 160
5——
HD44780U
Interface Timing Characteristics with External Driver
Item Symbol Min Typ Max Unit Test Condition
Clock pulse width High level t
Low level t
Clock set-up time t
Data set-up time t
Data hold time t
M delay time t
Clock rise/fall time t
CWH
CWL
CSU
SU
DH
DM
ct
Power Supply Conditions Using Internal Reset Circuit
Item Symbol Min Typ Max Unit Test Condition
Power supply rise time t
Power supply off time t
rCC
OFF
800 — — ns Figure 27
800 — —
500 — —
300 — —
300 — —
–1000 — 1000
— — 100
0.1 — 10 ms Figure 28
1——
53
HD44780U
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0 V.
V
CC
B
V1
A
V5
A =
V
–V5
CC
B =
V
–V1
CC
A 1.5 V
≥
B 0.25 × A
≤
The conditions of V1 and V5 voltages are for proper
operation of the LSI and not for the LCD output level.
The LCD drive voltage condition for the LCD output
level is specified as LCD voltage VLCD.
2. VCC ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must be maintained.
3. For die products, specified at 75°C.
4. For die products, specified by the die shipment specification.
5. The following four circuits are I/O pin configurations except for liquid crystal display output.
Input pin
Pin: E (MOS without pull-up) Pins: RS, R/W (MOS with pull-up)
I/O Pin
Pins: DB0 –DB7
(MOS with pull-up)
(pull-up MOS)
PMOS
NMOS
V
CC
V
CC
PMOS
(pull up MOS)
V
CC
(input circuit)
PMOSPMOS
V
CC
PMOS
NMOS
Output pin
Pins: CL1, CL2, M, D
Input enable
V
CC
PMOS
NMOS
54
NMOS
NMOS
PMOS
NMOS
V
CC
Output enable
Data
(output circuit)
(tristate)
HD44780U
6. Applies to input pins and I/O pins, excluding the OSC1 pin.
7. Applies to I/O pins.
8. Applies to output pins.
9. Current flowing through pull–up MOSs, excluding output drive MOSs.
10.Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive
current flows through the input circuit to the power supply. To avoid this from happening, the input
level must be fixed high or low.
11.Applies only to external clock operation.
Th Tl
Oscillator OSC1
0.7 V
CC
0.5 V
Open
OSC2
0.3 V
CC
CC
t
rcp
Th
Duty = 100%
Th + Tl
×
t
fcp
12.Applies only to the internal oscillator operation using oscillation resistor Rf.
R :
75 k ± 2% (when VCC = 3 V)
Ω
f
R :
91 k ± 2% (when V
f
CC
= 5 V)Ω
Since the oscillation frequency varies depending on the OSC1 and
OSC2 pin capacitance, the wiring length to these pins should be minimized.
VCC = 5 V
VCC = 3 V
500
400
300
(270)
max.
typ.
OSC
f (kHz)
200
min.
(91)
100
150
100
(75)
50 100 150
R (k )fΩ
R
f
500
400
300
OSC
f (kHz)
200
100
OSC1
OSC2
(270)
50
R (k )
Ω
f
max.
typ.
min.
55
HD44780U
13.RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin
(COM1 to COM16).
RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin
(SEG1 to SEG40).
14.The following graphs show the relationship between operation frequency and current consumption.
V
= 5 V
f
OSC
CC
or f
cp
(kHz)
1.8
1.6
1.4
1.2
1.0
(mA)
0.8
CC
I
0.6
0.4
0.2
0.0
0 100 200 300 400 500
max.
typ.
1.8
1.6
1.4
1.2
1.0
(mA)
0.8
CC
I
0.6
0.4
0.2
0.0
0 100 200 300 400 500
f
OSC
V
= 3 V
CC
max.
typ.
or f
(kHz)
cp
15.Applies to the OSC1 pin.
16.Each COM and SEG output voltage is within ±0.15 V of the LCD voltage (VCC, V1, V2, V3, V4, V5)
when there is no load.
56
Load Circuits
Data Bus DB0 to DB7
For V = 4.5 to 5.5 V
CC
Test
point
V = 5 V
CC
3.9 kΩ
HD44780U
For V = 2.7 to 4.5 V
CC
Test
point
90 pF 11 kΩ
External Driver Control Signals: CL1, CL2, D, M
Test
point
IS2074
diodes
H
30 pF
50 pF
57
HD44780U
Timing Characteristics
RS
R/W
E
DB0 to DB7
RS
VIH1
VIL1
t
AS
VIH1
VIL1
t
AH
VIL1 VIL1
VIH1
VIL1
PW
EH
VIH1
VIL1
t
Er
VIH1
VIL1
t
DSW
Valid data
t
cycE
t
AH
t
Ef
t
H
VIH1
VIL1
Figure 25 Write Operation
VIH1
VIL1
t
AS
VIH1
VIL1
t
AH
VIL1
R/W
VIH1 VIH1
PW
E
DB0 to DB7
VIH1
VIL1
t
DDR
t
Er
VOH1
VOL1 *
Note: * VOL1 is assumed to be 0.8 V at 2 MHz operation.
Figure 26 Read Operation
58
t
EH
AH
t
Ef
VIH1
VIL1
Valid data
t
cycE
t
DHR
VOH1
* VOL1
VIL1
CL1
CL2
VOH2
VOL2
t
CSU
t
CSU
VOH2
t
CWH
VOL2
t
CWH
VOH2
HD44780U
t
ct
t
CWL
t
ct
t
VOH2
VOL2
DH
D
t
SU
M
VOH2
t
DM
Figure 27 Interface Timing with External Driver
V
CC
2.7 V/4.5 V*
0.2 V
2
t
rcc
0.1 ms t
10 ms≤ ≤ t
rcc
0.2 V 0.2 V
*1
t
OFF
1 ms≥
OFF
Notes: 1.
t
compensates for the power oscillation period caused by momentary power supply
OFF
oscillations.
Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation.
2.
For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not operate
3.
normally.
In this case, the LSI must be initialized by software. (Refer to the Initializing by
Instruction section.)
Figure 28 Internal Power Supply Reset
59
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