Page 1
DS92LV090A
9 Channel Bus LVDS Transceiver
DS92LV090A 9 Channel Bus LVDS Transceiver
February 2001
General Description
The DS92LV090Ais one in a series of Bus LVDS transceivers designed specifically for the high speed, low power
proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. Thedevice also features a flow through pinout
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides
common mode noise rejection of
The receiver threshold is less than
common mode range and translates the differential Bus
LVDS to standard (TTL/CMOS) levels. (See Applications
Information Section for more details.)
±
1V.
±
100 mV over a±1V
Simplified Functional Diagram
Features
n Bus LVDS Signaling
n 3.2 nanosecond propagation delay max
n Chip to Chip skew
n Low power CMOS design
n High Signaling Rate Capability (above 100 Mbps)
n 0.1V to 2.3V Common Mode Range for V
±
n
100 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 64 pin TQFP package
n High impedance Bus pins on power off (V
n Driver Channel to Channel skew (same device) 230ps
typical
n Receiver Channel to Channel skew (same device)
370ps typical
±
800ps
= 200mV
ID
= 0V)
CC
DS100111-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation DS100111 www.national.com
Page 2
Connection Diagram
DS92LV090A
DS100111-2
Top View
Order Number DS92LV090ATVEH
See NS Package Number VEH064DB
Pinout Description
Pin Name Pin # Input/Output Descriptions
DO+/RI+ 27, 31, 35, 37, 41,
45, 47, 51, 55
DO−/RI− 26, 30, 34, 36, 40,
44, 46, 50, 54
D
IN
2, 6, 12, 18, 20, 22,
58, 60, 62
RO 3, 7, 13, 19, 21, 23,
59, 61, 63
RE
17 I Receiver Enable TTL Input (Active Low).
DE 16 I Driver Enable TTL Input (Active High).
GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board).
V
CC
10, 15, 24, 57, 64 Power VCCfor digital circuitry (must connect to VCCon PC board). These
AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board).
AV
CC
29, 32, 42, 48, 52 Power Analog VCC(must connect to VCCon PC board). These pins
NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect.
I/O True Bus LVDS Driver Outputs and Receiver Inputs.
I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
I TTL Driver Input.
O TTL Receiver Output.
These pins connected internally.
pins connected internally.
These pins connected internally.
connected internally.
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Page 3
DS92LV090A
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Enable Input Voltage
(DE, RE)
Driver Input Voltage (D
Receiver Output Voltage
) −0.3V to (VCC+0.3V)
(R
OUT
Bus Pin Voltage (DO/RI
ESD (HBM 1.5 kΩ, 100 pF)
Driver Short Circuit Duration momentary
Receiver Short Circuit
Duration momentary
Maximum Package Power Dissipation at 25˚C
TQFP 1.74 W
Derate TQFP Package 13.9 mW/˚C
) 4.0V
CC
−0.3V to (VCC+0.3V)
) −0.3V to (VCC+0.3V)
IN
±
) −0.3V to +3.9V
>
4.5 kV
θ
ja
θ
jc
Storage Temperature
Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) 260˚C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (V
Receiver Input Voltage 0.0 2.4 V
Operating Free Air Temperature −40 +85 ˚C
Maximum Input Edge Rate
(Note 6)(20% to 80%) ∆t/∆V
Data 1.0 ns/V
Control 3.0 ns/V
) 3.0 3.6 V
CC
71.7˚C/W
10.9˚C/W
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD
∆V
V
OS
∆V
V
OH
V
OL
I
OSD
V
OH
V
OL
I
OD
V
TH
V
TL
V
CMR
I
IN
Output Differential
Voltage
VODMagnitude Change 27 mV
OD
RL=27Ω,
Figure 1
DO+/RI+,
DO−/RI−
240 300 460 mV
Offset Voltage 1.1 1.3 1.5 V
Offset Magnitude
OS
Change
Driver Output High
Voltage
Driver Output Low
Voltage
Output Short Circuit
Current (Note 10)
Voltage Output High
(Note 11)
RL=27Ω
RL=27Ω
VOD= 0V, DE = VCC, Driver
outputs shorted together
VID= +300 mV IOH= −400 µA R
OUT
Inputs Open V
0.95 1.1 V
VCC−0.2 V
−0.2 V
CC
510mV
1.4 1.65 V
|36| |65| mA
Inputs
Terminated,
R
=27Ω
L
V
−0.2 V
CC
Voltage Output Low IOL= 2.0 mA, VID= −300 mV 0.05 0.075 V
Receiver Output
Dynamic Current (Note
10)
= 300mV, V
V
ID
V
= −300mV, V
ID
OUT=VCC
OUT
−1.0V −110 |75|
= 1.0V |75|
Input Threshold High DE = 0V, VCM= 1.5V DO+/RI+,
Input Threshold Low −100 mV
Receiver Common
DO−/RI−
|VID|/2 2.4 −
Mode Range
Input Current DE = 0V, RE = 2.4V,
VIN= +2.4V or 0V
V
= 0V, VIN= +2.4V or 0V −20
CC
−20
±
1 +20 µA
±
1 +20 µA
110 mA
+100 mV
|/2
|V
ID
mA
V
www.national.com3
Page 4
DC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
DS92LV090A
V
IH
V
IL
I
IH
I
IL
V
CL
I
CCD
I
CCR
I
CCZ
I
CC
I
OFF
C
OUTPUT
c
OUTPUT
Minimum Input High
Voltage
Maximum Input Low
Voltage
DIN, DE,
RE
2.0 V
GND 0.8 V
Input High Current VIN=VCCor 2.4V −20
Input Low Current VIN= GND or 0.4V −20
Input Diode Clamp
Voltage
Power Supply Current
Drivers Enabled,
I
= −18 mA
CLAMP
No Load, DE = RE = V
DIN=VCCor GND
−1.5 −0.8 V
,
CC
V
CC
Receivers Disabled
Power Supply Current
DE=RE=0V,V
=±300mV
ID
Drivers Disabled,
Receivers Enabled
Power Supply Current,
Drivers and Receivers
TRI-STATE
®
Power Supply Current,
Drivers and Receivers
Enabled
Power Off Leakage
Current
DE = 0V; RE = VCC,
DIN=VCCor GND 35 80 mA
DE=V
;RE=0V,
CC
DIN=VCCor GND,
=27Ω
R
L
VCC= 0V or OPEN,
, DE, RE = 0V or OPEN,
D
IN
V
APPLIED
= 3.6V (Port Pins)
DO+/RI+,
DO−/RI− −20 +20 µA
Capacitance@Bus Pins DO+/RI+,
DO−/RI−
Capacitance@R
OUT
R
OUT
CC
±
10 +20 µA
±
10 +20 µA
55 80 mA
73 80 mA
170 210 mA
5pF
7pF
V
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLD
t
PLHD
t
SDK1
t
SDK2
t
SDK3
t
TLH
t
THL
Differential Prop. Delay High to Low (Note 8) RL=27Ω,
Differential Prop. Delay Low to High (Note 8) 0.6 1.4 2.2 ns
Differential Skew |t
PHLD–tPLHD
| (Note 9) 80 ps
Figures 2, 3
=10pF
C
L
,
0.6 1.4 2.2 ns
Chip to Chip Skew (Note 12) 1.6 ns
Channel to Channel Skew (Note 13) 0.25 0.45 ns
Transition Time Low to High 0.6 1.2 ns
Transition Time High to Low 0.5 1.2 ns
Disable Time High to Z RL=27Ω,
Disable Time Low to Z 38ns
Enable Time Z to High 38ns
Figures 4, 5
=10pF
C
L
,
38ns
Enable Time Z to Low 38ns
Differential Prop. Delay High to Low (Note 8)
Differential Prop Delay Low to High (Note 8) 1.6 2.4 3.2 ns
Differential Skew |t
PHLD–tPLHD
| (Note 9) 80 ps
Figures 6, 7
=35pF
C
L
,
1.6 2.4 3.2 ns
Chip to Chip Skew (Note 12) 1.6 ns
Channel to Channel Skew (Note 13) 0.35 0.60 ns
Transition Time Low to High 1.5 2.5 ns
Transition Time High to Low 1.5 2.5 ns
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Page 5
AC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHZ
t
PLZ
t
PZH
t
PZL
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into devicepinsarepositive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specifiedexcept
V
, ∆VODand VID.
OD
Note 3: All typicals are given for V
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
Note 5: C
Note 6: Generator waveforms for all tests unless otherwise specified:f=25MHz,Z
minimum skew, data input edge rates should be equal to or faster than 1ns/V;control signals equal to orfaster than 3ns/V. In general, the faster the input edge rate,
the better the AC performance.
Note 7: The DS92LV090Afunctions within datasheet specification when a resistive load is applied to the driver outputs.
Note 8: Propagation delays are guaranteed by design and characterization.
Note 9: t
Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 11: V
Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.
Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-903, AN-971,
AN-977, and AN-1108.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recommended practices are:
Use at least 4 PCB board layer (Bus LVDS signals,
•
ground, power and TTL signals).
Keep drivers and receivers as close to the (Bus LVDS
•
port side) connector as possible.
Bypass each Bus LVDS device and also use distributed
•
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in
parallel should be used between each V
The capacitors should be as close as possible to the V
pin.
Multiple vias should be used to connect V
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
Use the termination resistor which best matches the dif-
•
ferential impedance of your transmission line.
Leave unused Bus LVDS receiver inputs open (floating).
•
Limit traces on unused inputs to
Isolate TTL signals from Bus LVDS signals
•
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
Use controlled impedance media. The backplane and
•
connectors should have a matched differential impedance.
Disable Time High to Z RL= 500Ω,
Disable Time Low to Z 3.5 8 ns
Enable Time Z to High 3.5 8 ns
Figures 8, 9
=35pF
C
L
,
4.5 10 ns
Enable Time Z to Low 3.5 8 ns
= +3.3V and TA= +25˚C, unless otherwise stated.
CC
>
4.5 kV EIAJ (0Ω, 200 pF)>300V.
includes probe and fixture capacitance.
L
SKD1|tPHLD–tPLHD
failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
OH
| is the worse case skew between any channel and any device over recommended operation conditions.
=50Ω,tr,tf=<1.0 ns (0%–100%). To ensure fastest propagation delay and
O
TABLE 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
TABLE 2. Transmitter Mode
INPUTS OUTPUTS
DE D
IN
DO+ DO−
HL LH
HHHL
<
<
D
2.0V X X
IN
and ground.
CC
H 0.8V
LXZZ
CC
TABLE 3. Receiver Mode
and Ground
<
0.5 inches.
CC
RE
LL(
LH(
L −100 mV
HX Z
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
INPUTS
(RI+) – (RI−)
<
−100 mV) L
>
+100 mV) H
<
<
V
+100 mV X
ID
OUTPUT
DS92LV090A
www.national.com5
Page 6
Test Circuits and Timing Waveforms
DS92LV090A
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
DS100111-3
DS100111-4
FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms
www.national.com 6
DS100111-5
Page 7
Test Circuits and Timing Waveforms (Continued)
FIGURE 4. Driver TRI-STATE Delay Test Circuit
DS92LV090A
DS100111-6
DS100111-7
FIGURE 5. Driver TRI-STATE Delay Waveforms
DS100111-8
FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit
DS100111-9
FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms
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Page 8
Test Circuits and Timing Waveforms (Continued)
DS92LV090A
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
FIGURE 9. Receiver TRI-STATE Delay Waveforms
DS100111-10
DS100111-11
Typical Bus Application Configurations
Bi-Directional Half-Duplex Point-to-Point Applications
Multi-Point Bus Applications
DS100111-12
DS100111-13
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Page 9
Physical Dimensions All dimensions are in millimeters
DS92LV090A 9 Channel Bus LVDS Transceiver
64-Lead Molded TQFP Package
Order Number DS92LV090ATVEH
NS Package Number VEH064DB
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whose failure to perform when properly used in
accordance with instructions for use provided in the
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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
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