Rainbow Electronics DS92LV040A User Manual
DS92LV040A
4 Channel Bus LVDS Transceiver
DS92LV040A 4 Channel Bus LVDS Transceiver
August 2002
General Description
The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single
3.3V power supply and includes four differential line drivers
and four receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The device
also features a flow through pin out which allows easy PCB
routing for short stubs between its pins and the connector.
The driver translates 3V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for
high speed operation while consuming minimal power and
reducing EMI. In addition, the differential signaling provides
common mode noise rejection greater than
The receiver threshold is less than +0/−70 mV. The receiver
translates the differential Bus LVDS to standard (LVTTL/
LVCMOS) levels. (See Applications Information Section for
more details.)
±
1V.
Simplified Functional Diagram
Features
n Bus LVDS Signaling
n Propagation delay: Driver 2.3ns max, Receiver 3.2ns
max
n Low power CMOS design
n 100% Transition time 1ns driver typical, 1.3ns receiver
typical
n High Signaling Rate Capability (above 155 Mbps)
n 0.1V to 2.3V Common Mode Range for V
n 70 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 44 pin LLP (Leadless Leadframe
Package) package
n High impedance Bus pins on power off (V
= 200mV
ID
= 0V)
CC
10133601
© 2002 National Semiconductor Corporation DS101336 www.national.com
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
DS92LV040A
Distributors for availability and specifications.
Supply Voltage (V
Enable Input Voltage
(DE, RE)
Driver Input Voltage (D
Receiver Output Voltage
(R
) −0.3V to (VCC+0.3V)
OUT
Bus Pin Voltage (DO/RI
ESD (Note 4)
(HBM 1.5 kΩ, 100 pF)
Machine Model
Maximum Package Power Dissipation at 25˚C
LLP(Note 3) 4.8 W
) 4.0V
CC
−0.3V to (VCC+0.3V)
) −0.3V to (VCC+0.3V)
IN
±
) −0.3V to +3.9V
>
>
4kV
250V
θ
(Note 3) 25.8˚C/W
ja
θ
jc
25.5˚C/W
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) 260˚C
Recommended Operating Conditions
Min Max Units
Supply Voltage (V
Receiver Input Voltage 0.0 2.4 V
Operating Free Air Temperature −40 +85 ˚C
Slowest Input Edge Rate
(Note 7)(20% to 80%) ∆t/∆V
Data 1.0 ns/V
Control 3.0 ns/V
) 3.0 3.6 V
CC
Derate LLP Package 38.8mW/˚C
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 4)
Symbol Parameter Conditions Pin Min Typ Max Units
V
∆V
V
∆V
V
V
I
OSD
V
V
I
OD
V
V
V
I
IN
OD
OS
OHD
OLD
OHR
OLR
TH
TL
CMR
Output Differential
Voltage
VODMagnitude Change 527mV
OD
RL=27Ω, Figure 1 DO+/RI+,
DO−/RI−
200 300 460 mV
Offset Voltage 1.1 1.3 1.5 V
Offset Magnitude Change 5 10 mV
OS
Driver Output High
Voltage
Driver Output Low
Voltage
Driver Output Short
Circuit Current (Note 11)
Receiver Voltage Output
High (Note 12)
Receiver Voltage Output
Low
Receiver Output Dynamic
Current (Note 11)
Input Threshold High
(Note 9)
Input Threshold Low
(Note 9)
Receiver Common Mode
Range
Input Current DE = 0V, RE = 2.4V,
RL=27Ω
RL=27Ω
VOD= 0V, DE = VCC, Driver outputs
shorted together
VID= +300 mV IOH=−4mA R
OUT
Inputs Open V
Inputs Terminated,
RL=27Ω
IOL= 4.0 mA, VID= −300 mV
VID= 300mV, V
V
= −300mV, V
ID
OUT=VCC
OUT
−1.0V −50 |33| mA
= 1.0V |36| 60 mA
DE = 0V, Over common mode range DO+/RI+,
DO−/RI−
VIN= +2.4V or 0V
V
= 0V, VIN= +2.4V or 0V −20
CC
1.4 1.65 V
0.95 1.1 V
|30| | 45| mA
VCC−0.2 V
−0.2 V
CC
V
−0.2 V
CC
0.05 0.100 V
−40 0 mV
−70 −40 mV
|VID|/2 2.4 −
|/2
|V
ID
−20
±
1 +20 µA
±
1 +20 µA
V
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DC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 4)
Symbol Parameter Conditions Pin Min Typ Max Units
V
IH
V
IL
I
IH
I
IL
V
CL
I
CCD
I
CCR
I
CCZ
I
CC
I
OFF
C
OUTPUT
c
OUTPUT
Minimum Input High
Voltage
Maximum Input Low
Voltage
DIN, DE,
RE
2.0 V
GND 0.8 V
Input High Current VIN=VCCor 2.4V −20
Input Low Current VIN= GND or 0.4V −20
Input Diode Clamp
Voltage
Power Supply Current
Drivers Enabled,
I
= −18 mA
CLAMP
No Load, DE = RE = V
DIN=VCCor GND
−1.5 −0.8 V
,
CC
V
CC
Receivers Disabled
Power Supply Current
DE=RE=0V,V
=±300mV
ID
Drivers Disabled,
Receivers Enabled
Power Supply Current,
Drivers and Receivers
DE = 0V; RE = V
DIN=VCCor GND 28 40 mA
,
CC
TRI-STATE
Power Supply Current,
Drivers and Receivers
Enabled
Power Off Leakage
Current
DE=V
DIN=VCCor GND,
R
L
VCC= 0V or OPEN,
D
IN
V
APPLIED
;RE=0V,
CC
=27Ω
, DE, RE = 0V or OPEN,
= 3.6V (Port Pins)
DO+/RI+,
DO−/RI− −20 +20 µA
Capacitance@Bus Pins DO+/RI+,
DO−/RI−
Capacitance@R
OUT
R
OUT
CC
±
2.5 +20 µA
±
2.5 +20 µA
V
20 40 mA
27 40 mA
70 100 mA
5pF
5pF
DS92LV040A
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 7)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
t
PLHD
t
SKD1
t
CCSK
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAXD
Differential Prop. Delay High to Low (Note 9) RL=27Ω,
Differential Prop. Delay Low to High (Note 9) 1.0 1.5 2.3 ns
Differential Skew |t
PHLD–tPLHD
| (duty cycle)(Note 10),
Figures 2, 3,
=10pF
C
L
(Note 9)
1.0 1.5 2.3 ns
80 160 ps
Channel to Channel Skew (all 4 channels), (Note 9) 220 400 ps
Transition Time Low to High (20% to 80%) 0.4 0.75 1.3 ns
Transition Time High to Low (80% to 20%) 0.4 0.75 1.3 ns
Disable Time High to Z RL=27Ω,
Disable Time Low to Z 5.0 10 ns
Enable Time Z to High 5.0 10 ns
Figures 4, 5,
=10pF
C
L
5.0 10 ns
Enable Time Z to Low 5.0 10 ns
Guaranteed operation per data sheet up to the Min.
Duty Cycle 45/55%,Transition time ≤ 25% of period
85 125 MHz
(Note 9)
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AC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 7)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
DS92LV040A
t
PHLDR
t
PLHDR
t
SDK1R
Differential Prop. Delay High to Low (Note 9) Figures 6, 7,
=15pF
Differential Prop Delay Low to High (Note 9) 1.6 2.4 3.2 ns
Differential Skew |t
PHLD–tPLHD
| (duty cycle)(Note 10),
C
L
(Note 9)
t
CCSKR
t
TLHR
t
THLR
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAXR
Channel to Channel Skew (all 4 channels)(Note 9) 140 300 ps
Transition Time Low to High (10% to 90%) (Note 9) 0.850 1.250 2.0 ns
Transition Time High to Low (90% to 10%) (Note 9) 0.850 1.030 2.0 ns
Disable Time High to Z RL= 500Ω,
Disable Time Low to Z 3.0 10 ns
Enable Time Z to High 3.0 10 ns
Figures 8, 9,
=15pF
C
L
Enable Time Z to Low 3.0 10 ns
Guaranteed operation per data sheet up to the Min.
Duty Cycle 45/55%,Transition time ≤ 25% of period
(Note 9)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative.All voltages are referenced to ground unless otherwise specified except
V
, ∆VODand VID.
OD
Note 3: Package must be mounted to pc board in accordance with AN-1187 to achieve thermals.
Note 4: All typicals are given for V
Note 5: ESD Rating: HBM (1.5 kΩ, 100 pF)
Note 6: C
Note 7: Generator waveforms for all tests unless otherwise specified:f=25MHz, Z
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate,
the better the AC performance.
Note 8: The DS92LV040A functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 9: Propagation delays, transition times, and receiver threshold are guaranteed by design and characterization.
Note 10: t
Note 11: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 12: V
Note 13: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
includes probe and fixture capacitance.
L
SKD1|tPHLD–tPLHD
fail-safe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
OH
= +3.3V and TA= +25˚C, unless otherwise stated.
CC
| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions.
>
4 kV EIAJ (0Ω, 200 pF)>250.
=50Ω,tr,tf=<1.0 ns (0%–100%). To ensure fastest propagation delay and
O
1.6 2.4 3.2 ns
85 160 ps
3.0 10 ns
85 125
MHz
Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-977, AN-971, and
AN-903.
BLVDS drivers and receivers are intended to be used in a
differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media
such as differential PCB traces. Typically, the characteristic
differential impedance of the media (Zo) is in the range of
50Ω to 100Ω. Two termination resistors of ZoΩ each are
placed at the ends of the transmission line backplane. The
termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. The
effects of mid-stream connector(s), cable stub(s), and other
impedance discontinuity as well as ground shifting, noise
margin limits, and total termination loading must be taken
into account. The DS92LV040A differential line driver is a
balanced current mode design. A current mode driver, generally speaking has a high output impedance (100 ohms)
and supplies a reasonably constant current for a range of
loads (a voltage mode driver on the other hand supplies a
constant voltage for a range of loads). Current is switched
through the load in one direction to produce a logic state and
in the other direction to produce the other logic state. The
output current is typically 12 mA. The current changes as a
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function of load resistor. The current mode requires (as
discussed above) that a resistive termination be employed to
terminate the signal and to complete the loop. Unterminated
configurations are not allowed. The 12 mA loop current will
develop a differential voltage of about 300mV across a 27Ω
(double terminated 54Ω differential transmission backplane)
effective resistance, which the receiver detects with a 230
mV minimum differential noise margin neglecting resistive
line losses (driven signal minus receiver threshold (300 mV
– 70 mV = 230 mV)). The signal is centered around +1.2V
(Driver Offset, VOS ) with respect to ground. Note that the
steady-state voltage (VSS ) peak-to-peak swing is twice the
differential voltage (VOD ) and is typically 600 mV. The
current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due
to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current
mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
ICC requirements of the ECL/PECL designs. LVDS requires
80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other
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