Rainbow Electronics DS92001 User Manual

DS92001

3.3V B/LVDS-BLVDS Buffer

General Description

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input
signal and provides an BLVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the ’stub length’ or
the distance between the transmission line and the untermi­nated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging con­cerns often make it difficult to make the stubs as short as the
designer would like.

The DS92001 has edge transitions optimized for multidrop
backplanes where the switching frequency is in the 200 MHz
range or less. The output edge rate is critical in some sys­tems where long stubs may be present, and utilizing a slow
transition allows for longer stub lengths.

The DS92001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver inputs to be placed
very close to the main transmission line, thus improving
system performance.

A wide input dynamic range allows the DS92001 to receive
differential signals from LVPECL as well as LVDS sources.
This will allow the device to also fill the role of an LVPECL­BLVDS translator.

June 2002

The LOS pin detects a non-driven B/LVDS bus state at the
input and provides an active LOW output. The LOS pin can
be tied to the device’s output enable pin (EN) to generate a
TRI-STATE output state when the input is un-driven. The
LOS pin can also be used locally to inform the system of the
bus state.

Features

n Single +3.3 V Supply
n B/LVDS receiver inputs accept LVPECL signals
n TRI-STATE outputs
n Loss of Signal (LOS) pin detects a non-driven bus

<

n Receiver input threshold
n Fast propagation delay of 1.4 ns (typ)
n Low jitter 400 Mbps fully differential data path
n Compatible with BLVDS 10-bit SerDes (40MHz)
n Compatible with ANSI/TIA/EIA-644-A LVDS standard
n Available in SOIC and space saving LLP package
n Industrial Temperature Range

±

100 mV

DS92001 3.3V B/LVDS-BLVDS Buffer

Connection and Block Diagrams

SOIC - Top View

20024705

LLP - Top View

20024743

DAP (GND) Pad Not Shown

20024702

Functional Operation

BLVDS Inputs BLVDS Outputs

[IN+] − [IN−] OUT+ OUT−

VID ≥ 0.1V H L

VID ≤ −0.1V L H

Full Fail-safe

OPEN/SHORTor Terminated

HL

Ordering Information

Order Number NS Pkg. No. Pkg. Type

DS92001TM M08A SOIC

DS92001TLD LDA08A LLP

© 2002 National Semiconductor Corporation DS200247 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

DS92001

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

LVCMOS/LVTTL Input Voltage
(EN)

LVCMOS/LVTTL Output Voltage
(LOS)

B/LVDS Receiver Input Voltage
(IN+, IN−) −0.3V to +4V

BLVDS Driver Output Voltage
(OUT+, OUT−) −0.3V to +4V

BLVDS Output Short Circuit
Current

Junction Temperature +150˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range

Soldering (4 sec.) +260˚C

) −0.3V to +4V

CC

−0.3V to (V

−0.3V to (VCC+ 0.3V)

+ 0.3V)

CC

Continuous

Maximum Package Power Dissipation at 25˚C

M Package 726 mW

Derate M Package 5.8 mW/˚C above +25˚C

LDA Package 2.44 W

Derate LDA Package 19.49 mW/˚C above

ESD Ratings

(HBM, 1.5kΩ, 100pF) ≥2.5kV

(EIAJ, 0Ω, 200pF) ≥250V

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (V

Receiver Differential Input
Voltage (V

=1.2V

V

CM

ID

) with

Operating Free Air
Temperature

B/LVDS Input Rise/Fall
20% to 80%

) 3.0 3.3 3.6 V

CC

0.1 2.4 |V|

−40 +25 +85 ˚C

220ns

+25˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS/LVTTL DC SPECIFICATIONS (EN)

V

IH

V

IL

I

IH

I

IL

V

CL

LVCMOS/LVTTL DC SPECIFICATIONS (LOS)

V

OH

V

OL

I

OSHLOS

BLVDS OUTPUT DC SPECIFICATIONS (OUT)

|V

OD

∆V

V

OS

∆V

I

OZ

High Level Input Voltage 2.0 V

Low Level Input Voltage GND 0.8 V

High Level Input Current VIN=VCCor 2.0V +7 +20 µA

Low Level Input Current VIN= GND or 0.8V −10

±

1 +10 µA

Input Clamp Voltage ICL= −18 mA −0.6 −1.5 V

Output High Voltage IOH= −4mA, VID≥ |200mV|, VCM= 1.2V V

3.1 V

CC

−0.4V

Output Low Voltage

IOL= 4mA, VID= 0V, VCM= 1.2V 0.15 0.4 V

(Note 5)

Output Short Circuit Current

V

= 0V, 200mV ≤ VID≤ 2V, VCM= 1.5V −35 −60 mA

OUT

(output high)(Note 4)

| Differential Output Voltage

(Note 2)

Change in Magnitude of V

OD

RL=27Ω 250 350 500 mV

R

=50Ω 350 450 600 mV

L

RL=27Ω or 50Ω Figure 1, Figure 2

OD

for Complimentary Output
States

Offset Voltage RL=27Ω or RL=50Ω 1.1 1.25 1.375 V

Change in Magnitude of V

OS

for Complimentary Output

Figure 1

OS

220mV

States

Output TRI-STATE Current EN = 0V, V

OUT=VCC

or GND −20

±

5 +20 µA

CC

CC

V

V

20 mV

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

BLVDS OUTPUT DC SPECIFICATIONS (OUT)

I

I

I

OFF

OS1

OSD

Power-Off Leakage Current VCC= 0V or Open Circuit, V

Output Short Circuit Current
(Note 4)

Differential Output Short Circuit
Current (Note 4)

EN=VCC,VCM= 1.2V,VID= 200mV, V
or
V

ID

V

ID

V

ID

EN=VCC,VID= |200mV|, VCM. = 1.2V, VOD=0V
(connect true and complement outputs through a
current meter)

B/LVDS RECEIVER DC SPECIFICATIONS (IN)

V

TH

Differential Input High

VCM= +0.05V, +1.2V or +3.25V −30 −5 mV

Threshold (Note 5)

V

TL

Differential Input Low
Threshold (Note 5)

V

CMR

Common Mode Voltage Range
(Note 5)

I

∆I

V

IN

IN

FSOD

Input Current VIN=V

V

IN

Change in Magnitude of I

Fail-safe BLVDS Outputs
(OUT+ is a more positive
voltage than OUT−)

IN

VIN=V

V

IN

Inputs open,
shorted, or
terminated

(Note 5)

SUPPLY CURRENT

I

I

CCD

CCZ

Total Dynamic Supply Current
(includes load current)

TRI-STATE Supply Current EN = 0V,Freq. = 200MHz 50% duty cycle,

EN=VCC,RL=27Ω or 50Ω,CL=15pF,
Freq. = 200MHz 50% duty cycle,
V

ID

V

ID

= 3.6V −20

OUT

= 0V,

OUT+

= −200mV, VCM= 1.2V, V

= −200mV, VCM= 1.2V, V
= 200mV, VCM=1.2V, V

=0V

OUT−

OUT+=VCC

OUT−=VCC

,or

−70 −30 mV

|VID|/2 V

CC

VCC= 3.6V or 0V |1.5| |20| µA

= 0V |1.5| |20| µA

CC

=0V 1 6 µA

=27Ω 250 350 500 mV

R

L

=50Ω 350 450 600 mV

R

L

= 200mV, VCM= 1.2V

= 200mV, VCM= 1.2V

±

5 +20 µA

−30 −60 mA

53 80 mA

|30| |42| mA

CC

V

−|VID|/2

16µA

50 65 mA

36 46 mA

DS92001

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

Symbol Parameter Conditions Min Typ Max Units

LVDS OUTPUT AC SPECIFICATIONS (OUT)

t

PHLD

t

PLHD

t

SKD1

t

SKD3

t

SKD4

Differential Propagation Delay
High to Low
(Note 10)

Differential Propagation Delay
Low to High
(Note 10)

Pulse Skew |t

PLHD−tPHLD

|
(measure of duty cycle)
(Notes 5, 6)

Part-to-Part Skew (Note 5)
(Note 7)

Part-to-Part Skew (Note 5)
(Note 8)

= 200mV, VCM= 1.2V,

V

ID

=27Ω or 50Ω,CL= 15pF

R

L

Figure 3 and Figure 4

1.0 1.4 2.0 ns

1.0 1.4 2.0 ns

0 20 200 ps

0 200 300 ps

01ns

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AC Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

DS92001

Symbol Parameter Conditions Min Typ Max Units

LVDS OUTPUT AC SPECIFICATIONS (OUT)

t

LHT

t

HLT

t

PHZ

t

PLZ

t

PZH

t

PZL

t

DJ

t

RJ

f

MAX

LVCMOS/LVTTL AC SPECIFICATIONS (LOS)

t

PHLLOS

t

PLHLOS

t

LHLOS

t

HLLOS

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
V

Note 3: All typical are given for V

Note 4: Output short circuit current (I

Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and

temperature) range.

Note 6: t
the same channel (a measure of duty cycle).

Note 7: t
applies to devices at the same V

Note 8: t
operating temperature and voltage ranges, and across process distribution. t

Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test
equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A
(20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t
picoseconds.

Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤ 200MHz, Zo =
50Ω,tr,tf≤ 0.5ns. Generator used was HP8130A (300MHz capability).

Note 11: f
is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum
guaranteed AC frequency. The typical value is always greater than the minimum guarantee.

Rise Time (Notes 5, 10)
20% to 80% points

Fall Time (Notes 5, 10)

RL=50Ω or 27Ω,CL= 15pF
Figure 3 and Figure 5

0.350 0.6 1.0 ns

0.350 0.6 1.0 ns

80% to 20% points

Disable Time (Active High to Z) RL=50Ω,CL= 15pF 3 25 ns

Disable Time (Active Low to Z) Figure 6 and Figure 7 325ns

Enable Time (Z to Active High) 100 120 ns

Enable Time (Z to Active Low) 100 120 ns

LVDS Data Jitter, Deterministic
(Peak-to-Peak) (Note 9)

LVDS Clock Jitter, Random
(Note 9)

Maximum guaranteed
frequency

VID= 300mV; PRBS = 223− 1 data; VCM= 1.2V at
400Mbps (NRZ)

VID= 300mV; VCM= 1.2V at 200MHz clock

= 200mV, VCM= 1.2V

V

ID

78 ps

36 ps

200 300 MHz

(Note 11)

LVTTL Propagation Delay High
to Low (Note 5)

LVTTL Propagation Delay Low

CL = 10pF, IN− = 1V, 1V ≤ IN+ ≤ 1.3V,
Freq. = 10MHz, 50% Duty Cycle

Figures 8, 9

10 15 20 ns

2 5 10 ns

to High (Note 5)

Rise Time

123ns

20% to 80% (Note 5)

Fall Time

1 1.3 3 ns

80% to 20% (Note 5)

, and ∆VOD.VODhas a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.

TL

,|t

SKD1

PLHD−tPHLD

, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

SKD3

, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended

SKD4

test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%. This specification

MAX

= +3.3V and TA= +25˚C, unless otherwise stated.

CC

) is specified as magnitude only, minus sign indicates direction only.

OS

|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

and within 5˚C of each other within the operating temperature range. This parameter guaranteed by design and characterization.

CC

is defined as |Max − Min| differential propagation delay.

SKD4

measured 100 picoseconds, tRJmeasured 60

DJ

ID,VOD,VTH

,

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