DS92001
3.3V B/LVDS-BLVDS Buffer
General Description
The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input
signal and provides an BLVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the ’stub length’ or
the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the
designer would like.
The DS92001 has edge transitions optimized for multidrop
backplanes where the switching frequency is in the 200 MHz
range or less. The output edge rate is critical in some systems where long stubs may be present, and utilizing a slow
transition allows for longer stub lengths.
The DS92001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver inputs to be placed
very close to the main transmission line, thus improving
system performance.
A wide input dynamic range allows the DS92001 to receive
differential signals from LVPECL as well as LVDS sources.
This will allow the device to also fill the role of an LVPECLBLVDS translator.
June 2002
The LOS pin detects a non-driven B/LVDS bus state at the
input and provides an active LOW output. The LOS pin can
be tied to the device’s output enable pin (EN) to generate a
TRI-STATE output state when the input is un-driven. The
LOS pin can also be used locally to inform the system of the
bus state.
Features
n Single +3.3 V Supply
n B/LVDS receiver inputs accept LVPECL signals
n TRI-STATE outputs
n Loss of Signal (LOS) pin detects a non-driven bus
<
n Receiver input threshold
n Fast propagation delay of 1.4 ns (typ)
n Low jitter 400 Mbps fully differential data path
n Compatible with BLVDS 10-bit SerDes (40MHz)
n Compatible with ANSI/TIA/EIA-644-A LVDS standard
n Available in SOIC and space saving LLP package
n Industrial Temperature Range
±
100 mV
DS92001 3.3V B/LVDS-BLVDS Buffer
Connection and Block Diagrams
SOIC - Top View
20024705
LLP - Top View
20024743
DAP (GND) Pad Not Shown
20024702
Functional Operation
BLVDS Inputs BLVDS Outputs
[IN+] − [IN−] OUT+ OUT−
VID ≥ 0.1V H L
VID ≤ −0.1V L H
Full Fail-safe
OPEN/SHORTor Terminated
HL
Ordering Information
Order Number NS Pkg. No. Pkg. Type
DS92001TM M08A SOIC
DS92001TLD LDA08A LLP
© 2002 National Semiconductor Corporation DS200247 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
DS92001
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
LVCMOS/LVTTL Input Voltage
(EN)
LVCMOS/LVTTL Output Voltage
(LOS)
B/LVDS Receiver Input Voltage
(IN+, IN−) −0.3V to +4V
BLVDS Driver Output Voltage
(OUT+, OUT−) −0.3V to +4V
BLVDS Output Short Circuit
Current
Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range
Soldering (4 sec.) +260˚C
) −0.3V to +4V
CC
−0.3V to (V
−0.3V to (VCC+ 0.3V)
+ 0.3V)
CC
Continuous
Maximum Package Power Dissipation at 25˚C
M Package 726 mW
Derate M Package 5.8 mW/˚C above +25˚C
LDA Package 2.44 W
Derate LDA Package 19.49 mW/˚C above
ESD Ratings
(HBM, 1.5kΩ, 100pF) ≥2.5kV
(EIAJ, 0Ω, 200pF) ≥250V
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
Receiver Differential Input
Voltage (V
=1.2V
V
CM
ID
) with
Operating Free Air
Temperature
B/LVDS Input Rise/Fall
20% to 80%
) 3.0 3.3 3.6 V
CC
0.1 2.4 |V|
−40 +25 +85 ˚C
220ns
+25˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
V
IH
V
IL
I
IH
I
IL
V
CL
LVCMOS/LVTTL DC SPECIFICATIONS (LOS)
V
OH
V
OL
I
OSHLOS
BLVDS OUTPUT DC SPECIFICATIONS (OUT)
|V
OD
∆V
V
OS
∆V
I
OZ
High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Input Current VIN=VCCor 2.0V +7 +20 µA
Low Level Input Current VIN= GND or 0.8V −10
±
1 +10 µA
Input Clamp Voltage ICL= −18 mA −0.6 −1.5 V
Output High Voltage IOH= −4mA, VID≥ |200mV|, VCM= 1.2V V
3.1 V
CC
−0.4V
Output Low Voltage
IOL= 4mA, VID= 0V, VCM= 1.2V 0.15 0.4 V
(Note 5)
Output Short Circuit Current
V
= 0V, 200mV ≤ VID≤ 2V, VCM= 1.5V −35 −60 mA
OUT
(output high)(Note 4)
| Differential Output Voltage
(Note 2)
Change in Magnitude of V
OD
RL=27Ω 250 350 500 mV
R
=50Ω 350 450 600 mV
L
RL=27Ω or 50Ω Figure 1, Figure 2
OD
for Complimentary Output
States
Offset Voltage RL=27Ω or RL=50Ω 1.1 1.25 1.375 V
Change in Magnitude of V
OS
for Complimentary Output
Figure 1
OS
220mV
States
Output TRI-STATE Current EN = 0V, V
OUT=VCC
or GND −20
±
5 +20 µA
CC
CC
V
V
20 mV
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Min Typ Max Units
BLVDS OUTPUT DC SPECIFICATIONS (OUT)
I
I
I
OFF
OS1
OSD
Power-Off Leakage Current VCC= 0V or Open Circuit, V
Output Short Circuit Current
(Note 4)
Differential Output Short Circuit
Current (Note 4)
EN=VCC,VCM= 1.2V,VID= 200mV, V
or
V
ID
V
ID
V
ID
EN=VCC,VID= |200mV|, VCM. = 1.2V, VOD=0V
(connect true and complement outputs through a
current meter)
B/LVDS RECEIVER DC SPECIFICATIONS (IN)
V
TH
Differential Input High
VCM= +0.05V, +1.2V or +3.25V −30 −5 mV
Threshold (Note 5)
V
TL
Differential Input Low
Threshold (Note 5)
V
CMR
Common Mode Voltage Range
(Note 5)
I
∆I
V
IN
IN
FSOD
Input Current VIN=V
V
IN
Change in Magnitude of I
Fail-safe BLVDS Outputs
(OUT+ is a more positive
voltage than OUT−)
IN
VIN=V
V
IN
Inputs open,
shorted, or
terminated
(Note 5)
SUPPLY CURRENT
I
I
CCD
CCZ
Total Dynamic Supply Current
(includes load current)
TRI-STATE Supply Current EN = 0V,Freq. = 200MHz 50% duty cycle,
EN=VCC,RL=27Ω or 50Ω,CL=15pF,
Freq. = 200MHz 50% duty cycle,
V
ID
V
ID
= 3.6V −20
OUT
= 0V,
OUT+
= −200mV, VCM= 1.2V, V
= −200mV, VCM= 1.2V, V
= 200mV, VCM=1.2V, V
=0V
OUT−
OUT+=VCC
OUT−=VCC
,or
−70 −30 mV
|VID|/2 V
CC
VCC= 3.6V or 0V |1.5| |20| µA
= 0V |1.5| |20| µA
CC
=0V 1 6 µA
=27Ω 250 350 500 mV
R
L
=50Ω 350 450 600 mV
R
L
= 200mV, VCM= 1.2V
= 200mV, VCM= 1.2V
±
5 +20 µA
−30 −60 mA
53 80 mA
|30| |42| mA
CC
V
−|VID|/2
16µA
50 65 mA
36 46 mA
DS92001
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (OUT)
t
PHLD
t
PLHD
t
SKD1
t
SKD3
t
SKD4
Differential Propagation Delay
High to Low
(Note 10)
Differential Propagation Delay
Low to High
(Note 10)
Pulse Skew |t
PLHD−tPHLD
|
(measure of duty cycle)
(Notes 5, 6)
Part-to-Part Skew (Note 5)
(Note 7)
Part-to-Part Skew (Note 5)
(Note 8)
= 200mV, VCM= 1.2V,
V
ID
=27Ω or 50Ω,CL= 15pF
R
L
Figure 3 and Figure 4
1.0 1.4 2.0 ns
1.0 1.4 2.0 ns
0 20 200 ps
0 200 300 ps
01ns
www.national.com3
AC Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
DS92001
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (OUT)
t
LHT
t
HLT
t
PHZ
t
PLZ
t
PZH
t
PZL
t
DJ
t
RJ
f
MAX
LVCMOS/LVTTL AC SPECIFICATIONS (LOS)
t
PHLLOS
t
PLHLOS
t
LHLOS
t
HLLOS
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
V
Note 3: All typical are given for V
Note 4: Output short circuit current (I
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and
temperature) range.
Note 6: t
the same channel (a measure of duty cycle).
Note 7: t
applies to devices at the same V
Note 8: t
operating temperature and voltage ranges, and across process distribution. t
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test
equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A
(20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t
picoseconds.
Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤ 200MHz, Zo =
50Ω,tr,tf≤ 0.5ns. Generator used was HP8130A (300MHz capability).
Note 11: f
is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum
guaranteed AC frequency. The typical value is always greater than the minimum guarantee.
Rise Time (Notes 5, 10)
20% to 80% points
Fall Time (Notes 5, 10)
RL=50Ω or 27Ω,CL= 15pF
Figure 3 and Figure 5
0.350 0.6 1.0 ns
0.350 0.6 1.0 ns
80% to 20% points
Disable Time (Active High to Z) RL=50Ω,CL= 15pF 3 25 ns
Disable Time (Active Low to Z) Figure 6 and Figure 7 325ns
Enable Time (Z to Active High) 100 120 ns
Enable Time (Z to Active Low) 100 120 ns
LVDS Data Jitter, Deterministic
(Peak-to-Peak) (Note 9)
LVDS Clock Jitter, Random
(Note 9)
Maximum guaranteed
frequency
VID= 300mV; PRBS = 223− 1 data; VCM= 1.2V at
400Mbps (NRZ)
VID= 300mV; VCM= 1.2V at 200MHz clock
= 200mV, VCM= 1.2V
V
ID
78 ps
36 ps
200 300 MHz
(Note 11)
LVTTL Propagation Delay High
to Low (Note 5)
LVTTL Propagation Delay Low
CL = 10pF, IN− = 1V, 1V ≤ IN+ ≤ 1.3V,
Freq. = 10MHz, 50% Duty Cycle
Figures 8, 9
10 15 20 ns
2 5 10 ns
to High (Note 5)
Rise Time
123ns
20% to 80% (Note 5)
Fall Time
1 1.3 3 ns
80% to 20% (Note 5)
, and ∆VOD.VODhas a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.
TL
,|t
SKD1
PLHD−tPHLD
, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
SKD3
, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended
SKD4
test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%. This specification
MAX
= +3.3V and TA= +25˚C, unless otherwise stated.
CC
) is specified as magnitude only, minus sign indicates direction only.
OS
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
and within 5˚C of each other within the operating temperature range. This parameter guaranteed by design and characterization.
CC
is defined as |Max − Min| differential propagation delay.
SKD4
measured 100 picoseconds, tRJmeasured 60
DJ
ID,VOD,VTH
,
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DC Test Circuits
DS92001
20024703
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Full Load DC Test Circuit
AC Test Circuits and Timing Diagrams
FIGURE 3. BLVDS Output Load
20024708
20024706
20024707
FIGURE 4. Propagation Delay Low-to-High and High-to-Low
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AC Test Circuits and Timing Diagrams (Continued)
DS92001
FIGURE 5. BLVDS Output Transition Time
FIGURE 6. TRI-STATE Delay Test Circuit
20024709
20024701
FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time
FIGURE 8. LOS Output Load for Propagation Delay, and Rise/Fall Times
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20024704
20024741
AC Test Circuits and Timing Diagrams (Continued)
FIGURE 9. LOS Output Waveforms for Propagation Delay, and Rise/Fall Times
DS92001 Pin Description (SOIC and LLP)
Pin Name Pin # Input/Output Description
GND 1 P Ground
IN − 2 I Inverting receiver B/LVDS input pin
IN+ 3 I Non-inverting receiver B/LVDS input pin
LOS
V
CC
OUT+ 6 O Non-inverting driver BLVDS output pin
OUT - 7 O Inverting driver BLVDS output pin
EN 8 I Enable pin. When EN is LOW, the driver is disabled and the BLVDS
GND DAP P LLP Package Ground
4 O Loss of Signal output pin. LOS is asserted low while signal is invalid.
See Applications Information section.
5 P Power Supply, 3.3V±0.3V.
outputs are in TRI-STATE. When EN is HIGH, the driver is enabled.
LVCMOS/LVTTL levels.
DS92001
20024742
www.national.com7
Typical Applications
DS92001
FIGURE 10. Backplane Stub-Hider Application
FIGURE 11. Cable Repeater Application
20024711
20024710
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Application Information
The DS92001 can be used as a ’stub-hider.’ In many systems, signals are distributed across backplanes, and one of
the limiting factors for system speed is the ’stub length’ or the
distance between the transmission line and the unterminated
receivers on the individual cards. See Figure 10. Although it
is generally recognized that this distance should be as short
as possible to maximize system performance, real-world
packaging concerns and PCB designs often make it difficult
to make the stubs as short as the designer would like. The
DS92001, available in the LLP (Leadless Leadframe Package) package, can improve system performance by allowing
the receiver to be placed very close to the main transmission
line either on the backplane itself or very close to the connector on the card. Longer traces to the LVDS receiver may
be placed after the DS92001. This very small LLP package is
a 75% space savings over the SOIC package.
The DS92001 may also be used as a repeater as shown in
Figure 11. The signal is recovered and redriven at full
strength down the following segment. The DS92001 may
also be used as a level translator, as it accepts LVDS,
BLVDS, and LVPECL inputs.
LOS Detection:
The LOS pin presents a logic High level during normal
operation (|100|mV ≤ VID≤ |2|V, of the device. When normal
transmission stops the LOS pin is asserted low. This occurs
when the signal’s source is removed, or turned-off (TRISTATE). When the input signal voltage (V
millivolts the LOS pin is asserted Low. For normal operation,
Rise and Fall times presented to the B/LVDS inputs must be
faster than 20 nanoseconds (20% to 80%) to avoid a loss of
signal detection. Typical input transitions are in the 1-3 nanosecond range. In the case of a decaying signal (such as valid
signal to TRI-STATE), the slope should be monotonic to
avoid glitches in the LOS detection.
) is less than |10|
ID
DS92001
LOS Detection - Output Low
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.01µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC Board considerations:
Use at least 4 PCB board layers (top to bottom): LVDS
signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
For PC board considerations for the LLP package, please
refer to application note AN-1187 “Leadless Leadframe
Package.” It is important to note that to optimize signal
integrity (minimize jitter and noise coupling), the LLP thermal
land pad, which is a metal (normally copper) rectangular
region located under the package as seen in Figure 12,
should be attached to ground and match the dimensions of
the exposed pad on the PCB (1:1 ratio).
FIGURE 12. LLP Thermal Land Pad and Pin Pads - Top View
Differential Traces:
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
<
10mm long). This will help eliminate
20024744
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will result. Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines.
Minimize the number of vias and other discontinuities on the
line.
www.national.com9
Application Information (Continued)
Avoid 90˚ turns (these cause impedance discontinuities).
DS92001
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allowable.
Termination:
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should
be between 90Ω and 130Ω for point-to-point links. Multidrop
(driver in the middle) or multipoint configurations are typically
terminated at both ends. The termination value may be lower
than 100Ω due to loading effects and in the 50Ω to 100Ω
range. Remember that the current mode outputs need the
termination resistor to generate the differential voltage.
Surface mount 1% - 2% resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be
(12mm MAX).
Probing LVDS Transmission Lines:
>
Always use high impedance (
<
2 pF) scope probes with a wide bandwidth (1 GHz)
(
scope. Improper probing will give deceiving results.
FailSafe Feature:
The BLVDS receiver is a high gain, high speed device that
amplifies a small differential signal (30mV) to BLVDS ouput
drive levels. Due to the high gain and tight threshold of the
receiver, care should be taken to prevent noise from appearing as a valid signal.
100kΩ), low capacitance
<
10mm
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a high level output voltage ) for floating, terminated or shorted receiver inputs.
1. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition,
the BLVDS outputs will again be in a HIGH state, even
with the end of cable 100Ω termination resistor across
the input pins. The unplugged cable can become a
floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To
insure that any noise is seen as common-mode and not
differential, a balanced interconnect should be used.
Twisted pair cable will offer better balance than flat
ribbon cable.
2. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differential input voltage, the BLVDS outputs will remain in a
HIGH state. Shorted input fail-safe voltage range is 0V
to 2.4V.
3. External Biasing. External lower value pull up and pull
down resistors (for a stronger bias) may be used to
boost fail-safe in the presence of higher noise levels.
The pull up and pull down resistors should be in the 5kΩ
to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should
be set to approximately 1.2V (less than 1.75V) to be
compatible with the internal circuitry. Please refer to
application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information.
www.national.com 10
Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number DS92001TM
See NS Package Number M08A
DS92001
Order Number DS92001TLD
See NS Package Number LDA08A
www.national.com11
DS92001 3.3V B/LVDS-BLVDS Buffer
Notes
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
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Corporation
Americas
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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