Rainbow Electronics DS90LV001 User Manual

DS90LV001

3.3V LVDS-LVDS Buffer

General Description

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input
signal and provides an LVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the ’stub length’ or
the distance between the transmission line and the untermi­nated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging con­cerns often make it difficulttomakethestubs as short as the
designer would like.

The DS90LV001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver to be placed very
close to the main transmission line, thus improving system
performance.

A wide input dynamic range will allow the DS90LV001 to
receive differential signals from LVPECL as well as LVDS
sources. This will allow the device to also fill the role of an
LVPECL-LVDS translator.

April 2001

An output enable pin is provided, which allows the user to
place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin
LLP and SOIC.

Features

n Single +3.3 V Supply
n LVDS receiver inputs accept LVPECL signals
n TRI-STATE outputs

<

n Receiver input threshold
n Fast propagation delay of 1.4 ns (typ)
n Low jitter 800 Mbps fully differential data path
n 100 ps (typ) of pk-pk jitter with PRBS = 2

pattern at 800 Mbps

n Compatible with ANSI/TIA/EIA-644-A LVDS standard
n 8 pin SOIC and space saving (70%) LLP package
n Industrial Temperature Range

±

100 mV

23

−1 data

DS90LV001 3.3V LVDS-LVDS Buffer

Connection Diagram

Block Diagram

Top View

DS101338-5

Order Number DS90LV001TM, DS90LV001TLD

See NS Package Number M08A, LDA08A

DS101338-2

© 2001 National Semiconductor Corporation DS101338 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/

DS90LV001

Distributors for availability and specifications.

Supply Voltage (V
LVCMOS/LVTTL Input Voltage

(EN)
LVDS Receiver Input Voltage

(IN+, IN−) −0.3V to +4V

) −0.3V to +4V

CC

−0.3V to (V

CC

+ 0.3V)

Maximum Package Power Dissipation at 25˚C

M Package 726 mW
Derate M Package 5.8 mW/˚C above +25˚C
LDA Package 2.44 W
Derate LDA Package 19.49 mW/˚C above

ESD Ratings

(HBM, 1.5kΩ, 100pF) ≥2.5kV
(EIAJ, 0Ω, 200pF) ≥250V

LVDS Driver Output Voltage
(OUT+, OUT−) −0.3V to +4V

LVDS Output Short Circuit
Current

Continuous

Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range

Soldering (4 sec.) +260˚C

Recommended Operating
Conditions

Min Typ Max Units

Supply Voltage (V
Receiver Input Voltage 0 V
Operating Free Air

) 3.0 3.3 3.6 V

CC

−40 +25 +85 ˚C

CC

Temperature

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS/LVTTL DC SPECIFICATIONS (EN)

V

IH

V

IL

I

IH

I

IL

V

CL

LVDS OUTPUT DC SPECIFICATIONS (OUT)

V

OD

∆V

V

OS

∆V

I

OZ

I

OFF

I

OS

I

OSD

LVDS RECEIVER DC SPECIFICATIONS (IN)

V

TH

V

TL

V

CMR

I

IN

∆I

SUPPLY CURRENT

I

CCD

I

CCZ

High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Input Current VIN= 3.6V or 2.0V, VCC= 3.6V +7 +20 µA
Low Level Input Current VIN= GND or 0.8V, VCC= 3.6V

±

1

Input Clamp Voltage ICL= −18 mA −0.6 −1.5 V

Differential Output Voltage RL= 100Ω 250 325 450 mV
Change in Magnitude of VODfor Complimentary

OD

Figure 1

and

Figure 2

Output States
Offset Voltage RL= 100Ω 1.080 1.19 1.375 V
Change in Magnitude of VOSfor Complimentary

OS

Figure 1

Output States
Output TRI-STATE Current EN = 0V, V
Power-Off Leakage Current VCC= 0V, V
Output Short Circuit Current (Note 4) EN = VCC,V

OUT=VCC

= 3.6V or GND

OUT

and V

OUT+

or GND

= 0V −16 −24 mA

OUT−

±

1

±

1

Differential Output Short Circuit Current (Note 4) EN = VCC,VOD= 0V −7 −12 mA

Differential Input High Threshold VCM= +0.05V, +1.2V or +3.25V 0 +100 mV
Differential Input Low Threshold −100 0 mV
Common Mode Voltage Range VID= 100mV, VCC= 3.3V 0.05 3.25 V
Input Current VIN= +3.0V VCC= 3.6V or 0V

V

=0V

IN

Change in Magnitude of I

IN

IN

VIN= +3.0V VCC= 3.6V or 0V 1 6 µA
V

=0V 1 6 µA

IN

±
±

1
1

Total Supply Current EN = VCC,RL= 100Ω,CL=5pF 47 70 mA
TRI-STATE Supply Current EN = 0V 22 35 mA

CC

±

10 µA

20 mV

20 mV

±

10 µA

±

10 µA

±

10 µA

±

10 µA

+25˚C

V

V

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD1

t

SKD3

t

SKD4

t

LHT

t

HLT

t

PHZ

t

PLZ

t

PZH

t

PZL

t

DJ

t

RJ

Differential Propagation Delay High to Low RL= 100Ω,CL= 5pF 1.0 1.4 2.0 ns
Differential Propagation Delay Low to High
Pulse Skew |t

PLHD−tPHLD

| (Note 5) (Note 6) 20 200 ps

Figure 3

and

Figure 4

1.0 1.4 2.0 ns

Part to Part Skew (Note 5) (Note 7) 0 60 ps
Part to Part Skew (Note 5) (Note 8) 400 ps
Rise Time (Note 5) RL= 100Ω,CL= 5pF 200 320 450 ps
Fall Time (Note 5)

Figure 3

and

Figure 5

200 310 450 ps
Disable Time (Active High to Z) RL= 100Ω,CL= 5pF 3 25 ns
Disable Time (Active Low to Z)

Figure 6

and

Figure 7

325ns
Enable Time (Z to Active High) 25 45 ns
Enable Time (Z to Active Low) 25 45 ns
LVDS Data Jitter, Deterministic (Peak-to-Peak)

(Note 9)
LVDS Clock Jitter, Random (Note 9) VID= 300mV; VCM= 1.2V at 400MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
Note 3: All typical are given for V
Note 4: Output short circuit current (I
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and

temperature) range.
Note 6: t

the same channel.
Note 7: t

applies to devices at the same V
Note 8: t

operating temperature and voltage ranges, and across process distribution. t
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test

equipment setup: HP8133A(patternpulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A(50GHz
scope module). The HP8133A with RG142B cable exhibit a t

,|t

SKD1

PLHD−tPHLD

, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

SKD3

, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended

SKD4

= +3.3V and TA= +25˚C, unless otherwise stated.

CC

) is specified as magnitude only, minus sign indicates direction only.

OS

|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

and within 5˚C of each other within the operating temperature range.

CC

= 21ps and tRJ= 1.8ps.

DJ

VID= 300mV; PRBS = 223− 1 data;

= 1.2V at 800Mbps (NRZ)

V

CM

clock

is defined as |Max − Min| differential propagation delay.

SKD4

100 135 ps

2.2 3.5 ps

and ∆VOD.

OD

DS90LV001

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DC Test Circuits

DS90LV001

DS101338-3

FIGURE 1. Differential Driver DC Test Circuit

DS101338-8

FIGURE 2. Differential Driver Full Load DC Test Circuit

AC Test Circuits and Timing Diagrams

FIGURE 3. LVDS Output Load

FIGURE 4. Propagation Delay Low-to-High and High-to-Low

DS101338-6

DS101338-7

FIGURE 5. LVDS Output Transition Time

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DS101338-9