Rainbow Electronics DS89C450 User Manual
Ultra-High-Speed Flash Microcontrollers
DS89C430/DS89C440/DS89C450
www.maxim-ic.com
GENERAL DESCRIPTION
The DS89C430, DS89C440, and DS89C450 offer the
highest performance available in 8051-compatible
microcontrollers. They feature newly designed
processor cores that execute instructions up to 12
times faster than the original 8051 at the same
crystal speed. Typical applications will experience a
speed improvement up to 10x. At 1 million
instructions per second (MIPS) per megahertz, the
microcontrollers achieve 33 MIPS performance from
a maximum 33MHz clock rate.
The Ultra-High-Speed Flash Microcontroller User’s Guide should
be used in conjunction with this data sheet. Download it at
www.maxim-ic.com/microcontrollers
.
FEATURES
§ High-Speed 8051 Architecture
One Clock-Per-Machine Cycle
DC to 33MHz Operation
Single Cycle Instruction in 30ns
Optional Variable Length MOVX to Access
Fast/Slow Peripherals
Dual Data Pointers with Automatic
Increment/Decrement and Toggle Select
Supports Four Paged Memory-Access Modes
§ On-Chip Memory
16kB/32kB/64kB Flash Memory
In-Application Programmable
In-System Programmable Through Serial Port
1kB SRAM for MOVX
APPLICATIONS
Data Logging Vending
Automotive Test Equipment Motor Control
Magstripe Reader/Scanner Consumer Electronics
Gaming Equipment Telephones
HVAC Programmable Logic
Uninterruptible Power
Supplies
Building Energy Control and
Management
White Goods (Washers,
Microwaves, etc.)
Controllers
Building Security and
Door Access Control
Industrial Control and
Automation
ORDERING INFORMATION
PART
DS89C430-MNL
DS89C430-QNL 16kB x 8 44 PLCC
DS89C430-ENL 16kB x 8 44 TQFP
DS89C440-MNL
DS89C440-QNL 32kB x 8 44 PLCC
DS89C440-ENL 32kB x 8 44 TQFP
DS89C450-MNL
DS89C450-QNL 64kB x 8 44 PLCC
DS89C450-ENL 64kB x 8 44 TQFP
Complete Selector Guide appears at end of data sheet.
Pin Configurations appear at end of data sheet.
FLASH
MEMORY SIZE
16kB x 8 40 PDIP
32kB x 8 40 PDIP
64kB x 8 40 PDIP
PIN-PACKAGE
§ 80C52 Compatible
8051 Pin and Instruction Set Compatible
Four Bidirectional, 8-Bit I/O Ports
Three 16-Bit Timer Counters
256 Bytes Scratchpad RAM
§ Power-Management Mode
Programmable Clock Divider
Automatic Hardware and Software Exit
§ ROMSIZE Feature
Selects Internal Program Memory Size from
0 to 64kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
§ Peripheral Features
Two Full-Duplex Serial Ports
Programmable Watchdog Timer
13 Interrupt Sources (Six External)
Five Levels of Interrupt Priority
Power-Fail Reset
Early Warning Power-Fail Interrupt
Electromagnetic Interference (EMI) Reduction
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1 of 48
REV: 111003
.
DS89C430/DS89C44/DS89C450 Ultra-High-Speed Flash Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.3V to (VCC + 0.5V)
Voltage Range on V
Relative to Ground -0.3V to +6.0V
CC
Ambient Temperature Range (under bias) -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL MIN TYP MAX UNITS
Supply Voltage (Notes 2, 3) V
Power-Fail Warning (Notes 2, 4) V
Reset Trip Point (Min Operating Voltage) (Notes 2, 3, 4) V
CC
4.2 4.375 4.6 V
PFW
3.95 4.125 4.35 V
RST
4.5 5.0 5.5 V
Supply Current, Active Mode (Note 5) ICC 75 110 mA
Supply Current, Idle Mode at 33MHz (Note 6) I
Supply Current, Stop Mode, Bandgap Disabled (Note 7) I
Supply Current, Stop Mode, Bandgap Enabled (Note 7) I
40 50 mA
IDLE
1 100 mA
STOP
150 300 mA
SPBG
Input Low Level (Note 2) VIL -0.3 +0.8 V
Input High Level (Note 2) VIH 2.0 VCC + 0.3 V
Input High Level XTAL and RST (Note 2) V
Output Low Voltage, Port 1 and 3 at IOL = 1.6mA (Note 2) V
Output Low Voltage, Port 0 and 2, ALE, PSEN at IOL = 3.2mA
(Note 2)
Output High Voltage, Port 1, 2, and 3, at IOH = -50mA
(Notes 2, 8)
Output High Voltage, Port 1, 2, and 3 at IOH = -1.5mA (Notes 2, 9) V
Output High Voltage, Port 0, 1, 2, ALE, PSEN, RD, WR in Bus
Mode at I
= -8mA (Notes 2, 10)
OH
Output High Voltage, RST at IOL = -0.4mA (Note 2, 11) V
3.5 VCC + 0.3 V
IH2
0.15 0.45 V
OL1
V
0.15 0.45 V
OL2
V
2.4 V
OH1
2.4 V
OH2
V
2.4 V
OH3
2.4 V
OH4
Input Low Current, Port 1, 2, and 3 at 0.4V IIL -50 mA
Transition Current from 1 to 0, Port 1, 2, and 3 at 2V (Note 12) ITL -650 mA
Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) IL -10 +10 mA
Input Current, Port 0 in Bus Mode (Note 14) IL -300 +300 mA
RST Pulldown Resistance (Note 13) R
RST
50 120 200 kW
2 of 48
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Specifications to -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that V
that point. This indicates that there is a range of voltages [(V
MIN
to V
(min)] where the processor's operation is not guaranteed, but
RST
the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper
operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.
While the specifications for V
PFW
and V
overlap, the design of the hardware makes it so this is not possible. Within the ranges
RST
given, there is guaranteed separation between these two voltages.
Active current is measured with a 33MHz clock source driving XTAL1, V
Idle mode current is measured with a 33MHz clock source driving XTAL1, V
= RST = 5.5V. All other pins are disconnected.
CC
= 5.5V, RST at ground. All other pins are
CC
disconnected.
Stop mode is measured with XTAL and RST grounded, V
= 5.5V. All other pins are disconnected.
CC
RST = 5.5V. This condition mimics the operation of pins in I/O mode.
During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition
mode.
When addressing external memory.
Guaranteed by design.
Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V.
RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode.
This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at
approximately 2V.
(min) is specified below
RST
3 of 48
AC CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.)
DS89C430/DS89C440/DS89C450
PARAMETER SYMBOL
System Clock External
Oscillator (Note 15)
System Clock External Crystal
(Note 15)
ALE Pulse Width (Note 16) t
Port 0 Instruction Address Valid
to ALE Low
Port 2 Instruction Address Valid
to ALE Low
Port 0 Data AddressValid to
ALE Low
Program Address Hold After
ALE Low
Address Hold after ALE Low
MOVX Write
1-CYCLE
PAGE MODE 1
2-CYCLE
PAGE MODE 1
4-CYCLE
PAGE MODE 1
PAGE MODE 2 NONPAGE MODE
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
1/t
0 33 0 33 0 33 0 33 0 33
CLCL
1/t
1 33 1 33 1 33 1 33 1 33
CLCL
0.5t
- 2
LHLL
t
t
AVLL
t
0.5t
AVLL2
t
AVLL3
t
0.5t
LLAX
t
LLAX2
CLCL
+ t
STC3
- 4 0.5t
CLCL
- 8 1.5t
CLCL
0.5t
- 8
CLCL
+ t
STC4
t
- 2
CLCL
+ t
STC3
- 4 1.5t
CLCL
- 8 2.5t
CLCL
1.5t
- 8
CLCL
+ t
STC4
2t
- 4
CLCL
+ t
STC3
- 4 0.5t
CLCL
- 8 1t
CLCL
2.5t
- 8
CLCL
+ t
STC3
1.5t
- 5
CLCL
+ t
STC3
- 3 0.5t
CLCL
- 4 t
CLCL
t
- 3 +
CLCL
t
STC3
- 10 1t
CLCL
0.5t
- 8
CLCL
+ t
STC2
1.5t
CLCL
+ t
STC3
CLCL
- 4
CLCL
0.5t
CLCL
+ t
STC3
- 10
CLCL
0.5t
CLCL
+ t
STC2
- 5
- 3
- 3
- 8
UNITS
MHz
ns
ns
ns
ns
ns
ns
Address Hold after ALE Low
MOVX Read
ALE Low to Valid Instruction In t
ALE Low to PSEN Low t
PSEN Pulse Width for Program
Fetch
0.5t
- 8
t
LLAX3
2t
LLIV
1.5t
LLPL
t
t
PLPH
CLCL
+ t
STC4
- 5 t
CLCL
1.5t
- 8
CLCL
+ t
STC4
- 5 2t
CLCL
2.5t
- 8
CLCL
+ t
STC3
- 5 t
CLCL
0.5t
- 8
CLCL
+ t
STC3
CLCL
- 6 0.5t
CLCL
- 5 2t
CLCL
4 of 48
0.5t
- 8
+ t
CLCL
STC2
- 6 2t
- 2
CLCL
- 5
CLCL
CLCL
- 6
ns
ns
ns
ns
AC CHARACTERISTICS (continued)
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PARAMETER SYMBOL
PSEN Low to Valid Instruction
In
Input Instruction Hold After
PSEN
Input Instruction Float After
PSEN
Port 0 Address to Valid
Instruction In
Port 2 Address to Valid
Instruction In
PSEN Low to Port 0 Address
Float
RD Pulse Width (P3.7)
(Note 16)
WR Pulse Width (P3.6)
(Note 16)
1-CYCLE
PAGE MODE 1
2-CYCLE
PAGE MODE 1
4-CYCLE
PAGE MODE 1
PAGE MODE 2 NONPAGE MODE
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t
t
PLIV
t
0 0 0 0 0
PXIX
t
t
PXIZ
t
1.5t
AVIV0
t
t
AVIV2
t
0 0
PLAZ
t
- 5
t
RLRH
t
WLWH
CLCL
+ t
STC1
t
- 5
CLCL
+ t
STC1
- 20 t
CLCL
- 20 1.5t
CLCL
t
- 5
+ t
t
+ t
CLCL
CLCL
STC1
- 5
STC1
- 20 2t
CLCL
- 20 2.5t
CLCL
2t
- 5
2t
CLCL
+ t
CLCL
+ t
STC1
STC1
- 5
- 20 t
CLCL
- 20 3t
CLCL
2t
- 5
CLCL
+ t
STC1
2t
- 5
CLCL
+ t
STC1
- 20 2t
CLCL
- 5 t
CLCL
- 22 3t
CLCL
- 20 3.5t
CLCL
2t
- 5
CLCL
+ t
STC1
2t
- 5
CLCL
+ t
STC1
CLCL
CLCL
CLCL
CLCL
- 20
- 5
- 22
- 20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
RD (P3.7) Low to Valid Data In
(Note 16)
Data Hold After RD (P3.7) t
Data Float After RD (P3.7) t
MOVX ALE Low to Input Data
Valid (Note 16)
t
- 18
t
RLDV
0 0 0 0 0
RHDX
t
RHDZ
t
LLDV
CLCL
+ t
STC1
t
CLCL
+ t
- 18
STC1
2t
- 18
CLCL
+ t
STC1
2t
- 18
CLCL
+ t
STC1
- 5 t
CLCL
2t
- 8
CLCL
+ t
STC1
2t
- 18
2t
CLCL
+ t
CLCL
CLCL
+ t
STC1
- 5
- 5
STC1
5 of 48
ns
ns
ns
ns
AC CHARACTERISTICS (continued)
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.)
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PARAMETER SYMBOL
PAGE MODE 1
1-CYCLE
2-CYCLE
PAGE MODE 1
4-CYCLE
PAGE MODE 1
PAGE MODE 2 NONPAGE MODE
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
- 8
- 5
STC2
- 2 t
3t
CLCL
+ t
3.5t
20 + t
0.5t
+ t
STC2
STC1
CLCL
CLCL
STC2
- 20
STC1
+ 5
+ 4
-
Port 0 Address to Valid Data
In (Note 16)
Port 2 Address to Valid Data
In (Note 16)
ALE Low to RD or WR Low
(Note 16)
Port 0 Address Valid to RD or
WR Low (Note 16)
Port 2 Address Valid to RD or
WR Low (Note 16)
Data Out Valid to WR
Transition (Note 15)
Data Hold After WR
(Note 15)
RD or WR High to ALE High
(Note 15)
3t
- 20
t
AVDV0
- 8
- 5
STC2
1.5t
-
CLCL
20 + t
2t
+ 6
CLCL
+ t
STC2
+ 4 t
STC2
STC1
4t
1.5t
t
CLCL
CLCL
+ t
+ t
STC2
STC2
CLCL
STC5
+ t
- 10
- 8
- 2 t
t
- 20
t
AVDV2
t
LLRL
t
LLWL)
(
t
AVRL0
t
AVWL0)
(
t
AVRL2
(t
AVWL2)
t
-5 -5 -5 -5 -5
QVWX
t
WHQX
t
RHLH
t
WHLH)
(
- 8 +
0.5t
CLCL
t
STC2
0 + t
STC5
t
+ t
CLCL
- 10
t
- 2 t
STC2
CLCL
+ t
0.5t
6 + t
- 5
STC2
STC2
STC1
+
CLCL
STC2
+ 4 t
2t
0.5t
t
CLCL
CLCL
+ t
+ t
STC2
STC2
CLCL
STC5
+ t
- 10
- 2 t
- 5
STC2
3.5t
-
CLCL
20 + t
4t
CLCL
t
STC2
STC1
+ 6 +
+ 4 t
STC2
0.5t
1.5t
t
t
CLCL
CLCL
CLCL
+ t
STC2
CLCL
+ t
STC2
- 5 +
t
STC5
+ t
STC2
- 10
- 2 t
STC2
- 8
- 5
CLCL
+ t
STC1
3.0t
- 20
CLCL
+ t
STC1
+ 4
0.5t
CLCL
+ t
STC2
+ 4 t
STC2
0.5t
t
1.5t
t
CLCL
+ t
CLCL
+ t
STC2
CLCL
STC2
- 5 +
t
STC2
CLCL
STC5
+ t
- 10
Note: Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator and are not 100% tested, but are
guaranteed by design.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
6 of 48
P
R
W
Note 15:
The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/
maximum external clock speed. The term “1/t
following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.
4X/2X
CD1 CD0
1 0 0 1 10MHz 8.25MHz
0 0 0 2 5MHz 16.5MHz
X 0 1 Reserved — —
X 1 0 4 See AC Characteristics See AC Characteristics
X 1 1 1/1024 See AC Characteristics See AC Characteristics
Note 16:
Note 17:
External MOVX instruction times are dependent upon the setting of the MD2, MD1, and MD0 bits in the clock control register. The
, t
, t
terms “t
STC1
STC2
” used in the variable timing table above are calculated through the use of the table given below.
STC3
MD2 MD1 MD0 MOVX Instruction Time t
0 0 0 2 Machine Cycles 0 t
0 0 1 3 Machine Cycles 2 t
0 1 0 4 Machine Cycles 6 t
0 1 1 5 Machine Cycles 10 t
1 0 0 6 Machine Cycles 14 t
1 0 1 7 Machine Cycles 18 t
1 1 0 8 Machine Cycles 22 t
1 1 1 9 Machine Cycles 26 t
Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance are dependent upon the frequency of the selected crystal.
Figure 1. Nonpage Mode Timing
XTAL1
t
CLCL
ALE
t
AVLL2
t
SEN
AVLL
” used in the AC Characteristics variable timing table is determined from the
CLCL
Number of External Clock
Cycles per System Clock
(1/t
)
CLCL
t
LHLL
t
AVLL3
t
t
STC1
0 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
5 t
CLCL
5 t
CLCL
5 t
CLCL
5 t
CLCL
LLAX3
DS89C430/DS89C440/DS89C450
External Clock Speed
Min Max
t
STC2
0 t
CLCL
0 t
CLCL
0 t
CLCL
0 t
CLCL
4 t
CLCL
4 t
CLCL
4 t
CLCL
4 t
CLCL
t
STC3
0 t
CLCL
0 t
CLCL
0 t
CLCL
0 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
t
STC4
0 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
1 t
CLCL
t
LLAX2
STC5
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
D
R
Port 0
Port 2
LSB
t
LLIV
t
LLPL
t
PXIX
t
LLAX
MOVX MOVX
t
PXIZ
t
AVIV0
t
PLPH
t
AVWL2
t
PLIV
t
RLRH
t
LLDV
t
AVDV0
t
RLDV
LSBLSB LSB LSB
t
AVDV2
DATA
t
RHDX
t
t
AVIV2
RHDZ
t
PLAZ
t
AVWL0
OPCODE
t
t
WHQX
MSB MSBMSBMSB MSB
7 of 48
WHLH
t
LLWL
t
WLWH
t
QVWX
DATA
Figure 2. Page Mode 1 Timing
P
R
W
P
R
W
XTAL1
CLCL
t
ALE
AVLL2
t
SEN
D
R
AVIV2
t
Port 0
OPCODE
MOVX
MOVX
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
LHLL
t
PLPH
t
LLAX2
LLAX3
t
LLWL
t
RLRH
t
RHDX
t
RLDV
t
DATA
AVDV2
t
LLAX
t
PXIX
t
PLIV
t
OPCODE
t
QVWX
t
AVWL2
t
DATA
WHLH
t
WHQX
t
WLWH
t
Port 2
LSB
LSB LSB LSB
Figure 3. Page Mode 2 Timing
XTAL1
t
CLCL
ALE
t
AVLL
t
AVLL2
SEN
D
R
Port 0
Port 2
MSB
t
LLPL
t
PLIV
t
AVIV0
t
PXIX
t
LLIV
t
t
LLAX
OPCODE DATA
MOVX MOVX
PXIZ
t
PLPH
MSB LSB MSBMSB MSB LSB
t
LHLL
t
t
AVLL3
LLAX2
t
t
t
AVDV0
t
AVDV2
t
LLDV
t
RLRH
AVWL2
LLAX3
t
RLDV
t
PLAZ
t
RHDX
t
RHDZ
MSB
t
AVIV2
LSBLSB LSB LSBLSB
t
AVWL0
OPCODE
t
WLWH
t
WHLH
t
LLWL
t
WHQX
LSB
t
QVWX
MSB MSB
DATA
8 of 48
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
EXTERNAL CLOCK CHARACTERISTICS
(V
= 4.5V to 5.5V, TO = -40°C to +85°C.)
CC
PARAMETER SYMBOL MIN MAX UNITS
Clock High Time t
Clock Low Time t
Clock Rise Time t
Clock Fall Time t
10 ns
CHCX
10 ns
CLCX
5 ns
CLCH
5 ns
CHCL
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
(V
= 4.5V to 5.5V, TO = -40°C to +85°C.) (Figure 4)
CC
PARAMETER SYMBOL CONDITIONS
SM2 = 0 360 12t
Clock Cycle Time t
XLXL
SM2 = 1 120 4t
Output Data Setup to Clock
Rising
t
QVXH
SM2 = 0 200
SM2 = 1 40 3t
Output Data Hold to Clock
Rising
t
XHQX
SM2 = 0 50 2t
SM2 = 1 20 t
33MHz VARIABLE
MIN MAX MIN MAX
ns
CLCL
ns
CLCL
10t
-
CLCL
100
- 10 ns
CLCL
- 10 ns
CLCL
- 100
CLCL
UNITS
ns
Input Data Hold After Clock
Rising
Clock Rising Edge to Input
Data Valid
Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal
clocks in a serial port clock cycle.
t
XHDX
t
XHDV
SM2 = 0 0 0 ns
SM2 = 1 0 0
SM2 = 0 200 10t
- 100 ns
CLCL
SM2 = 1 40 3t
- 50 ns
CLCL
9 of 48
Figure 4. Serial Port Timing
SERIAL PORT (SYNCHRONOUS MODE)
SM2 = 1 TDX CLOCK = XTAL FREQ/4
ALE
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PSEN
WRITE TO SBUF
RXD DATA OUT
TXD CLOCK
TI
WRITE TO SCON
TO CLEAR RI
RXD DATA IN
TXD CLOCK
R1
t
QVXH
D0 DI D3 D4D2 D5 D6 D7
t
XLXL
t
XHDV
SERIAL PORT (SYNCHRONOUS MODE)
SM2 = 0 TDX CLOCK = XTAL FREQ/12
ALE
PSEN
WRITE TO SBUF
RXD DATA OUT
TXD CLOCK
t
XHQX
D7D6D5D4D3D2DID0
t
XHDX
1/(XTAL FREQ/12)
D0 DI D6 D7
TRANSMIT
RECEIVE
T
R
A
N
S
M
I
T
WRITE TO SCON
TXD CLOCK
TO CLEAR RI
RXD DATA IN
TXD CLOCK
TI
R1
D0 DI D6 D7
10 of 48
R
E
C
E
I
V
E
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
POWER-CYCLE TIMING CHARACTERISTICS
(VCC = 4.5V to 5.5V, TO = -40°C to +85°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS
Crystal Startup Time (Note 18) t
Power-On Reset Delay (Note 19)
Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an 11.0592MHz crystal manufactured
Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin
by Fox Electronics.
meets the V
criteria. At 33MHz, this time is 1.99ms.
IH2
8 ms
CSU
65,536 t
t
POR
CLCL
FLASH MEMORY PROGRAMMING CHARACTERISTICS
(VCC = 4.5V to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS
Data Retention (Note 20) tDR 100 years
Write/Erase Endurance t
Program/Time t
Erase Time t
Note 20: At room temperature.
20,000 cycles
ENDURE
40 ms
PROG
4 ms
ERASE
11 of 48
PIN DESCRIPTION
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PIN
PDIP PLCC TQFP
40 12, 44 6, 38 VCC
1, 22, 23,
20
9 10 4 RST
19 21 15 XTAL1
18 20 14 XTAL2
29 32 26
30 33 27
39 43 37 P0.0 (AD0)
38 42 36 P0.1 (AD1)
37 41 35 P0.2 (AD2)
36 40 34 P0.3 (AD3)
35 39 33 P0.4 (AD4)
34 38 32 P0.5 (AD5)
33 37 31
32 36 30
34
16, 17, 28,
39
NAME FUNCTION
GND
PSEN
ALE/PROG
P0.6 (AD6)
P0.7 (AD7)
+5V
Logic Ground
External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to
recognize external active-high reset inputs. The pin also employs an internal pulldown
resistor to allow for a combination of wire-ORed external reset sources. An RC is not
required for power-up, as the device provides this function internally.
Crystal Oscillators. These pins provide support for fundamental-mode parallel-resonant
AT-cut crystals. XTAL1 also acts as an input if there is an external clock source in place of
a crystal. XTAL2 serves as the output of the crystal amplifier.
Program Store Enable. This signal is commonly connected to optional external program
memory as a chip enable. PSEN provides an active-low pulse and is driven high when
external program memory is not being accessed. In one-cycle page mode 1, PSEN
remains low for consecutive page hits.
Address Latch Enable. This signal functions as a clock to latch the external address LSB
from the multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373-family transparent latch. In default mode, ALE has a pulse
width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE
pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE
is high when using the EMI reduction mode and during a reset condition. ALE can be
enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON
during external memory accesses. As an alternate mode, this pin (PROG) is used to
execute the parallel program function.
Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an
alternate function, Port 0 can function as the multiplexed address/data bus to access offchip memory. During the time when ALE is high, the LSB of a memory address is
presented. When ALE falls to logic 0, the port transitions to a bidirectional data bus. This
bus is used to read external program memory and read/write external RAM or peripherals.
When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset
condition of port 0 is tri-state. Pullup resistors are required only when using port 0 as an
I/O port.
12 of 48
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
PIN DESCRIPTION (continued)
PIN
PDIP PLCC TQFP
1 2 40 P1.0
2 3 41 P1.1
3 4 42 P1.2
4 5 43 P1.3
5 6 44 P1.4
6 7 1 P1.5
7 8 2 P1.6
8 9 3 P1.7
21 24 18 P2.0 (A8)
22 25 19 P2.1 (A9)
23 26 20 P2.2(A10)
24 27 21 P2.3(A11)
25 28 22 P2.4(A12)
26 29 23 P2.5(A13)
27 30 24 P2.6(A14)
28 31 25 P2.7(A15)
10 11 5 P3.0
11 13 7 P3.1
12 14 8 P3.2
13 15 9 P3.3
14 16 10 P3.4
15 17 11 P3.5
16 18 12 P3.6
17 19 13 P3.7
NAME FUNCTION
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate
functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The
reset condition of port 1 is with all bits at logic 1. In this state, a weak pullup holds the port
high. This condition also serves as an input state, since any external circuit that writes to
the port overcomes the weak pullup. When software writes a 0 to any port pin, the
DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on until either
a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong
transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary
strong driver turns off, the port again becomes the output high (and input) state. The
alternate functions of port 1 are as follows:
PORT ALTERNATE FUNCTION
P1.0 T2 External I/O for Timer/Counter2
P1.1 T2EX Timer 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Receive
P1.3 TXD1 Serial Port 1 Transmit
P1.4 INT2 External Interrupt 2 (Positive Edge Detect)
P1.5 INT3 External Interrupt 3 (Negative Edge Detect)
P1.6 INT4 External Interrupt 4 (Positive Edge Detect)
P1.7 INT5 External Interrupt 5 (Negative Edge Detect)
Port 2 (A8–A15), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset condition of port 2
is logic high. In this state, a weak pullup holds the port high. This condition also serves as
an input mode, since any external circuit that writes to the port overcomes the weak
pullup. When software writes a 0 to any port pin, the DS89C430/DS89C440/DS89C450
activate a strong pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 causes a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the
port again becomes both the output high and input state. As an alternate function, port 2
can function as the MSB of the external address bus when reading external program
memory and read/write external RAM or peripherals. In page mode 1, port 2 provides both
the MSB and LSB of the external address bus. In page mode 2, it provides the MSB and
data.
Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate
functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and RD and
WR strobes. The reset condition of port 3 is with all bits at a logic 1. In this state, a weak
pullup holds the port high. This condition also serves as an input mode, since any external
circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any
port pin, the DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on
until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes
a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes both the output high and input
state. The alternate modes of port 3 are as follows:
PORT ALTERNATE FUNCTION
P3.0 RXD0 Serial Port 0 Receive
P3.1 TXD0 Serial Port 0 Transmit
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
P3.6 WR External Data Memory Write Strobe
P3.7 RD External Data Memory Read Strobe
31 35 29
EA
External Access. Allows selection of internal or external program memory. Connect to
ground to force the DS89C430/DS89C440/DS89C450 to use an external memory program
memory. The internal RAM is still accessible as determined by register settings. Connect
to use internal flash memory.
to V
CC
13 of 48
Figure 5. Functional Diagram
P
E
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
CONTROL
AND
SEQUENCER
DECODER
IR
INTERNAL CONTROL BUS
SERIAL I/O
WATCHDOG TIMER
AND
POWER MANAGER
Dallas Semiconductor
DS89C430/DS89C440/
DS89C450
INTERNAL
REGISTERS
TIMER/
COUNTERS
CLOCK
AND
RESET
XTAL2
XTAL1
INTERRUPT
CPU
1kB x 8
RAM
MEMORY
CONTROL
A
RST
SEN
SFRs
DPTR
DPTR1
SP
16kB/32kB
64kB x 8
FLASH
ROM
LOADER
PROG
PC
AR INC
AR
ADDRESS BUS
I/O PORTS
P0 P1
P2 P3
ALE/
DETAILED DESCRIPTION
The DS89C430, DS89C440, and DS89C450 are pin compatible with all three packages of the standard 8051 and
include standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. The three part
numbers vary only by the amount of internal flash memory (DS89C430 = 16kB, DS89C440 = 32kB, DS89C450 =
64kB), which can be in-system/in-application programmed from a serial port using ROM-resident or user-defined
loader software. For volume deployments, the flash can also be loaded externally using standard commercially
available parallel programmers.
Besides greater speed, the DS89C430/DS89C440/DS89C450 include 1kB of data RAM, a second full hardware
serial port, seven additional interrupts, two extra levels of interrupt priority, programmable watchdog timer,
brownout monitor, and power-fail reset. Dual data pointers (DPTRs) are included to speed up block data-memory
moves with further enhancements coming from selectable automatic increment/decrement and toggle select
operation. The speed of MOVX data memory access can be adjusted by adding stretch values up to 10 machine
cycles for flexibility in selecting external memory and peripherals.
A power management mode consumes significantly lower power by slowing the CPU execution rate from one clock
period per cycle to 1024 clock periods per cycle. A selectable switchback feature can automatically cancel this
mode to enable normal speed responses to interrupts.
For EMI-sensitive applications, the microcontroller can disable the ALE signal when the processor is not accessing
external memory.
14 of 48
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Terminology
The term DS89C430 is used in the remainder of the document to refer to the DS89C430, DS89C440, and
DS89C450, unless otherwise specified.
Compatibility
The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the
DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket
for the 8xC51 family, immediately improving the operation. While remaining familiar to 8051 family users, the
DS89C430 has many new features. In general, software written for existing 8051-based systems works without
modification on the DS89C430, with the exception of critical timing routines, as the DS89C430 performs its
instructions much faster for any given crystal selection.
The DS89C430 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus
1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to 12 clocks-percycle operation to keep their timing compatible with a legacy 8051 family systems. However, timers are individually
programmable to run at the new one clock per cycle if desired. The DS89C430 provides several new hardware
features, described in subsequent sections, implemented by new special-function registers (SFRs).
Performance Overview
Featuring a completely redesigned high-speed 8051-compatible core, the DS89C430 allows operation at a higher
clock frequency. This updated core does not have the wasted memory cycles that are present in a standard 8051.
A conventional 8051 generates machine cycles using the clock frequency divided by 12. The same machine cycle
takes one clock in the DS89C430. Thus, the fastest instructions execute 12 times faster for the same crystal
frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed
improvement is reduced when using external memory access modes that require more than one clock per cycle.
Individual program improvement depends on the instructions used. Speed-sensitive applications would make the
most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes makes
dramatic speed improvements likely for any code. These architectural improvements produce instruction cycle
times as low as 30ns. The dual data pointer feature also allows the user to eliminate wasted instructions when
moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses.
Instruction Set Summary
All instructions have the same functionality as their 8051 counterparts, including their affect on bits, flags, and other
status functions. However, the timing of each instruction is different, in both absolute and relative number of clocks.
For absolute timing of real-time events, the duration of software loops can be calculated using information given in
the Instruction Set table in the Ultra-High-Speed Flash Microcontroller User’s Guide. However, counter/timers
default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals
with software executing at higher speed. Timers optionally can run at a reduced number of clocks per increment to
take advantage of faster processor operation.
The relative time of some instructions may be different in the new architecture. For example, in the original
architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles
or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C430, the MOVX instruction
takes as little as two machine cycles or two oscillator cycles, but the “MOV direct, direct” uses three machine cycles
or three oscillator cycles. While both are faster than their original counterparts, they now have different execution
times. This is because the DS89C430 usually uses one machine cycle for each instruction byte and requires one
cycle for execution. The user concerned with precise program timing should examine the timing of each instruction
to become familiar with the changes.
Special-Function Registers (SFRs)
All peripherals and operations that are not explicit instructions in the DS89C430 are controlled through SFRs. The
most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC,
B, and PSW), data pointers, stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR
controls an individual function or reports the function’s status. The SFRs reside in register locations 80h–FFh and
are only accessible by direct addressing. SFRs with addresses ending in 0h or 8h are bit addressable.
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