DS8024
Smart Card Interface
________________________________________________________________
Maxim Integrated Products
1
Rev 1; 8/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The DS8024 smart card interface IC is a low-cost, analog
front-end for a smart card reader, designed for all ISO
7816, EMV*, and GSM11-11 applications. The DS8024 is
a pin-for-pin drop-in replacement for the NXP TDA8024
and is offered in 28-pin TSSOP and SO packages.
Applications requiring support for 1.8V smart cards or
requiring low power should consider the DS8113, which
achieves lower active- and stop-mode power with minimal changes to application hardware and software.
Applications
Set-Top Box Conditional Access
Access Control
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PIN Pads
Automated Teller Machines
Telecommunications
Pay/Premium Television
Features
♦ Analog Interface and Level Shifting for IC Card
Communication
♦ 8kV (min) ESD (IEC) Protection on Card Interfaces
♦ Internal IC Card Supply-Voltage Generation:
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦ I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦ Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦ High-Current, Short-Circuit and High-Temperature
Protection
Ordering Information
Note: Contact the factory for availability of other variants and
package options.
+
Denotes a lead-free/RoHS-compliant package.
*EMV is a trademark owned by EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata
.
Selector Guide appears at end of data sheet.
PGND
28
27
26
25
24
23
22
AUX2IN
AUX1IN
I/OIN
XTAL2
TOP VIEW
DS8024
XTAL1
OFF
GND
21 V
DD
20 RSTIN
19 CMDVCC
18 N.C.
17 V
CC
16 RST
15 CLK
5V/3V
CLKDIV2
CLKDIV1
CP1
V
DDA
V
UP
PRES
PRES
I/O
AUX2
AUX1
4
1
2
3
5
6
7
8
9
10
11
12
13
14CGND
CP2
SO/TSSOP
Pin Configuration
PART TEMP RANGE PIN-PACKAGE
DS8024-RJX+ -40°C to +85°C 28 TSSOP
DS8024-RRX+ -40°C to +85°C 28 SO
DS8024
Smart Card Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(VDD= +3.3V, V
DDA
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDDRelative to GND ...............-0.5V to +6.5V
Voltage Range on V
DDA
Relative to PGND ...........-0.5V to +6.5V
Voltage Range on CP1, CP2, and V
UP
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Relative to GND......................................-0.5V to (V
DD
+ 0.5V)
Maximum Junction Temperature .....................................+125°C
Maximum Power Dissipation (T
A
= -25°C to +85°C) .......700mW
Storage Temperature Range .............................-55°C to +150°C
Soldering Temperature.........Refer to the IPC/JEDEC J-STD-020
Specification.
POWER SUPPLY
Digital Supply Voltage VDD 2.7 6.0 V
Card Voltage-Generator Supply Voltage V
Reset Voltage Thresholds
CURRENT CONSUMPTION
Active VDD Current 5V Cards
(Including 80mA Draw from 5V Card)
Active VDD Current 5V Cards
(Current Consumed by DS8024 Only)
Active VDD Current 3V Cards
(Including 65mA Draw from 3V Card)
Active VDD Current 3V Cards
(Current Consumed by DS8024 Only)
Inactive-Mode Current IDD Card inactive 500 μA
CLOCK SOURCE
Crystal Frequency f
XTAL1 Operating Conditions
External Capacitance for Crystal
Internal Oscillator f
SHUTDOWN TEMPERATURE
Shutdown Temperature TSD (Note 3) +150 °C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DDA
V
Threshold voltage (falling) 2.30 2.45 2.60 V
TH2
Hysteresis 50 100 150 mV
V
HYS2
I
DD_50V
I
DD_IC
I
DD_30V
I
DD_IC
External crystal 0 20 MHz
XTAL
f
XTAL1
V
IL_XTAL1
V
IH_XTAL1
C
C
Low-level input on XTAL1 (Note 3) -0.3
High-level input on XTAL1 (Note 3)
,
XTAL1
XTAL2
2.7 MHz
INT
VCC= 5V, |ICC| < 80mA 4.0 6.0
VCC= 5V, |ICC| < 30mA 3.0 6.0
ICC = 80mA, f
= 10MHz, V
f
CLK
ICC = 80mA, f
= 10MHz, V
f
CLK
ICC = 65mA, f
f
= 10MHz, V
CLK
ICC = 65mA, f
f
= 10MHz, V
CLK
XTAL
DDA
= 20MHz,
XTAL
DDA
XTAL
DDA
= 20MHz,
XTAL
DDA
= 20MHz,
= 20MHz,
= 5.0V
= 5.0V (Note 2)
= 5.0V
= 5.0V (Note 2)
215 mA
135 mA
100 mA
35 mA
V
0 20 MHz
0.3 x
V
0.7 x
V
DD
DD
VDD +
0.3
V
(Note 3) 15 pF
DS8024
Smart Card Interface
_______________________________________________________________________________________ 3
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
DDA
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RST PIN
Card-Inactive Mode
Card-Active Mode
Output Low Voltage V
Output Current I
Output Low Voltage V
Output High
Voltage
V
Rise Time t
Fall Time t
Shutdown Current
Threshold
Current Limitation I
RSTIN to RST Delay t
D(RSTIN-RST)
OL_RST1
OL_RST1
OL_RST2
OH_RST2
I
RST(SD)
RST(LIMIT)
I
V
I
I
CL= 30pF (Note 3) 0.1 μs
R_RST
CL= 30pF (Note 3) 0.1 μs
F_RST
= 1mA 0 0.3 V
OL_RST
= 0V 0 -1 mA
O_LRST
= 200μA 0 0.3 V
OL_RST
V
-
OH_RST
= -200μA
CC
0.5
V
CC
-20 mA
-20 +20 mA
2 μs
V
CLK PIN
Card-Inactive Mode
Card-Active Mode
Output Low Voltage V
Output Current I
Output Low Voltage V
Output High
Voltage
Rise Time t
Fall Time t
Current Limitation I
Clock Frequency f
OL_CLK1 IOLCLK
OL_CLK1
V
OH_CLK2 IOHCLK
CLK(LIMIT)
V
OL_CLK2
I
CL= 30pF (Note 3) 8 ns
R_CLK
CL= 30pF (Note 3) 8 ns
F_CLK
-70 +70 mA
Operational (Note 3) 0 10 MHz
CLK
Duty Factor C
Slew Rate SR C
= 1mA 0 0.3 V
= 0V 0 -1 mA
OLCLK
= 200μA 0 0.3 V
OLCLK
V
-
= -200μA
= 30pF (Note 3) 45 55 %
L
= 30pF (Note 3) 0.2 V/ns
L
CC
0.5
V
V
CC
VCC PIN
Card-Inactive Mode
Output Low Voltage V
Output Current I
ICC= 1mA 0 0.3 V
CC1
VCC = 0V 0 -1 mA
CC1
I
< 80mA 4.75 5.00 5.25
CC(5V)
I
< 65mA 2.78 3.00 3.22
CC(3V)
5V card: current pulses of 40nC
Output Low Voltage V
CC2
with I < 200mA, t < 400ns,
f < 20MHz (Note 3)
4.6 5.4
V
3V card: current pulses of 24nC
Card-Active Mode
with I < 200mA, t < 400ns,
2.75 3.25
f < 20MHz (Note 3)
Output Current I
Shutdown Current
Threshold
I
Slew Rate V
CC2
CC(SD)
CCSR
V
V
120 mA
Up/down, C < 300nF 0.05 0.16 0.22 V/μs
= 0 to 5V -80
CC(5V)
= 0 to 3V -65
CC(3V)
mA
DS8024
Smart Card Interface
4 _______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
DDA
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DATA LINES (I/O AND I/OIN)
I/O I/OIN Falling Edge Delay t
Pullup Pulse Active Time tPU (Note 3) 100 ns
Maximum Frequency f
Input Capacitance CI (Note 3) 10 pF
I/O, AUX1, AUX2 PINS
Card-Inactive Mode
Card-Active Mode
I/OIN, AUX1IN, AUX2IN PINS
Output Low Voltage VOL IOL = 1mA 0 0.3 V
Output High Voltage VOH IOH < -40μA
Output Rise/Fall Time tOT CL= 30pF, 10% to 90% (Note 3) 0.1 μs
Input Low Voltage VIL -0.3
Input High Voltage V
Input Low Current I
Input High Current I
Input Rise/Fall Time tIT V
Integrated Pullup Resistor RPU Pullup to VDD 9 11 13 k
Current When Pullup Active I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
D(IO-IOIN)
Output Low Voltage V
Output Current I
Internal Pullup
Resistor
Output Low Voltage V
Output High
Voltage
V
Output Rise/Fall
Time
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
R
(Note 3) 200 ns
1 MHz
IOMAX
I
OL_IO1
V
OL_IO1
To VCC 9 11 19 k
PU_IO
OL_IO2 IOL_IO
I
OH_IO2
CL= 30pF (Note 3) 0.1 μs
t
OT
-0.3 +0.8
IL_IO
1.5 V
IH_IO
IL_IO
V
IH_IO
= 1mA 0 0.3 V
OL_IO
= 0V 0 -1 mA
OL_IO
= 1mA 0 0.3 V
= < -40μA (3V/5V) 0.75 x VCC VCC V
OH_IO
CC
V
= 0V 700 μA
IL_IO
= VCC 20 μA
IH_IO
V
Input Rise/Fall Time tIT (Note 3) 1.2 μs
Current Limitation I
Current When
Pullup Active
CL= 30pF -15 +15 mA
IO(LIMIT)
I
PU
IH
IL_IO
IH_IO
PU
CL= 80pF, VOH = 0.9 x V
(Note 3)
VIL = 0V 600 μA
VIH = VDD 10 μA
to VIH (Note 3) 1.2 μs
IL
CL= 30pF, VOH = 0.9 x V
(Note 3)
DD
DD
-1 mA
0.75 x
V
DD
0.7 x
V
DD
VDD +
0.1
0.3 x
V
DD
VDD +
0.3
V
V
V
-1 mA
DS8024
Smart Card Interface
_______________________________________________________________________________________ 5
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
DDA
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
Note 1: Operation guaranteed at TA= -40°C and TA= +85°C, but not tested.
Note 2: IDD_IC measures the amount of current used by the DS8024 to provide the smart card current minus the load.
Note 3: Guaranteed by design, but not production tested.
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
Integrated Pullup Resistor RPU Pullup to VDD, 5V/3V only 50 85 120 k
INTERRUPT OUTPUT PIN (OFF)
Output Low Voltage VOL IOL = 2mA 0 0.3 V
Output High Voltage VOH IOH = -15μA
Integrated Pullup Resistor RPU Pullup to VDD 12 20 28 k
PRES, PRE S PINS
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
TIMING
Activation Time t
Deactivation Time t
CLK to Card Start
Time
PRES/PRES Debounce Time t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IL
IH
IL_IO
IH_IO
IL_PRES
IH_PRES
IL_PRES
IH_PRES
ACT
DEACT
Window Start t3 95
Window End t
160
5
DEBOUNCE
-0.3
0.7 x
V
DD
0 < VIL < VDD 5 μA
0 < VIH < VDD 5 μA
0.75 x
V
DD
0.7 x
V
DD
V
V
160 μs
80 μs
8 ms
= 0V 40 μA
IL_PRES
= VDD 40 μA
IH_PRES
0.3 x
V
DD
VDD +
0.3
V
0.3 x
V
DD
V
V
V
V
μs
DS8024
Smart Card Interface
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 2
3 5V/3V
4 PGND Analog Ground
5, 7 CP2, CP1
6 V
8 VUP Charge-Pump Output. Connect a 100nF capacitor (ESR < 100m) between VUP and GND.
9 PRES
10 PRES
11 I/O Smart Card Data-Line Output. Card data communication line, contact C7.
12, 13
14 CGND Smart Card Ground
15 CLK Smart Card Clock. Card clock, contact C3.
16 RST Smart Card Reset. Card reset output from contact C2.
17 V
18 N.C. No Connection. Unused on the DS8024.
19 CMDVCC Activation Sequence Initiate. Active-low input from host.
20 RSTIN Card Reset Input. Reset input from the host.
21 VDD Supply Voltage
22 GND Digital Ground
23 OFF Status Output. Active-low interrupt output to the host. Use a 20k integrated pullup resistor to VDD.
24, 25
26 I/OIN I/O Input. Host-to-interface chip data I/O line.
27, 28
CLKDIV1,
CLKDIV2
DDA
AUX2,
AUX1
CC
XTAL1,
XTAL2
AUX1IN,
AUX2IN
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects
5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card
voltages.
Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100m)
between CP1 and CP2.
Charge-Pump Supply. Must be equal to or higher than VDD. Connect a supply of at least 3.3V.
Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and
C8 (AUX2).
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m).
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1.
C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
DS8024
Smart Card Interface
_______________________________________________________________________________________ 7
Detailed Description
The DS8024 is an analog front-end for communicating
with 3V and 5V smart cards. Using an integrated
charge pump, the DS8024 can operate from a single
input voltage. The device translates all communication
lines to the correct voltage level and provides power for
smart card operation. It can operate from a wide input
voltage range (3.3V to 6.0V). The DS8024 is compatible
with the NXP TDA8024 and is provided in the same
packages. (Note that the PORADJ pin is not present in
the DS8024. Most applications do not make use of this
input pin, instead using the DS8024’s default reset
threshold.)
Power Supply
The DS8024 can operate from a single supply or a dual
supply. The supply pins for the device are V
DD
, GND,
V
DDA
, and PGND. VDDshould be in the range of 2.7V
to 6.0V, and is the supply for signals that interface with
the host controller. It should, therefore, be the same
supply as used by the host controller. All smart card
contacts remain inactive during power on or power off.
The internal circuits are kept in the reset state until V
DD
reaches V
TH2
+ V
HYS2
and for the duration of the internal power-on reset pulse, tW. A deactivation sequence
is executed when VDDfalls below V
TH2
.
An internal charge pump and regulator generate the
3V or 5V card supply voltage (VCC). The charge pump
and regulator are supplied by V
DDA
and PGND. V
DDA
should be connected to a minimum 3.3V (maximum
6.0V) supply and should be at a potential that is equal
to or higher than VDD.
The charge pump operates in a 1x (voltage follower) or
2x (voltage doubler) mode depending on the input
V
DDA
and the selected card voltage (5V or 3V).
• For 5V cards, the DS8024 operates in a 1x mode
for V
DDA
> 5.8V and in a 2x mode for V
DDA
< 5.8V.
• For 3V cards, the DS8024 operates in a 1x mode
for V
DDA
> 4.1V and in a 2x mode for V
DDA
< 4.0V.
Voltage Supervisor
The voltage supervisor monitors the VDDsupply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power on or power off of the V
DD
supply. See Figure 2.
Figure 1. Functional Diagram
Figure 2. Voltage Supervisor Behavior
V
DDA
PGND
CP1
CP2
V
UP
V
CC
CGND
RST
CLK
PRES
PRES
I/O
AUX1
AUX2
V
GND
XTAL1
XTAL2
CLKDIV1
CLKDIV2
5V/3V
CMDVCC
RSTIN
OFF
I/OIN
AUX1IN
AUX2IN
DD
POWER-SUPPLY
SUPERVISOR
CLOCK
GENERATION
CARD VOLTAGE
GENERATOR
AND
CHARGE PUMP
TEMPERATURE
MONITOR
CONTROL
SEQUENCER
I/O TRANSCEIVER
DS8024
V
DD
(INTERNAL SIGNAL)
ALARM
t
W
POWER ON
t
W
SUPPLY DROPOUT
+ V
V
TH2
V
TH2
POWER OFF
HYS2
DS8024
Smart Card Interface
8 _______________________________________________________________________________________
The DS8024 card interface remains inactive no matter
the levels on the command lines until duration tWafter
VDDhas reached a level higher than V
TH2
+ V
HYS2
.
When VDDfalls below V
TH2
, the DS8024 executes a
card deactivation sequence if its card interface is
active.
Clock Circuitry
The clock signal from the DS8024 to the smart card
(CLK) is generated from the clock input on XTAL1 or
from a crystal operating at up to 20MHz connected
between pins XTAL1 and XTAL2. The inputs CLKDIV1
and CLKDIV2 determine the frequency of the CLK signal, which can be f
XTAL
, f
XTAL/2
, f
XTAL/4
, or f
XTAL/8
.
Table 1 shows the relationship between CLKDIV1 and
CLKDIV2 and the frequency of CLK.
Do not change the state of pins CLKDIV1 and CLKDIV2
simultaneously; a delay of 10ns minimum between
changes is required. The minimum duration of any state
of CLK is 8 periods of XTAL1.
The hardware in the DS8024 guarantees that the frequency change is synchronous. During a transition of
the clock divider, no pulse is shorter than 45% of the
smallest period, and the clock pulses before and after
the instant of change have the correct width.
To achieve a 45% to 55% duty factor on pin CLK when
no crystal is present, the input signal on XTAL1 should
have a 48% to 52% duty factor. Transition time on
XTAL1 should be less than 5% of the period.
With a crystal, the duty factor on pin CLK may be 45%
to 55% depending on the circuit layout and on the crystal characteristics and frequency.
The DS8024 crystal oscillator runs when the device is
powered up. If the crystal oscillator is used or the clock
pulse on pin XTAL1 is permanent, the clock pulse is
applied to the card at time t4(see Figures 7 and 8). If
the signal applied to XTAL1 is controlled by the host
microcontroller, the clock pulse is applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
I/O Transceivers
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
I/O and I/OIN are pulled high with an 11kΩ resistor (I/O
to V
CC
and I/OIN to VDD) in the inactive state. The first
side of the transceiver to receive a falling edge
becomes the master. When the master is decided, the
opposite side switches to slave mode, ignoring subsequent edges until the master releases. After a time delay
t
D(EDGE)
, an n transistor on the slave side is turned on,
thus transmitting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay t
PU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high transitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
Inactive Mode
The DS8024 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω
to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the highimpedance state (11kΩ pullup resistor to VDD).
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency.
Activation Sequence
After power-on and the reset delay, the host microcontroller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Table 1. Clock Frequency Selection
Table 2. Card Presence Indication
CLKDIV1 CLKDIV2 f
0 0 f
0 1 f
1 1 f
1 0 f
CLK
XTAL
XTAL
XTAL
XTAL
/8
/4
/2
OFF CMDVC C STATUS
High High Card present.
Low High Card not present.
DS8024
Smart Card Interface
_______________________________________________________________________________________ 9
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
1) Host: CMDVCC is pulled low.
2) DS8024: The internal oscillator changes to high
frequency (t0).
3) DS8024: The voltage generator is started
(between t
0
and t1).
4) DS8024: V
CC
rises from 0 to 5V or 3V with a controlled slope (t2= t1+ 1.5 × T). T is 64 times the
internal oscillator period (approximately 25µs).
5) DS8024: I/O, AUX1, and AUX2 are enabled (t3=
t1+ 4T).
6) DS8024: The CLK signal is applied to the C3 contact (t4).
7) DS8024: RST is enabled (t5= t1+ 7T).
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t
3
and t5; CLK will now
start.
4) DS8024: RST stays low until t
5
, then RST becomes
the copy of RSTIN.
5) DS8024: RSTIN has no further effect on CLK after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t3(minimum
200ns after the transition on I/O, see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform activation with RSTIN held permanently high.
Active Mode
When the activation sequence is completed, the
DS8024 card interface is in active mode. The host
microcontroller and the smart card exchange data on
the I/O lines.
Figure 3. Activation Sequence Using RSTIN and CMDVCC
CMDVCC
V
CC
I/O
CLK
RSTIN
RST
I/OIN
t
0t1
t
2
t
3
ATR
t
t5 = t
4
ACT
DS8024
Smart Card Interface
10 ______________________________________________________________________________________
Figure 4. Activation Sequence at t
3
Figure 5. Deactivation Sequence
CMDVCC
V
CC
I/O
CLK
RSTIN
RST
I/OIN
CMDVCC
RST
t
0t1
ATR
200ns
t
2
t3t
4
t5 = t
ACT
CLK
I/O
V
CC
t
10
t
12
t
13
t
DE
t
14
t
15
DS8024
Smart Card Interface
______________________________________________________________________________________ 11
Deactivation Sequence
When the host microcontroller is done communicating
with the smart card, it sets the CMDVCC line high to
execute an automatic deactivation sequence and
returns the card interface to the inactive mode.
The following sequence of events occurs during a
deactivation sequence (Figure 5):
1) RST goes low (t10).
2) CLK is held low (t
12
= t10+ 0.5 × T), where T is 64
times the period of the internal oscillator (approximately 25µs).
3) I/O, AUX1, and AUX2 are pulled low (t13= t10+ T).
4) V
CC
starts to fall (t14= t10+ 1.5 × T).
5) When V
CC
reaches its inactive state, the deactiva-
tion sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at VDD(pulled
up through an 11kΩ resistor).
7) The internal oscillator returns to its lower frequency.
V
CC
Generator
The card voltage (VCC) generator can supply up to
80mA continuously at 5V or 65mA at 3V. An internal
overload detector triggers at approximately 120mA.
Current samples to the detector are filtered. This allows
spurious current pulses (with a duration of a few µs) up
to 200mA to be drawn without causing deactivation.
The average current must stay below the specified
maximum current value.
See the
Applications Information
section for recommen-
dations to help maintain VCCvoltage accuracy.
Fault Detection
The DS8024 integrates circuitry to monitor the following
fault conditions:
• Short-circuit or high current on V
CC
• Card removal while the interface is activated
•VDDdropping below threshold
• Card voltage generator operating out of the specified values (V
DDA
too low or current consumption
too high)
• Overheating
There are two different cases for how the DS8024
reacts to fault detection (Figure 6):
• Outside a Card Session (CMDVCC High). Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The V
DD
supply is
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and temperature detection are disabled because the card is
not powered up.
• Within a Card Session (CMDVCC Low). Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed automatically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present). Depending on the connector’s card-present switch (normally closed or
normally open) and the mechanical characteristics
of the switch, bouncing can occur on the PRES signals at card insertion or withdrawal.
The DS8024 has a debounce feature with an 8ms typical duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
Stop Mode (Low-Power Mode)
The DS8024 (like the TDA8024) does not support a lowpower stop mode. For applications requiring low-power
support, refer to the DS8113.
Smart Card Power Select
The DS8024 supports two smart card VCCvoltages: 3V
and 5V. The power select is controlled by the 5V/3V
signal as shown in Table 3. VCCis 5V if 5V/3V is asserted to a logic-high state, and VCCis 3V if 5V/3V is pulled
to a logic-low state.
Table 3. VCCSelect and Operation Mode
V
5V/3V CMDVCC
0 0 3 Activated
0 1 3 Inactivated
1 0 5 Activated
1 1 5 Inactivated
CC
SELECT (V)
CARD INTERFACE
STATUS
DS8024
Smart Card Interface
12 ______________________________________________________________________________________
Figure 6. Behavior of PRES, OFF, CMDVCC, and V
CC
Figure 7. Emergency Deactivation Sequence (Card Extraction)
PRES
OFF
CMDVCC
DEBOUNCE DEBOUNCE
V
CC
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
OFF
PRES
RST
CLK
I/O
V
CC
DEACTIVATION CAUSED
BY SHORT CIRCUIT
t
10
t
12
t
13
t
DE
t
14
t
15
DS8024
Smart Card Interface
______________________________________________________________________________________ 13
MAXQ1103
Figure 8. Typical Application Diagram
GPIO
ISOIO0
V
DD
100nF
100nF
+10μF
PGND V
DDA
PRESGPIO
V
RST
CLK
AUX1
AUX2
CGND
+3.3V
100kΩ
CC
I/O
100nF* 220nF*
33pF
XTAL1 XTAL2 V
...
...
...
...
CLKDIV1
CLKDIV2
5V/3V
OFF
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
33pF
+3.3V
100nF 100nF
GND VDDCP1 CP2
DS8024
UP
CLKDIV1
GPIO
...
...
...
GPIO
ISOIO1
*PLACE A 100nF CAPACITOR CLOSE TO DS8024 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT.
CLKDIV2
5V/3V
OFF
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
XTAL1 XTAL2 V
33pF
GND VDDCP1 CP2
33pF
DS8024
100nF 100nF
+3.3V
UP
100nF
PGND V
+10μF
100nF
V
RST
CLK
AUX1
AUX2
CGND
PRES
DDA
V
DD
CC
I/O
100kΩ
+3.3V
100nF* 220nF*
DS8024
Smart Card Interface
14 ______________________________________________________________________________________
Applications Information
Performance can be affected by the layout of the application. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the
DS8024 and the connector; place the DS8024
very near to the connector; decouple the VDDand
V
DDA
lines separately. These lines are best posi-
tioned under the connector.
• The DS8024 and the host microcontroller must use
the same V
DD
supply. Pins CLKDIV1, CLKDIV2,
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
CMDVCC, and OFF are referenced to VDD; if pin
XTAL1 is to be driven by an external clock, also
reference this pin to VDD.
• Trace C3 (CLK) should be placed as far as possible from the other traces.
• The trace connecting CGND to C5 (GND) should
be straight (the two capacitors on C1 (VCC)
should be connected to this ground trace).
• Avoid ground loops among CGND, PGND, and GND.
• Decouple V
DDA
and VDDseparately; if the two
supplies are the same in the application, they
should be connected in a star on the main trace.
• Connect a 100nF capacitor (ESR < 100mΩ)
between V
CC
and CGND and place near the
DS8024’s VCCpin.
• Connect a 100nF or 220nF capacitor (220nF preferred, ESR < 100mΩ) between VCCand CGND
and place near the smart card socket’s C1 contact.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps.
Selector Guide
Note: Contact the factory for availability of other variants and
package options.
+
Denotes a lead-free/RoHS-compliant package.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 SO (300 mils) —
21-0042
28 TSSOP —
56-G2020-001
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
CURRENT
PART
DS8024-RJX+ 3.0, 5.0 No 28 TSSOP
DS8024-RRX+ 3.0, 5.0 No 28 SO
VOLTAGES
SUPPORTED (V)
SUPPORTS
STOP MODE
PINPACKAGE
DS8024
Smart Card Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient
conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding
the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMVCo does not warrant any
products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo approval does not under any
circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merchantability, fitness for purpose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and services which have received
EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in
connection therewith.
Revision History
REVISION
NUMBER
0 6/08
1 8/08
REVISION
DATE
DESCRIPTION
Initial release. —
Clarified the V
table.
specification in the Recommended DC Operating Conditions
DDA
PAGES
CHANGED
2
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