DS3904
DS3904 Triple 128-Position Nonvolatile
Variable Digital Resistor/Switch
4 ______________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: Applies to AO, SCL, SDA as well as H0, H1, and H2 in the high-impedance state.
Note 3: I
STBY
specified with SDA = SCL = VCCand A0 = GND.
Note 4: Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation
from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at
position 7Fh.
Note 5: Relative linearity is used to determine the change of resistance between two adjacent resistor positions.
Note 6: Temperature coefficient specifies the change in resistance as a function of temperature. The temperature
coefficient varies with resistor position. Guaranteed by design.
Note 7: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns =1250ns before the SCL line is released.
Note 8: After this period, the first clock pulse is generated.
Note 9: The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IN MIN
of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
Note 11: C
B
—total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCCand 0.1 x VCC.
Note 12: EEPROM write begins after a stop condition occurs.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.7V to +5.5V, TA= -40°C to +85°C.)