Rainbow Electronics DS3690 User Manual

DS3690

3.3V 26-Channel, Three-Stateable
Transmission Gate

________________________________________________________________

Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS3690 is a 26-channel, three-stateable transmis­sion gate designed for transparent digital signal trans­fer when enabled and fast-gated bus isolation when the
device is disabled. Each of the 26 independent chan­nels can be used for input, output, or I/O signal appli­cations, with a typical signal propagation delay of less
than 10ns. Using the logic-control input, all channels
can be simultaneously enabled for bus transmission or
forced to a high-impedance condition to isolate a criti­cal component on that bus.

The DS3690 operates on a single 3.3V (typical) power
supply and is available in a space-saving 56-pin lead­free TQFN package.

Applications

POS Terminals

PIN Pads

Cryptographic Processors

Gaming

Lottery Terminals

Industrial Controls and Monitoring

Features

♦ 26 Bidirectional Channels

♦ Low Propagation Delay (< 10ns typ)

♦ High-Speed On/Off Time (< 20ns typ)

♦ 2.7V to 3.6V Supply

♦ Wide Temperature Range: -55°C to +85°C

♦ TQFN Package (5mm x 11mm x 0.8mm)

Ordering Information

Rev 0; 10/07

+

Denotes a lead-free package.

TRL = Tape and reel.

×

Pin Configuration

Typical Operating Circuit appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

DS3690T+ -55°C to +85°C 56 TQFN

DS3690T+TRL -55°C to +85°C 56 TQFN

TOP VIEW

CH10B37CH12B36CH13B35CH14B

CH11B

CH24B

CH25B

CH26B

GND

CH26A

CH25A

CH24A

CH09B

CH05B42CH07B

CH04B

CH03B

CH02B

CH01B

44

43

45

46

47

48

49

50

51

CE

52

53

54

55

+

56

5

4

3

2

1

CH05A7CH07A

CH04A

CH03A

CH02A

CH01A

CH08B

CH06B

40

41

DS3690

EXPOSED PAD (ON BOTTOM)

9

8

6

CH09A

CH08A

CH06A

39

38

10

11

CH10A12CH12A13CH13A14CH14A

CH11A

CH16B31CH18B30CH19B29CH20B

CH15B

33

34

16

15

CH16A18CH18A19CH19A20CH20A

CH15A

TQFN

11mm × 0.8mm)

(5mm

32

17

CH17B

CH17A

28

CH21B

27

CH22B

26

CH23B

25

GND

24

V

CC

23

CH23A

22

CH22A

21

CH21A

DS3690

3.3V 26-Channel, Three-Stateable
Transmission Gate

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(TA= -55°C to +85°C)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on Any Pin Relative to Ground......-0.5V to +6.0V

Operating Temperature Range ...........................-55°C to +85°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature...................Refer to IPC/JEDEC J-STD-020

DC ELECTRICAL CHARACTERISTICS

(VCC= +2.7V to +3.6V, TA= -55°C to +85°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS

(VCC= +2.7V to +3.6V, TA= -55°C to +85°C, unless otherwise noted.)

Input Pulse Levels: VIL= 0.0V, VIH= 2.7V

Input Pulse Rise and Fall Times: 5ns

Input and Output Timing Reference Level: V

CC

/2

Output Load: C

L

(100pF)

AC TEST CONDITIONS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

Input Logic 1 V

Input Logic 0 V

PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS

Standby Current I
Input Leakage Current (CE) II VIN = 0V to VCC, TA = +25°C -0.1 +0.1 μA

I/O Leakage Current I

CC

(Note 1) 2.7 3.3 3.6 V

CC

(Note 1)

IH

(Note 1) -0.3

IL

CE = CH1  CH26 = VCC, I

CE = VIH -1.0 +1.0 μA

IO

= 0mA 1 μA

OUT

0.7 x
V

CC

VCC +

0.3

0.3 x
V

CC

V

V

PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS

Propagation De lay
(A to B or B to A)

Chip Enable to Output Valid t

Chip Enable to Output Deselect t
Input to CE Setup Time tIS (Note 4) 0 ns

Skew Between Channels tS (Notes 5, 6) 1 ns

t

CEV

CEZ

CE = VIL (Note 2) 10 ns

PD

(Notes 2, 3) 20 ns

(Notes 2, 3) 20 ns

DS3690

3.3V 26-Channel, Three-Stateable
Transmission Gate

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Note 1: All voltages referenced to ground.
Note 2: Typical waveform shown is labeled CHxxA (input) to CHxxB (output), and is identical in function when selecting pin CHxxB

(as the input) to pin CHxxA (as the output).

Note 3: Output reference level is V

CC

/2.

Note 4: Input transitions prior to the CE falling edge are ignored (don’t care).
Note 5: Propagation delay differential between any two channels when using a common input signal source.
Note 6: Guaranteed by design and not 100% tested.

CAPACITANCE

(TA= +25°C)

Timing Diagrams

CHxxA

CHxxB

t

PD

t

PD

t

PD

Figure 1. Digital Channel Propagation Delay

Figure 2. Digital Channels Enabled by CE

Figure 3. Digital Channels Disabled by CE

PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS

Input Capacitance (CE) CIN Not production tested 5 pF

I/O Capacitance CIO Not production tested 8 pF

CE

t

IS

CHxxA

CHxxB

DON'T

CARE

HIGH IMPEDANCE

t

CEV

CE

CHxxA

CHxxB

DON'T CARE

t

CEZ

HIGH IMPEDANCE