Rainbow Electronics DS33M33 User Manual

Rev: 111908

(

)

ABRIDGED DATA SHEET

DS33M30/DS33M31/DS33M33

Ethernet Over SONET/SDH Mapper

________________________ General Description

The DS33M30 family of products provides a compact and efficient solution for transporting Gigabit Ethernet traffic over OC-3/STM-1 optical networks. With the addition of an optical transceiver, Ethernet PHY, DDR SDRAM, and host processor, a complete solution of GbE over OC-3/STM-1 can be implemented. The family supports Ethernet over SONET/SDH (EoS) at VC-4, “Next-Generation” EoS high-order mapping with multiple concatenated VC-3s, and Ethernet over PDH over SONET/SDH (EoPoS) with up to three virtually concatenated DS3/E3 tributaries. The supported frame encapsulations include GFP-F, HDLC, cHDLC, and X.86 (LAPS).

_______________________________ Applications

Ethernet Service Delivery Over SONET/SDH Multiservice Provisioning Platforms (MSPPs) Transparent LAN Services LAN Extension

_____________________________________Features

♦ Support for EoS in One STS-3c/VC-4, EoS

Over Up to Three Concatenated STS-1/VC-3s, and EoPoS Over Up to Three Concatenated DS-3s

♦ Two Independent 155.52Mbps SerDes Ports ♦ One 10/100/1000 IEEE 802.3 Ethernet MAC

Port

♦ Configurable MII/RMII/GMII MAC Interface ♦ GFP/LAPS/HDLC/cHDLC Encapsulation ♦ IEEE 802.1Q VLAN and Q-in-Q Support ♦ Add/Drop OAM Frames from μP Interface ♦ Quality of Service (QoS) Support ♦ Traffic Policing Through CIR/CBS ♦ Classification Through PCP or DSCP ♦ Supports Up to 512Mb DDR SDRAM Buffer ♦ SPI™ and Parallel Microprocessor Interfaces ♦ 1.8V, 2.5V, 3.3V Supplies

Features continued in Section

_________________________ Functional Diagram

DS33M30/M31/M33

Framer A

SERDES A

Mapper

DS3/E3

High-Order

Framer B

SERDES B

SerDes B AND FRAMER B ON

DS33M31/33 ONLY

Framers

1 VC-4

3x VC-3

DS3 ADD/DROP (DS33M33 ONLY)

LCAS

VCAT /

GFP / HDLC / LAPS

Advanced OAM

Traffic Mgmt

Ethernet MAC

______________________________________________________________________________Ordering Information

PART

DS33M30N+

DS33M31N+*

DS33M33N+

+Denotes a lead-free/RoHS-compliant package. *Future product—contact factory for availability.

SUPPORTED EoS/EoPoS

MODES

EoS at VC-4 1 No 144 CSBGA

EoS at VC-4,

EoS at 3xVC-3,

EoPoS at 3xDS3

EoS at VC-4,

EoS at 3xVC-3,

EoPoS at 3xDS3

155Mbps PORTS EXT. DS3/E3 LINE PIN-PACKAGE

2 No 256 CSBGA

2 Yes (3) 256 CSBGA

SPI is a trademark of Motorola, Inc.

Maxim Integrated Products 1

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

. For pricing, delivery, and ordering information, please contact Maxim Direct at

___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET

1. GENERAL DESCRIPTION AND FEATURE HIGHLIGHTS.............................................................4

1.1 DEVICE FEATURE OVERVIEW ........................................................................................................... 5

1.2 TDM FEATURE OVERVIEW .............................................................................................................. 6

1.3 SONET/SDH..................................................................................................................................7

1.3.1 STS-3/STM-1 SerDes ............................................................................................................................ 7

1.3.2 STS-3/STM-1 Framer and Formatter..................................................................................................... 7

1.3.3 STS-3c/AU-4 Pointer Processing........................................................................................................... 8

1.3.4 STS-3c SPE/VC-4 Path Termination ..................................................................................................... 8

1.3.5 STS-3 Mux/Demux (DS33M31 and DS33M33 Only)............................................................................. 8

1.3.6 STS-1/AU-3/TU-3 Formatter and Framer (DS33M31 and DS33M33 Only) .......................................... 9

1.3.7 STS-1/AU-3/TU-3 Pointer Processing (DS33M31 and DS33M33 only)................................................ 9

1.3.8 STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only).......................................................... 10

1.4 PDH (DS33M31 AND DS33M33 ONLY) ........................................................................................ 12

1.4.1 Add/Drop DS3/E3 Framer/Formatter (DS33M31 and DS33M33 only)................................................ 12

1.4.2 DS3/E3 Ethernet Mapping (DS33M31 and DS33M33 only)................................................................ 13

1.4.3 Line DS3/E3 Framer/Formatter (DS33M33 only) ................................................................................ 13

1.4.4 Loopback.............................................................................................................................................. 14

1.5 VIRTUAL CONCATENATION (VCAT) (DS33M31 AND DS33M33 ONLY)............................................14

1.5.1 SONET/SDH VCAT/LCAS ................................................................................................................... 14

1.5.2 PDH VCAT/LCAS................................................................................................................................. 15

1.6 ENCAPSULATION ...........................................................................................................................15

1.6.1 GFP-F Encapsulation (per ITU-T G.7041)........................................................................................... 15

1.6.2 HDLC Encapsulation............................................................................................................................ 15

1.6.3 cHDLC Encapsulation.......................................................................................................................... 15

1.6.4 X.86 Encapsulation Support ................................................................................................................ 15

1.7 ETHERNET FEATURE OVERVIEW ....................................................................................................15

1.7.1 Ethernet MAC Interface........................................................................................................................ 16

1.7.2 Ethernet Bridging for 10/100 ................................................................................................................ 16

1.7.3 Ethernet Traffic Classification .............................................................................................................. 16

1.7.4 Ethernet Traffic Profiling and Policing.................................................................................................. 16

1.7.5 Ethernet Traffic Scheduling.................................................................................................................. 16

1.7.6 Ethernet Control Frame Processing..................................................................................................... 16

1.7.7 Q-in-Q .................................................................................................................................................. 16

1.8 SDRAM INTERFACE......................................................................................................................16

1.9 CLOCK RATE ADAPTER (CLAD).....................................................................................................16

1.10 SPI SERIAL MICROPROCESSOR FEATURES................................................................................. 17

1.11 PARALLEL MICROPROCESSOR INTERFACE (DS33M31 AND DS33M33 ONLY)..............................17

1.12 TEST AND DIAGNOSTICS.............................................................................................................17

2. STANDARDS COMPLIANCE ........................................................................................................18

3. APPLICATIONS ............................................................................................................................. 20

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___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET

List of Figures

Figure 1-1 TDM Functional Blocks .............................................................................................................................. 6

Figure 3-1. Example Application 1: EoS for DS33M30.............................................................................................. 20

Figure 3-2. Example Application 2: EoPoS for DS33M31 Interworking with EoP in DS33X162 Family of Devices .20 Figure 3-3. Example Application 3: EoPoS Transport for DS33M33 with Integrated Ethernet and PDH Services .. 20

List of Tables

Table 1-1. Product Selection Matrix............................................................................................................................. 5

Table 1-2. Summary of Mapping Functions................................................................................................................. 5

Table 2-1. Standards Compliance Summary............................................................................................................. 18

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___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET

1. General Description and Feature Highlights

The DS33M30 family of devices provides interconnection and mapping functionality between Ethernet and SONET/SDH networking elements. The product family includes three devices with differing features:

• DS33M30: One GMII mapped to STS-3c/VC-4 in a compact 10mm package.

• DS33M31: One GMII/MII mapped to a protected interface, with higher order EoS and EoPoS.

• DS33M33: One GMII/MII mapped to a protected interface, with higher order EoS, EoPoS and DS3/E3

add/drop mux.

All devices in the product family contain an Ethernet MAC port, one or two STS-3/STM-1 SerDes ports with the LVDS/LVPECL interface, one or three GFP-F/HDLC/cHDLC/X.86 (LAPS) protocol encapsulators, one or three higher order SONET/SDH mappers, a DDR SDRAM interface, and a local bus port for control/status. Ethernet traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) protocol to be transmitted onto the STS-3/ STM-1 interface. The family receives encapsulated Ethernet frames from the SerDes receiver interface and transmits the de-encapsulated frames onto the Ethernet port.

With the smallest footprint, the DS33M30 contains the smallest feature set in the product family. It performs EoS higher order mapping of Ethernet frames into a single STS-3c SPE or VC-4. The DS33M30 has one 1000Mbps (GbE) port with GMII interface. The DS33M30 supports Ethernet OAM insert/extract capability, QoS Priority Scheduling, VLAN processing, and committed information rate (CIR)-based policers for the delivery of carrier Ethernet services.

The DS33M31 and DS33M33 expand on the features of the DS33M30 with additional mapping capabilities. They support next-generation Ethernet over SONET/SDH in virtually concatenated higher order containers as well as Ethernet-over-PDH-over-SONET/SDH (EoPoS) at the DS3/E3 level. They have an Ethernet interface that can be configured as a 10/100Mbps MII/RMII port or a 1000Mbps (GbE) GMII port. They integrate four mapping/demapping functions:

• SONET/SDH mapping: STS-1/VC-3 to STS-3/STM-1; or TU-3 to VC-4 to STM-1

• PDH mapping: DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4);

• EoS higher order mapping: Ethernet to STS-1/VC-3 (or TU-3); and

• EoPoS mapping: Ethernet to DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4).

At the STS-3/STM-1 side, the DS33M31 and DS33M33 devices interface to an STS-3/STM-1 signal through dual serial-data buses operating at the rate of 155.52Mbps. This allows the implementation of a protected SONET/SDH at PHY layer. Each serializer/deserializer (SerDes) is supported with independent STS-3/STM-1 framer.

The DS33M33 supports all the features of the DS33M30 and DS33M31, with additional line interfaces for up to three add/drop DS3/E3 tributaries.

The SerDes interfaces, with LVDS/LVPECL, can be seamlessly connected to commercially available optical transceivers.

Microprocessor control can be accomplished through an 8/16-bit local bus or SPI bus. The family contains a 125MHz DDR SDRAM controller and interfaces to a 32-bit-wide 256Mb DDR SDRAM through a 16-bit data bus. The DDR SDRAM is used to buffer data through the Ethernet and STS-3/STM-1 ports.

The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.

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___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET

Table 1-1. Product Selection Matrix

PART

DS33M30

DS33M31

DS33M33

Note: The number of members for a VCG in the DS33M31 and DS33M33 can be 1, 2, or 3.

ETHERNET

PORT

1 GbE

1 (10/100,

GbE)

1 (10/100,

GbE)

STS-3/ STM-1

PORT

1 0 EoS NA Y 1 SPI

2 (1+1

protected)

2 (1+1

protected)

PDH

(DS3/E3)

PORT

0 EoS, EoPoS Y Y 3

3 EoS, EoPoS Y Y 3

ETHERNET

MAPPING

VLAN

FORWARDING

SUPPORT

PRIORITY

FORWARDING

SUPPORT

VCAT

GROUPS

(VCGS)

μP

CONTROL

SPI or

Parallel

SPI or

Parallel

PACKAGE

10mm, 144

CSBGA

17mm, 256

CSBGA

17mm, 256

CSBGA

1.1 Device Feature Overview

Note: See the glossary section (in the full data sheet) for the descriptions of terms used in this documentation, especially for the terms referring to the ports, blocks, and directions.

Table 1-2. Summary of Mapping Functions

1 Ethernet > STS-3c > STS-3 x x x — 2 Ethernet > AU-4 > STM-1 x x x — 3 Ethernet > STS-1 > STS-3 — x x — 4 Ethernet > AU-3 > STM-1 — x x — 5 Ethernet > TU-3 > AU-4 > STM-1 — x x — 6 Ethernet > DS3 > STS-1 > STS-3 — x x 7 Ethernet > DS3 > AU-3 > STM-1 — x x 8 Ethernet > DS3 > TU-3 > AU-4 > STM-1 — x x 9 Ethernet > E3 > STS-1 > STS-3 — x x 10 Ethernet > E3 > AU-3 > STM-1 — x x 11 Ethernet > E3 > TU-3 > AU-4 > STM-1 — x x 12 DS3 > STS-1 > STS-3 — — x — 13 DS3 > AU-3 > STM-1 — — x — 14 DS3 > TU-3 > AU-4 > STM-1 — — x — 15 E3 > STS-1 > STS-3 — — x — 16 E3 > AU-3 > STM-1 — — x — 17 E3 > TU-3 > AU-4 > STM-1 — — x —

The DS33M30 family of devices offer the following features:

MAPPING FUNCTIONS “>” DS33M30 DS33M31 DS33M33 NOTES

Without

external DS3

port

Without

external E3

port

• Supports the mapping protocols as listed in

Table 1-2.

• Supports single 10/100/1000Mbps Ethernet interface

• STS-3/STM-1 interface operating at 155.52Mbps

• Supports two transmit timing modes for STS-3/STM-1 port(s):

• Loop timing (transmit timing reference = receive timing)

• Local timing (transmit timing reference = CLAD timing)

• Supports three transmit timing modes for Line DS3/E3 ports: (DS33M33)

• Loop timed (transmit timing reference = receive timing)

• Line timed (or thru timed) (transmit timing reference = Drop DS3/E3 thru timing)

• Local timed (transmit timing reference = CLAD timing)

• Certain clock, data, and control signals can be inverted to allow a glueless interface to other devices

• Certain port can be put into a low-power standby mode when not being used

Rev: 111908 5 of 20

___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET

• Manual or automatic one-second update of performance monitoring counters

• Single reference clock for all data rates using internal clock rate adapter (CLAD)

• Detection of loss of transmit clock and loss of receive clock

• Supports two packages:

• 10mm, 144-pin CSBGA Package (DS33M30)

• 17mm, 256-pin CSBGA Package (DS33M31/DS33M33)

• 1.8V, 2.5V, 3.3V supplies

• IEEE 1149.1 JTAG boundary scan

• Software access to device ID and silicon revision

• Development support includes evaluation kit, driver source code, and reference designs

1.2 TDM Feature Overview

Figure 1-1 describes the TDM side feature.

Figure 1-1. TDM Functional Blocks

SERDES

STS-3/STM-1

Side

STS-3 Section/Line Termination

M U

STS-3 Path

Termination

(VC-4)

M U X

STS-1 Path Termination

(VC-3)

M U X

EoS (VC-4/STS-3c)

DS3/E3

MAPPER

EoS (VC-3/STS-1)

DS3/E3 Desync

Add/Drop

DS3/E3 Framer

M U X

Add Direction

line coder

Drop Direction

Encapsulated

Ethernet

EoPoS

Line DS3/E3 Framer

B3ZS/ HDB3

Line DS3/E3 side

• Supports M23 DS3, C-bit DS3, G.751 E3, and G.832 E3 facilities

• Mapping/demapping of three DS3/E3 tributaries to/from STS-3/STM-1 through STS-1 or AU-3 or TU-3/AU-4

• Fully integrated and compliant DS3/E3 mapper/demapper and synchronizers/desynchronizers per

Telcordia, ANSI, and ITU standards

• High speed DS3/E3/STS-1/STS-3 overhead insertion/extraction with full access to all overhead bytes

• Full-featured DS3/E3/STS-1/STS-3 defect and performance monitoring (PM) support Large PM counters

for accumulation intervals up to one second

• Loopback capabilities at both STS-3/STM-1 side and line DS3/E3 side

• Dual STS-3/STM-1 155.52Mbps serial interfaces with receive clock recovery and transmit clock synthesis

• From a single reference clock the CLAD (cLock rate adapter) generates clock references for DS3

(44.736MHz), E3 (34.368MHz), and/or STS-3/STM-1 reference (77.76/19.44MHz)

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+ 14 hidden pages

Rainbow Electronics DS33M33 User Manual

Table of Contents

List of Figures

List of Tables

1. General Description and Feature Highlights

1.1 Device Feature Overview

1.2 TDM Feature Overview