Rainbow Electronics DS3184 User Manual
PRODUCT BRIEF
Y
Maxim/Dallas Semiconductor Confidential
PRODUCT PREVIEW
DS3181,2,3,4 Multi-Port ATM/Packet PHYs
For DS3/E3 with Built-In LIUs
FEATURES
• Quad (DS3184), triple (DS3183), dual (DS3182) or single (DS3181) with integrated LIU ATM / Packet PHYs for DS3 and E3
• Each port independently configurable
• Performs receive clock/data recovery and
transmit wave shaping
• Jitter attenuators can be placed either in the receive or transmit paths
• Interfaces to 75Ω coaxial cable at lengths up
to 380 meters or 1246 feet (DS3) or 440
meters or 1443 feet (E3)
• Uses 1:2 transformers on both Tx and Rx
• Requires minimal external components
• Universal PHYs map ATM cells and/or
HDLC packets into DS3 or E3 data streams
• UTOPIA 2 or 3 or POS-PHY 2 or 3 interface with 8, 16, or 32 bit bus width up to 66 MHz
• Ports independently configurable for cell or packet traffic in POS-PHY bus modes
• Direct, PLCP and clear-channel cell mapping
• Direct and clear-channel packet mapping
• On-chip DS3 (M23 or C-bit) and E3 (G.751
or G.832) framers
• Ports independently configurable for DS3, E3 or arbitrary framing protocol up to 52 Mbps
• Programmable (externally controlled or internally hardware based engine) subrate DS3/E3 circuitry
• Full featured DS3/E3/PLCP alarms
• Built-in HDLC controllers with 256 byte
FIFOs for DS3 PMDL, G.751 Sn bit or G.832
NR/GC bytes
www.maxim-ic.com/telecom
PRODUCT BRIEF
PRODUCT BRIEF
PRELIMINAR
• On-chip BERTs for PRBS and repetitive pattern generation, detection and analysis
• Large performance-monitoring counters for accumulation intervals up to 1 second
• Flexible overhead insertion/extraction ports for DS3, E3 and PLCP framers
• Loopback include line, diagnostic, framer payload and system interface
• Ports can be disabled to reduce power
• Integrates clock rate adapter to generate the
required 44.736 MHz for DS3, 34.368 MHz
for E3, and/or 52 MHz for arbitrary framing
protocol up to 52 Mbps
• 8/16-bit generic microprocessor interface
• Low power 3.3V operation (5V tolerant I/O)
• Small high-density Thermally Enhanced (TE)
Chip Scale BGA packaging
• Industrial temperature range: -40 to +85°C
• IEEE 1149.1 JTAG test port
Note: This Product Preview contains preliminary information and is subject to change without notice.
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm
Rev 1.5 1 of 13 022304
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Maxim/Dallas Semiconductor Confidential
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PRODUCT PREVIEW
DS3181,2,3,4 Multi-Port ATM/Packet PHYs
For DS3/E3 with Built-In LIUs
FUNCTIONAL DIAGRAM
Line
Interface
TXPn/TXNn
RXPn/RXNn
Ports[1:n]
To T3/E3
Transformers
DS3/E3
Overhead
Ports[1:n]
Frame
Interface
Ports[1:n]
PLCP
Overhead
Ports[1:n]
DS318x
Microprocessor
Interface
System
Interface
UTOPIA or
POS-PHY
bus
to ATM or
Link layer
ORDERING INFORMATION
Commercial Temperature Range (0°C to 70°C)
DS3181 Single 400-lead TE-CSBGA
DS3182 Dual 400-lead TE-CSBGA
DS3183 Triple 400-lead TE-CSBGA
DS3184 Quad 400-lead TE-CSBGA
Industrial Temperature Range (-40°C to 85°C)
DS3181N Single 400-lead TE-CSBGA
DS3182N Dual 400-lead TE-CSBGA
DS3183N Triple 400-lead TE-CSBGA
DS3184N Quad 400-lead TE-CSBGA
www.maxim-ic.com/telecom
Note: This Product Preview contains preliminary information and is subject to change without notice.
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm
Rev 1.5 2 of 13 022304
.
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4
Ω
Ω
DESCRIPTION
The DS3184 (quad), DS3183 (triple), DS3182 (dual), and DS3181 (single) PHYs perform all of the
functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3/E3 data
streams on T3 or E3 physical copper lines. Each line interface unit (LIU) has independent receive and
transmit paths. The Receive LIU block performs clock and data recovery from a B3ZS- or HDB3-coded
AMI signal and monitors for loss of the incoming signal. The Receive Framer block optionally performs
B3ZS/HDB3 decoding. The Transmit Formatter optionally performs B3ZS/HDB3 encoding, and drives
standard pulse-shape waveforms onto 75-ohm coaxial cable. Dedicated cell processor and packet
processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets
upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23
DS3, C-bit DS3, G.751 E3 or G.832 E3 data streams. PLCP framers provide legacy ATM transmissionconvergence support. With integrated hardware support for both cells and packets, the DS3184/3/2/1
PHYs enable high-density universal line cards for unchannelized DS3/E3 from T3/E3 copper lines to
ATM/Packet system switch interface. The DS318x ATM/Packet PHYs with embedded LIU conform to
the telecommunications standards listed in section 4.
1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at each LIU interface for proper operation. Figure 1-2 shows the functional block diagram of one channel ATM / Packet PHY.
Figure 1-1 LIU External Connections
Transmit
0.05uF
Receive
1:2ct
0.05uF
1:2ct
Each T3/E3 LIU Interface
330
(1%)
330
(1%)
TXP
TXN
RXP
RXN
VDD
VDD
VDD
VSS
VSS
VSS
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
1uF
3.3V
Power
1uF
Plane
1uF
Ground
Plane
Rev 1.5 3 of 13 022304
Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4
]
]
A
]
]
A
k
]
]
A
]
]
K
K
[
]
[
]
Figure 1-2 Functional Block Diagram
/ TGCLKn
TDENn
TDATn
TLCLKn
Trail
Trace
Buffer
TSOFn / TIOHMn
TPOHn
TPOHGCLK
Tx
PLCP/FRAC
Formatter
Loopback
Framer Payload
Rx
PLCP/FRAC
Framer
TPOHSOFn
8KREFI
BERT
Tx Cell
Processor
Tx Packet
Processor
Rx Packet
Processor
Rx Cell
Processor
Microprocessor
Interface
System Interface
Loopback
Tx
FIFO
Rx
FIFO
System
Interface
TSCLK
TADR[4:0
TDATA[31:0
TPRTY*
TEN*
TPX
TDXA[4:1
TSOX
TSP
TEOP
TSX
TMOD[1:0
TERR
RSCLK
RADR[4:0
RDATA[31:0
RPRTY*
REN*
RPX
RDXA[4:1
RSOX
REOP
RSX
RVAL
RMOD[1:0
RERR
TDMn
RXPn
RXNn
TXPn
TXNn
DS3/E3
Transmit
LIU
Loopback
LLine Terminal
DS3/E3
Receive
LIU
Clock Rate
Adapter
Loopback
Framer Diagnostic
Line Facility Loopbac
IEEE P1149.1
JTAG Test
Access Port
TMEI
B3ZS/
HDB3
Encoder
HDLC
B3ZS/
HDB3
Decoder
TOHn
TOHGCLKn
TOHSOFn
DS3 / E3
Transmit
Formatter
FEAC
DS3 / E3
Receive
Framer
CLKACLKB
REFCL
JTDI
JTMS
JTDO
JTCL
JTRST*
RECU
ROHn
RDATn
RSOFn
ROHSOFn
ROHGCLKn
RLCLKn
RDENn / RGCLKn
RPOHn
8KREFO
RPOHSOFn
RPOHGCLKn
9:0
CS*
ALE
15:0
A
D
INT*
MOT
RST*
PIOAn
RD*/DS*
WR*/ R/W*
PIOBn
n = port #
2 APPLICATIONS
• Access Concentrators
• Multi-Service Access Platforms
• ATM and Frame Relay Equipment
• Routers and Switches
• SONET/SDH ADM
• SONET/SDH Muxes
• PBXs
• Digital Cross Connect
• PDH Multiplexer/Demultiplexer
• Test Equipment
The following figures, Figure 2-1 and Figure 2-2, show applications for DS3184 as four port unchannelized ATM and packet T3/E3 line cards, respectively.
Rev 1.5 4 of 13 022304
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