Rainbow Electronics DS3170 User Manual
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www.maxim-ic.com
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceive
GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS
Access Concentrators
Routers and Switches
SONET/SDH ADM
SONET/SDH Muxes
PBXs Test Equipment
Demultiplexer
Multiservice Access
Platforms (MSAPs)
Multiservice Protocol
Platform (MSPPs)
Digital Cross Connect PDH Multiplexer/
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3170 0°C to +70°C
DS3170L 0°C to +70°C
DS3170N -40°C to +85°C
DS3170LN -40°C to +85°C
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
FUNCTIONAL DIAGRAM
DS3/E3 LINE
DS3/
E3
LIU
DS3170
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES
§ Single-Chip Transceiver for DS3 and E3
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
§ Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
§ On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
§ Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
§ Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
§ Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
§ CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
§ Software Compatible with DS3171–DS3174 SCT
Product Family
§ 8-/16-Bit Parallel and Slave SPI Serial (≤10Mbps)
Microprocessor Interface
§ Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
§ 100-Pin Small 11mm (1mm) CSBGA and 14mm
(1.4mm) LQFP Package Options
§ Industrial Temperature Operation: -40°C to +85°C
§ IEEE1149.1 JTAG Test Port
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 101404
.
DS3170 DS3/E3 Single-Chip Transceiver
DETAILED DESCRIPTION
The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has
independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and
data input. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard
pulse-shape waveforms onto 75W coaxial cable and can be bypassed for direct clock and data output. The jitter
attenuator can be put in the transmit or receive data path when the LIU is enabled. Built-in DS3/E3 framers transmit
and receive data in properly formatted C-bit DS3, M23 DS3, G.751 E3 or G.832 E3 data streams. Functions not
used are powered down to reduce system power requirements. The DS3170 conforms to the telecommunications
standards listed in Section 3.2
.
1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at the LIU interface for proper operation. Figure 1-2 shows the
functional block diagram of the one channel DS3/E3 SCT.
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170
Transmit
DS3/E3 LIU Interface
TXP
W
330
(1%)
VDD
VDD
0.01uF
0.01uF
0.1uF
0.1uF
1uF
1uF
3.3V
Power
Plane
TXN
1:2ct
VDD
0.01uF
0.1uF
1uF
Receive
1:2ct
330
(1%)
RXP
W
RXN
VSS
VSS
VSS
Ground
Plane
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Figure 1-2. Block Diagram
DS3170 DS3/E3 Single-Chip Transceiver
TOHCLK
TOH
TOHSOF
TOHEN
TPOS/TDAT
TNEG
TLCLK
TXP
TXN
RPOS/RDAT
RNEG/RCLV
RLCLK
RXP
RXN
DS3170
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
SPI
RST
REFCLK
Serial Interface Mode:
SPI (SCLK, MOSI, and MISO)
D[15:0]
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
ALE
TUA1
Serial or Parallel
uP Inteface
CS
A[8:1]
A[0]/BSWAP
TAIS
DLB
RD/DS
TCLKO/TGCLK
TSOFO/TDEN
DS3 / E3
Transmit
Formatter
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
Buffer
PLB
DS3 / E3
Receive
Framer
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
ROH
ROHCLK
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO/RGCLK
RSOFO/RDEN
JTDO
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DS3170 DS3/E3 Single-Chip Transceiver
TABLE OF CONTENTS
1 BLOCK DIAGRAMS 2
2 APPLICATIONS 12
3 FEATURE DETAILS 13
3.1 GLOBAL FEATURES........................................................................................................................................ 13
3.2 RECEIVE DS3/E3 LIU FEATURES .................................................................................................................. 13
3.3 JITTER ATTENUATOR FEATURES..................................................................................................................... 13
3.4 RECEIVE DS3/E3 FRAMER FEATURES ........................................................................................................... 13
3.5 TRANSMIT DS3/E3 FORMATTER FEATURES .................................................................................................... 14
3.6 TRANSMIT DS3/E3 LIU FEATURES................................................................................................................. 14
3.7 CLOCK RATE ADAPTER FEATURES ................................................................................................................. 14
3.8 HDLC CONTROLLER FEATURES..................................................................................................................... 14
3.9 FEAC CONTROLLER FEATURES ..................................................................................................................... 14
3.10 TRAIL TRACE BUFFER FEATURES ................................................................................................................... 15
3.11 BIT ERROR-RATE TESTER (BERT) FEATURES ................................................................................................ 15
3.12 LOOPBACK FEATURES ................................................................................................................................... 15
3.13 MICROPROCESSOR INTERFACE FEATURES ..................................................................................................... 15
3.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ................................................................................ 15
3.15 TEST FEATURES............................................................................................................................................ 15
4 STANDARDS COMPLIANCE 16
5 ACRONYMS AND GLOSSARY 17
6 MAJOR OPERATIONAL MODES 18
6.1 DS3/E3 FRAMED LIU MODE.......................................................................................................................... 18
6.2 DS3/E3 UNFRAMED LIU MODE ..................................................................................................................... 20
6.3 DS3/E3 FRAMED POS/NEG MODE............................................................................................................... 21
6.4 DS3/E3 UNFRAMED POS/NEG MODE .......................................................................................................... 22
6.5 DS3/E3 FRAMED UNI MODE ......................................................................................................................... 23
6.6 DS3/E3 UNFRAMED UNI MODE..................................................................................................................... 24
7 PIN DESCRIPTIONS 25
7.1 SHORT PIN DESCRIPTIONS............................................................................................................................. 25
7.2 DETAILED PIN DESCRIPTIONS......................................................................................................................... 27
7.3 PIN FUNCTIONAL TIMING ................................................................................................................................37
7.3.1 Line IO.................................................................................................................................................. 37
7.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 40
7.3.3 DS3/E3 Serial Data Interface ............................................................................................................... 41
7.3.4 Microprocessor Interface Functional Timing ........................................................................................ 43
7.3.5 JTAG Functional Timing....................................................................................................................... 50
8 INITIALIZATION AND CONFIGURATION 51
8.1 MONITORING AND DEBUGGING ....................................................................................................................... 52
9 FUNCTIONAL DESCRIPTION 53
9.1 PROCESSOR BUS INTERFACE ......................................................................................................................... 53
9.1.1 SPI Serial Port Mode............................................................................................................................ 53
9.1.2 8/16 Bit Bus Widths.............................................................................................................................. 53
9.1.3 Ready Signal (
9.1.4 Byte Swap Modes ................................................................................................................................ 53
9.1.5 Read-Write/Data Strobe Modes ........................................................................................................... 53
9.1.6 Clear on Read/Clear on Write Modes .................................................................................................. 53
9.1.7 Interrupt and Pin Modes....................................................................................................................... 54
9.1.8 Interrupt Structure ................................................................................................................................ 54
9.2 CLOCKS ........................................................................................................................................................ 55
9.2.1 Line Clock Modes................................................................................................................................. 55
9.2.2 Sources of Clock Output Pin Signals ................................................................................................... 57
9.2.3 Line IO Pin Timing Source Selection ................................................................................................... 59
9.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 62
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RDY
) ............................................................................................................................. 53
DS3170 DS3/E3 Single-Chip Transceiver
9.2.5
Gapped Clocks..................................................................................................................................... 63
9.3 RESET AND POWER-DOWN ............................................................................................................................ 63
9.4 GLOBAL RESOURCES..................................................................................................................................... 66
9.4.1 Clock Rate Adapter (CLAD)................................................................................................................. 66
9.4.2 8 kHz Reference Generation ............................................................................................................... 66
9.4.3 One Second Reference Generation..................................................................................................... 67
9.4.4 General-Purpose IO Pins ..................................................................................................................... 68
9.4.5 Performance Monitor Counter Update Details ..................................................................................... 69
9.4.6 Transmit Manual Error Insertion .......................................................................................................... 70
9.5 PORT RESOURCES ........................................................................................................................................71
9.5.1 Loopbacks ............................................................................................................................................ 71
9.5.2 Loss Of Signal Propagation ................................................................................................................. 73
9.5.3 AIS Logic .............................................................................................................................................. 73
9.5.4 Loop Timing Mode ............................................................................................................................... 75
9.5.5 HDLC Overhead Controller .................................................................................................................. 75
9.5.6 Trail Trace ............................................................................................................................................ 75
9.5.7 BERT.................................................................................................................................................... 75
9.5.8 System Port Pins.................................................................................................................................. 76
9.5.9 Framing Modes .................................................................................................................................... 77
9.5.10 Line Interface Modes............................................................................................................................ 77
9.6 DS3/E3 FRAMER / FORMATTER ..................................................................................................................... 79
9.6.1 General Description ............................................................................................................................. 79
9.6.2 Features ............................................................................................................................................... 79
9.6.3 Transmit Formatter............................................................................................................................... 80
9.6.4 Receive Framer.................................................................................................................................... 80
9.6.5 C-bit DS3 Framer/Formatter ................................................................................................................ 84
9.6.6 M23 DS3 Framer/Formatter ................................................................................................................. 87
9.6.7 G.751 E3 Framer/Formatter................................................................................................................. 89
9.6.8 G.832 E3 Framer/Formatter................................................................................................................. 91
9.7 HDLC OVERHEAD CONTROLLER.................................................................................................................... 96
9.7.1 General Description ............................................................................................................................. 96
9.7.2 Features ............................................................................................................................................... 97
9.7.3 Transmit FIFO ...................................................................................................................................... 97
9.7.4 Transmit HDLC Overhead Processor .................................................................................................. 98
9.7.5 Receive HDLC Overhead Processor ................................................................................................... 98
9.7.6 Receive FIFO ....................................................................................................................................... 99
9.8 TRAIL TRACE CONTROLLER............................................................................................................................ 99
9.8.1 General Description ............................................................................................................................. 99
9.8.2 Features ............................................................................................................................................. 100
9.8.3 Functional Description........................................................................................................................ 100
9.8.4 Transmit Data Storage ....................................................................................................................... 101
9.8.5 Transmit Trace ID Processor ............................................................................................................. 101
9.8.6 Transmit Trail Trace Processing ........................................................................................................ 101
9.8.7 Receive Trace ID Processor .............................................................................................................. 101
9.8.8 Receive Trail Trace Processing ......................................................................................................... 101
9.8.9 Receive Data Storage ........................................................................................................................ 102
9.9 FEAC CONTROLLER ................................................................................................................................... 102
9.9.1 General Description ........................................................................................................................... 102
9.9.2 Features ............................................................................................................................................. 103
9.9.3 Functional Description........................................................................................................................ 103
9.10 LINE ENCODER/DECODER............................................................................................................................ 104
9.10.1 General Description ........................................................................................................................... 104
9.10.2 Features............................................................................................................................................. 105
9.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 105
9.10.4 Transmit Line Interface ...................................................................................................................... 105
9.10.5 Receive Line Interface ....................................................................................................................... 106
9.10.6 B3ZS/HDB3 Decoder......................................................................................................................... 106
9.11 BERT......................................................................................................................................................... 108
9.11.1 General Description ........................................................................................................................... 108
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DS3170 DS3/E3 Single-Chip Transceiver
9.11.2
Features ............................................................................................................................................. 108
9.11.3 Configuration and Monitoring ............................................................................................................. 108
9.11.4 Receive Pattern Detection ................................................................................................................. 109
9.11.5 Transmit Pattern Generation.............................................................................................................. 111
9.12 LIU – LINE INTERFACE UNIT ........................................................................................................................ 112
9.12.1 General Description ........................................................................................................................... 112
9.12.2 Features ............................................................................................................................................. 112
9.12.3 Detailed Description ........................................................................................................................... 112
9.12.4 Transmitter ......................................................................................................................................... 113
9.12.5 Receiver ............................................................................................................................................. 114
10 OVERALL REGISTER MAP 117
11 REGISTER MAPS AND DESCRIPTIONS 119
11.1 REGISTERS BIT MAPS.................................................................................................................................. 119
11.1.1 Global Register Bit Map ..................................................................................................................... 119
11.1.2 HDLC Register Bit Map...................................................................................................................... 121
11.1.3 T3 Register Bit Map ........................................................................................................................... 123
11.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
11.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
11.2 GLOBAL REGISTERS ....................................................................................................................................126
11.2.1 Register Bit Descriptions.................................................................................................................... 126
11.3 PORT REGISTER.......................................................................................................................................... 133
11.3.1 Register Bit Descriptions.................................................................................................................... 133
11.4 BERT......................................................................................................................................................... 144
11.4.1 BERT Register Map ........................................................................................................................... 144
11.4.2 BERT Register Bit Descriptions ......................................................................................................... 144
11.5 B3ZS/HDB3 LINE ENCODER/DECODER ....................................................................................................... 151
11.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 151
11.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 152
11.6 HDLC......................................................................................................................................................... 156
11.6.1 HDLC Transmit Side Register Map.................................................................................................... 156
11.6.2 HDLC Receive Side Register Map..................................................................................................... 159
11.7 FEAC CONTROLLER ................................................................................................................................... 163
11.7.1 FEAC Transmit Side Register Map.................................................................................................... 163
11.7.2 FEAC Receive Side Register Map ..................................................................................................... 165
11.8 TRAIL TRACE............................................................................................................................................... 168
11.8.1 Trail Trace Transmit Side ................................................................................................................... 168
11.8.2 Trail Trace Receive Side Register Map ............................................................................................. 169
11.9 DS3/E3 FRAMER......................................................................................................................................... 174
11.9.1 Transmit DS3 ..................................................................................................................................... 174
11.9.2 Receive DS3 Register Map................................................................................................................ 176
11.9.3 Transmit G.751 E3 ............................................................................................................................. 183
11.9.4 Receive G.751 E3 Register Map ....................................................................................................... 186
11.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 191
11.9.6 Receive G.832 E3 Register Map ....................................................................................................... 194
12 JTAG INFORMATION 202
12.1 JTAG DESCRIPTION .................................................................................................................................... 202
12.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................. 203
12.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................................... 205
12.4 JTAG ID CODES......................................................................................................................................... 206
12.5 JTAG FUNCTIONAL TIMING.......................................................................................................................... 207
12.6 IO PINS ...................................................................................................................................................... 207
13 PIN CONFIGURATIONS 208
14 PACKAGE INFORMATION 213
15 PACKAGE THERMAL INFORMATION 215
16 DC ELECTRICAL CHARACTERISTICS 216
17 AC TIMING CHARACTERISTICS 218
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DS3170 DS3/E3 Single-Chip Transceiver
17.1
FRAMER DATA PATH AC CHARACTERISTICS ................................................................................................. 220
17.2 OVERHEAD PORT AC CHARACTERISTICS...................................................................................................... 221
17.3 MICRO INTERFACE AC CHARACTERISTICS .................................................................................................... 222
17.3.1 SPI Bus Mode ....................................................................................................................................222
17.3.2 Parallel Bus Mode .............................................................................................................................. 224
17.4 CLAD JITTER CHARACTERISTICS ................................................................................................................. 227
17.5 LIU INTERFACE AC CHARACTERISTICS ........................................................................................................ 227
17.5.1 Waveform Templates ......................................................................................................................... 227
17.5.2 LIU Input/Output Characteristics ........................................................................................................ 230
17.6 JTAG INTERFACE AC CHARACTERISTICS..................................................................................................... 232
18 REVISION HISTORY 233
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DS3170 DS3/E3 Single-Chip Transceiver
LIST OF FIGURES
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170 ....................................................................... 2
Figure 1-2. Block Diagram ........................................................................................................................................... 3
Figure 2-1. DS3/E3 Line Card ................................................................................................................................... 12
Figure 6-1. DS3/E3 Framed LIU Mode ...................................................................................................................... 19
Figure 6-2. DS3/E3 Unframed LIU Mode .................................................................................................................. 20
Figure 6-3. DS3/E3 Framed POS/NEG Mode ........................................................................................................... 21
Figure 6-4. DS3/E3 Unframed POS/NEG Mode........................................................................................................ 22
Figure 6-5. DS3/E3 Framed UNI Mode ..................................................................................................................... 23
Figure 6-6. DS3/E3 Unframed UNI Mode .................................................................................................................. 24
Figure 7-1. Tx Line IO B3ZS Functional Timing Diagram.......................................................................................... 37
Figure 7-2. Tx Line IO HDB3 Functional Timing Diagram ......................................................................................... 38
Figure 7-3. Rx Line IO B3ZS Functional Timing Diagram ......................................................................................... 38
Figure 7-4. Rx Line IO HDB3 Functional Timing Diagram......................................................................................... 39
Figure 7-5. Tx Line IO UNI Functional Timing Diagram ............................................................................................ 39
Figure 7-6. Rx Line IO UNI Functional Timing Diagram ............................................................................................ 40
Figure 7-7. DS3 Framing Receive Overhead Port Timing......................................................................................... 40
Figure 7-8. E3 G.751 Framing Receive Overhead Port Timing ................................................................................ 40
Figure 7-9. E3 G.832 Framing Receive Overhead Port Timing ................................................................................ 40
Figure 7-10. DS3 Framing Transmit Overhead Port Timing...................................................................................... 41
Figure 7-11. E3 G.751 Framing Transmit Overhead Port Timing ............................................................................. 41
Figure 7-12. E3 G.832 Framing Transmit Overhead Port Timing ............................................................................. 41
Figure 7-13. DS3 Framed Mode Transmit Serial Interface Pin Timing ..................................................................... 42
Figure 7-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing ............................................................. 42
Figure 7-15. E3 G.832 Framed Mode Transmit Serial Interface Pin Timing ............................................................. 42
Figure 7-16. DS3 Framed Mode Receive Serial Interface Pin Timing ...................................................................... 43
Figure 7-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing .............................................................. 43
Figure 7-18. E3 G.832 Framed Mode Receive Serial Interface Pin Timing .............................................................. 43
Figure 7-19. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0 .............................................. 44
Figure 7-20. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................ 44
Figure 7-21. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................ 44
Figure 7-22. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................ 44
Figure 7-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................ 45
Figure 7-24. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................ 45
Figure 7-25. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................ 45
Figure 7-26. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................ 45
Figure 7-27. 16-Bit Mode Write.................................................................................................................................. 46
Figure 7-28. 16-Bit Mode Read ................................................................................................................................. 46
Figure 7-29. 8-Bit Mode Write.................................................................................................................................... 47
Figure 7-30. 8-Bit Mode Read ................................................................................................................................... 47
Figure 7-31. 16-Bit Mode without Byte Swap ............................................................................................................ 48
Figure 7-32b 16-Bit Mode with Byte Swap ................................................................................................................ 48
Figure 7-33. Clear Status Latched Register on Read................................................................................................ 49
Figure 7-34. Clear Status Latched Register on Write................................................................................................ 49
Figure 7-35. RDY Signal Functional Timing Write ..................................................................................................... 50
Figure 7-36. RDY Signal Functional Timing Read ..................................................................................................... 50
Figure 9-1. Interrupt Structure ................................................................................................................................... 55
Figure 9-2. Internal Tx Clock ..................................................................................................................................... 58
Figure 9-3. Internal Rx Clock ..................................................................................................................................... 59
Figure 9-4. Example IO Pin Clock Muxing................................................................................................................. 63
Figure 9-5. Reset Sources......................................................................................................................................... 64
Figure 9-6. 8KREF Logic ........................................................................................................................................... 67
Figure 9-7. Performance Monitor Update Logic ........................................................................................................ 70
Figure 9-8. Transmit Error Insert Logic...................................................................................................................... 71
Figure 9-9. Loopback Modes ..................................................................................................................................... 72
Figure 9-10. ALB Mux ................................................................................................................................................ 72
Figure 9-11. AIS Signal Flow ..................................................................................................................................... 74
Figure 9-12. Framer Detailed Block Diagram ............................................................................................................ 79
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DS3170 DS3/E3 Single-Chip Transceiver
Figure 9-13. DS3 Frame Format................................................................................................................................ 81
Figure 9-14. DS3 Subframe Framer State Diagram .................................................................................................. 81
Figure 9-15. DS3 Multiframe Framer State Diagram................................................................................................. 82
Figure 9-16. G.751 E3 Frame Format ....................................................................................................................... 89
Figure 9-17. G.832 E3 Frame Format ....................................................................................................................... 92
Figure 9-18. MA Byte Format .................................................................................................................................... 92
Figure 9-19. HDLC Controller Block Diagram ........................................................................................................... 97
Figure 9-20. Trail Trace Controller Block Diagram .................................................................................................. 100
Figure 9-21. Trail Trace Byte (DT = Trail Trace Data)............................................................................................. 102
Figure 9-22. FEAC Controller Block Diagram.......................................................................................................... 103
Figure 9-23. FEAC Codeword Format.................................................................................................................... 104
Figure 9-24. Line Encoder/Decoder Block Diagram ................................................................................................ 105
Figure 9-25. B3ZS Signatures ................................................................................................................................. 107
Figure 9-26. HDB3 Signatures................................................................................................................................. 107
Figure 9-27. BERT Block Diagram .......................................................................................................................... 108
Figure 9-28. PRBS Synchronization State Diagram ................................................................................................ 110
Figure 9-29. Repetitive Pattern Synchronization State Diagram ............................................................................. 111
Figure 9-30. LIU Functional Diagram....................................................................................................................... 112
Figure 9-31. DS3/E3 LIU Block Diagram ................................................................................................................. 113
Figure 9-32. Receiver Jitter Tolerance .................................................................................................................... 116
Figure 12-1. JTAG Block Diagram........................................................................................................................... 202
Figure 12-2. JTAG TAP Controller State Machine .................................................................................................. 203
Figure 12-3. JTAG Functional Timing...................................................................................................................... 207
Figure 13-1. DS3170 Pin Assignments—100-Ball CSBGA (Top View) .................................................................. 212
Figure 13-2. DS3170 Pin Assignments—100-Pin LQFP ......................................................................................... 212
Figure 14-1. Mechanical Dimensions—100-Ball CSBGA........................................................................................ 213
Figure 14-2. Mechanical Dimensions—100-Pin LQFP ............................................................................................ 214
Figure 17-1. Clock Period and Duty Cycle Definitions............................................................................................. 218
Figure 17-2. Rise Time, Fall Time, and Jitter Definitions ........................................................................................ 218
Figure 17-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 218
Figure 17-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 219
Figure 17-5. To/From Hi Z Delay Definitions (Rising Clock Edge) .......................................................................... 219
Figure 17-6. To/From Hi Z Delay Definitions (Falling Clock Edge) ......................................................................... 219
Figure 17-7. SPI Interface Timing Diagram ............................................................................................................. 223
Figure 17-8. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 225
Figure 17-9. Micro Interface Multiplexed Read Cycle.............................................................................................. 226
Figure 17-10. DS3 Pulse Mask Template................................................................................................................ 228
Figure 17-11 E3 Waveform Template...................................................................................................................... 229
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DS3170 DS3/E3 Single-Chip Transceiver
LIST OF TABLES
Table 4-1. Standards Compliance ............................................................................................................................. 16
Table 7-1. DS3170 Short Pin Descriptions ................................................................................................................ 25
Table 7-2. Detailed Pin Descriptions ......................................................................................................................... 27
Table 8-1. Configuration of Port Register Settings .................................................................................................... 52
Table 9-1. LIU Enable Table ...................................................................................................................................... 57
Table 9-2. All Possible Clock Sources Based on Mode and Loopback..................................................................... 57
Table 9-3. Source Selection of TLCLK Clock Signal ................................................................................................. 58
Table 9-4. Source Selection of TCLKO (Internal Tx Clock)....................................................................................... 59
Table 9-5. Source Selection of RCLKO Clock Signal (Internal Rx Clock)................................................................. 59
Table 9-6. Transmit Line Interface Signal Pin Valid Timing Source Select ............................................................... 60
Table 9-7. Transmit Framer Pin Signal Timing Source Select .................................................................................. 61
Table 9-8. Receive Line Interface Pin Signal Timing Source Select ......................................................................... 61
Table 9-9. Receive Framer Pin Signal Timing Source Select ................................................................................... 62
Table 9-10. Reset and Power-Down Sources ........................................................................................................... 65
Table 9-11. CLAD Clock Source Settings ................................................................................................................. 66
Table 9-12. Global 8 kHz Reference Source Table ................................................................................................... 67
Table 9-13. Port 8 kHz Reference Source Table....................................................................................................... 67
Table 9-14. GPIO Global Signals .............................................................................................................................. 68
Table 9-15. GPIO Pin Global Mode Select Bits......................................................................................................... 68
Table 9-16. GPIO Port Alarm Monitor Select ............................................................................................................ 69
Table 9-17. Loopback Mode Selections .................................................................................................................... 71
Table 9-18. Line AIS Enable Modes .......................................................................................................................... 75
Table 9-19. Payload (Downstream) AIS Enable Modes ............................................................................................ 75
Table 9-20. TSOFI Input Pin Functions ..................................................................................................................... 76
Table 9-21. TSOFO/TDEN/Output Pin Functions...................................................................................................... 76
Table 9-22 TCLKO/TGCLK Output Pin Functions ..................................................................................................... 76
Table 9-23. RSOFO/RDEN Output Pin Functions ..................................................................................................... 77
Table 9-24. RCLKO/RGCLK Output Pin Functions ................................................................................................... 77
Table 9-25. Framing Mode Select Bits FM[2:0] ......................................................................................................... 77
Table 9-26. Line Mode Select Bits LM[2:0]................................................................................................................ 78
Table 9-27. C-Bit DS3 Frame Overhead Bit Definitions ............................................................................................ 85
Table 9-28. M23 DS3 Frame Overhead Bit Definitions ............................................................................................. 87
Table 9-29. G.832 E3 Frame Overhead Bit Definitions ............................................................................................. 92
Table 9-30. Payload Label Match Status.................................................................................................................. 96
Table 9-31. Pseudo-Random Pattern Generation ................................................................................................... 109
Table 9-32. Repetitive Pattern Generation .............................................................................................................. 109
Table 9-33. Transformer Characteristics ................................................................................................................. 114
Table 9-34. Recommended Transformers............................................................................................................... 115
Table 10-1. Register Address Map .......................................................................................................................... 117
Table 11-1. Global Register Bit Map........................................................................................................................ 119
Table 11-2. Port Register Bit Map ........................................................................................................................... 119
Table 11-3. BERT Register Bit Map ........................................................................................................................ 120
Table 11-4. Line Register Bit Map .......................................................................................................................... 121
Table 11-5. HDLC Register Bit Map ........................................................................................................................ 121
Table 11-6. FEAC Register Bit Map ........................................................................................................................ 122
Table 11-7. Trail Trace Register Bit Map................................................................................................................. 123
Table 11-8. T3 Register Bit Map.............................................................................................................................. 123
Table 11-9. E3 G.751 Register Bit Map................................................................................................................... 124
Table 11-10. E3 G.832 Register Bit Map................................................................................................................. 125
Table 11-11. Global Register Map........................................................................................................................... 126
Table 11-12. Port Register Map............................................................................................................................... 133
Table 11-13. BERT Register Map............................................................................................................................ 144
Table 11-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 151
Table 11-15. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 152
Table 11-16. Transmit Side HDLC Register Map .................................................................................................... 156
Table 11-17. Receive Side HDLC Register Map ..................................................................................................... 159
Table 11-18. FEAC Transmit Side Register Map .................................................................................................... 163
10 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Table 11-19. FEAC Receive Side Register Map ..................................................................................................... 165
Table 11-20. Transmit Side Trail Trace Register Map............................................................................................. 168
Table 11-21. Trail Trace Receive Side Register Map.............................................................................................. 169
Table 11-22. Transmit DS3 Framer Register Map .................................................................................................. 174
Table 11-23. Receive DS3 Framer Register Map ................................................................................................... 176
Table 11-24. Transmit G.751 E3 Framer Register Map .......................................................................................... 183
Table 11-25. Receive G.751 E3 Framer Register Map ........................................................................................... 186
Table 11-26. Transmit G.832 E3 Framer Register Map .......................................................................................... 191
Table 11-27. Receive G.832 E3 Framer Register Map ........................................................................................... 194
Table 12-1. JTAG Instruction Codes ....................................................................................................................... 205
Table 12-2. JTAG ID Codes .................................................................................................................................... 206
Table 13-1. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Signal Name)............................................... 208
Table 13-2. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Pin #) ........................................................... 209
Table 13-3. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Signal Name)........................................... 210
Table 13-4. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Ball #) ...................................................... 211
Table 15-1. Thermal Information for 100-Pin CSBGA ............................................................................................. 215
Table 15-2. Thermal Information for 100-Pin LQFP ................................................................................................ 215
Table 16-1. Recommended DC Operating Conditions ............................................................................................ 216
Table 16-2. DC Electrical Characteristics ................................................................................................................ 216
Table 16-3. Output Pin Drive ................................................................................................................................... 217
Table 17-1. Framer Interface Timing ....................................................................................................................... 220
Table 17-2. System Port Interface Timing ............................................................................................................... 220
Table 17-3. Misc Timing .......................................................................................................................................... 221
Table 17-4. Overhead Port Timing .......................................................................................................................... 221
Table 17-5. SPI Bus Mode Timing........................................................................................................................... 222
Table 17-6. Micro Interface Timing .......................................................................................................................... 224
Table 17-7. DS3 Waveform Template ..................................................................................................................... 227
Table 17-8. DS3 Waveform Test Parameters and Limits ........................................................................................ 227
Table 17-9. E3 Waveform Test Parameters and Limits........................................................................................... 228
Table 17-10. Receiver Input Characteristics—DS3 Mode....................................................................................... 230
Table 17-11. Receiver Input Characteristics—E3 Mode ......................................................................................... 230
Table 17-12. Transmitter Output Characteristics—DS3 Modes .............................................................................. 231
Table 17-13. Transmitter Output Characteristics—E3 Mode................................................................................... 231
Table 17-14. JTAG Interface Timing........................................................................................................................ 232
11 of 233
2 APPLICATIONS
· Access Concentrators
· Multiservice Access Platforms
· ATM and Frame Relay Equipment
· Routers and Switches
· SONET/SDH ADM
· SONET/SDH Muxes
· PBXs
· Digital Cross Connect
· PDH Multiplexer/Demultiplexer
· Test Equipment
· Integrated Access Device (IAD)
Figure 2-1
Figure 2-1. DS3/E3 Line Card
show s a DS3170 application.
DS3170 DS3/E3 Single-Chip Transceiver
DS3/E3
Line
DS3/E3
Line
T3/E3 Line Card (#1)
T3/E3
Trans-
formers
DS3170
DS3/E3
SCT
T3/E3 Line Card (#n)
T3/E3
Trans-
formers
DS3170
DS3/E3
SCT
DS3/E3
Backplane
Signals
Digital Cross
Connect (DCS)
DS3/E3
Backplane
Signals
DS3/E3
Backplane
Singals
T3/E3 Line Card (#n+1)
DS3170
DS3/E3
SCT
T3/E3
Trans-
formers
T3/E3 Line Card (#n+n)
DS3170
DS3/E3
SCT
T3/E3
Trans-
formers
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DS3170 DS3/E3 Single-Chip Transceiver
3 FEATURE DETAILS
The following sections describe the features provided by the DS3170 SCT.
3.1 Global Features
§ Supports the following transmission formats:
C-Bit DS3
M23 DS3
G.751 E3
G.832 E3
§ All controls and status fields are software accessible over either an 8/16-bit microprocessor port or a slave
serial bus communication port up to 10 Mbps (SPI)
§ On-chip clock rate adapter incorporates two separate internal PLLs to generate the necessary DS3 or E3 clock
used internally from an input clock reference (DS3, E3, 51.84 MHz, 77.76 MHz, or 19.44 MHz) and to provide
an output reference clock for external usage
§ Optional transmit loop timed clock mode using the receive clock
§ Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
§ Clock, data and control signals can be inverted to allow a glueless interface to other devices
§ Detection of loss of transmit clock and loss of receive clock
§ Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
§ Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
§ Automatic one-second, external or manual update of performance monitoring counters
§ Framing and line code error insertion available
3.2 Receive DS3/E3 LIU Features
§ Performs equalization, gain control, and clock and data recovery for incoming DS3 and E3 signals
§ AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
§ Interfaces directly to a DSX-3 monitor signal (20 dB flat loss) using built-in pre-amp
§ Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
§ Loss-of-lock status indication for internal phase-locked loop
3.3 Jitter Attenuator Features
§ Fully integrated, requires no external components
§ Standards-compliant jitter attenuation/jitter transfer
§ Can be inserted into the receive path or the transmit path
§ 16-bit buffer depth
3.4 Receive DS3/E3 Framer Features
§ B3ZS/HDB3 decoding
§ Frame synchronization for M23 and C-bit Parity DS3, G.751 E3 and G.832 E3
§ Detection of RAI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit, DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
§ Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
§ Manual or automatic one-second update of performance monitoring counters
§ The E3 national bit (Sn) is forwarded to a status register bit, the HDLC controller or the FEAC controller
§ HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit, or G.832
NR or GC channels
§ FEAC controller with four-codeword FIFO for DS3 FEAC channel
§ 16-byte Trail Trace Buffer compares and stores G.832 trail access point identifier
§ DS3 M23 C-bits configurable as payload or overhead, stored in registers for software inspection
§ Most framing overhead fields presented on the receive overhead port
§ Framer pass-through mode for clear-channel applications and externally defined frame formats
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DS3170 DS3/E3 Single-Chip Transceiver
3.5 Transmit DS3/E3 Formatter Features
§ Frame insertion for M23 and C-bit parity DS3, G.751 E3 and G.832 E3
§ B3ZS/HDB3 encoding
§ Formatter pass-through mode for clear channel applications and externally defined frame formats
§ Generation of RAI, AIS, DS3 idle signal, and G.832-E3 RDI
§ Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors,
M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
§ The E3 national bit (Sn) can be sourced from a control register, from the HDLC controller, or from the FEAC
controller
§ Most framing overhead fields can be sourced from transmit overhead port
§ HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit, or G.832
NR or GC channels
§ FEAC controller for DS3 FEAC channel can be configured to send one codeword, one codeword continuously,
or two different codewords back-to-back to send DS3 Line Loopback commands
§ 16-byte Trail Trace Buffer sources the G.832 trail access point identifier
§ Insertion of G.832 payload type, and timing marker bits from registers
§ DS3 M23 C-bits configurable as payload or overhead; as overhead they can be controlled from registers or the
transmit overhead port
3.6 Transmit DS3/E3 LIU Features
§ Drives standards-compliant DS3 and E3 waveshapes onto 75W coaxial cable
§ Waveshape template compliance over all cable lengths without LBO adjustment
§ Tri-state line driver outputs support protection switching applications
§ Line driver monitor circuit and alarm output
§ Wide 50±20% transmit clock duty cycle
§ Line Build-Out (LBO) control
§ Output driver monitor
3.7 Clock Rate Adapter Features
§ Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input
reference clock
§ Input reference clock can be 77.76 MHz, 51.84 MHz, 44.736MHz, 34.368 MHz, or 19.44 MHz
§ Internally derived clock can be used as references for LIU and jitter attenuator
§ Derived clock can be transmitted off-chip for external system use through TCLKO pin
§ Standards-compliant jitter and wander requirements
3.8 HDLC Controller Features
§ Designed to handle multiple LAPD messages without Host intervention
§ 256 byte receive and transmit FIFOs are large enough to handle the three DS3 PMDL messages (Path ID, Idle
Signal ID, and Test Signal ID) that are sent and received once per second
§ Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
§ Programmable high or low water marks for the transmit and receive FIFOs
§ Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode or the G.751 Sn bit or the G.832 NR or
GC channels
3.9 FEAC Controller Features
§ Designed to handle multiple FEAC codewords without Host intervention
§ Receive FEAC automatically validates incoming codewords and stores them in a 4-codeword FIFO
§ Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different
codewords back-to-back to send DS3 Line Loopback commands
§ Terminates the FEAC channel in DS3 C-Bit Parity mode or the Sn bit in E3 mode
14 of 233
DS3170 DS3/E3 Single-Chip Transceiver
3.10 Trail Trace Buffer Features
§ Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
§ Insertion of the outgoing trail access point identifier from a 16-byte transmit register
§ Receive trace identifier unstable status indication
3.11 Bit Error-Rate Tester (BERT) Features
§ Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
§ Supports pattern insertion/extraction in DS3/E3 payload, or entire data stream
§ Large 24-bit error counter allows testing to proceed for long periods without host intervention
§ Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
§ Off-line monitoring on the Receive BERT
3.12 Loopback Features
§ LIU terminal loopback (transmit to receive) - ALB
§ Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - LLB
§ Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal toward
line/tributary interface - DLB
§ Simultaneous line facility loopback (LLB) and framer diagnostic loopback (DLB)
§ Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - PLB
3.13 Microprocessor Interface Features
§ Multiplexed or nonmultiplexed 8- or 16-bit control port
§ Intel and Motorola bus compatible
§ Global reset input pin
§ Global interrupt output pin
§ Eight programmable I/O pins (GPIOx)
3.14 Slave Serial Peripheral Interface (SPI) Features
§ Three-wire synchronous serial data link operating in full duplex slave mode up to 10 Mbps
§ Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260 and
microcontrollers such as M68HC11
§ Software provision ability for active phase of the serial clock (i.e. rising edge versus falling edge), bit ordering of
the serial data (most significant first versus least significant bit first)
3.15 Test Features
§ Five pin JTAG port
§ All functional pins are inout pins in JTAG mode
§ Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
§ Custom JTAG instructions to use RAM BIST
§ RAM BIST on all internal RAM
§ HIZ pin to force all digital output and inout pins into HIZ
§ TEST pin for manufacturing scan test modes
15 of 233
DS3170 DS3/E3 Single-Chip Transceiver
4 STANDARDS COMPLIANCE
Table 4-1. Standards Compliance
SPECIFICATION SPECIFICATION TITLE
ANSI
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
T1.646-1995
ATM Forum
af-phy-0034.000
af-phy-0054.000
ETSI
ETS 300 686
TBR 24
ETS EN 300 689
ETS 300 689
IETF
RFC 2496
ISO
ISO 3309:1993
ITU-T
G.703
G.704
G.751
G.775
G.823
G.824
G.832
I.432
O.151
Q.921
TELCORDIA
GR-499-CORE
GR-820-CORE
IEEE
IEEE Std 1149-
1990
Digital Hierarchy – Electrical Interfaces
Digital Hierarchy – Formats Specification
Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation – DS3 Metallic Interface Specification
Broadband ISDN – Physical Layer Specification for User-Network Interfaces Including
DS1/ATM
E3 Public UNI, August, 1995
DS3 Physical Layer Interface Specification, January, 1996
Business TeleCommunications; 34Mbps and 140Mbits/s digital leased lines (D34U, D34S,
D140U and D140S); Network interface presentation, 1996
Business TeleCommunications; 34Mbit/s digital unstructured and structured lease lines;
attachment requirements for terminal equipment interface, 1997
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications (BTC); 34 Mbps digital leased lines (D34U and D34S),
Terminal equipment interface, V 1.2.1, 2001-07
Definition of Managed Objects for the DS3/E3 Interface Type, January, 1999
Information Technology – Telecommunications & information exchange between systems –
High Level Data Link Control (HDLC) procedures – Frame structure, Fifth Edition, 1993
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Synchronous Frame Structures Used at 1544, 6312, 2048, 8488 and 44 736 kbit/s
Hierarchical Levels, July, 1995
Digital Multiplex Equipment Operating at the Third Order Bit Rate of 34,368 kbit/s and the
Fourth Order bit Rate of 139,264 kbit/s and Using Positive Justification, 1993
Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November, 1994
The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048
kbit/s Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Transport of SDH Elements on PDH Networks – Frame and Multiplexing Structures,
November, 1995
B-ISDN User-Network Interface – Physical Layer Specification, March, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October, 1992
ISDN User-Network Interface – Data Link Layer Specification, March 1993
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2,
December 1998
Generic Digital Transmission Surveillance, Issue 1, November 1994
IEEE Standard Test Access Port and Boundary-Scan Architecture, (Includes IEEE Std
1149-1993) October 21, 1993
16 of 233
DS3170 DS3/E3 Single-Chip Transceiver
5 ACRONYMS AND GLOSSARY
Definition of the terms used in this data sheet:
· CCM—Clear-Channel Mode
· CLAD—Clock Rate Adapter
· Clear Channel—A Datastream with no framing included, also known as Unframed
· FRM—Frame Mode
· FSCT—Framer Single-Chip Transceiver Mode
· HDLC—High-Level Data-Link Control
· Packet—HDLC Packet
· SCT—Single-Chip Transceiver (Framer and LIU)
· SCT Mode—DS3/E3 Framer and LIU
· Unchannelized—See Clear Channel
17 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6 MAJOR OPERATIONAL MODES
The major operational modes are determined by the FM[2:0] framer mode bits, as well as a few other control bits.
Unused features are powered down and the data paths are held in reset. The configuration registers of the unused
features can be written to and read from. Some of the IO pins change functions in different operational modes. The
line interface operational modes are determined by the LM[2:0] bits.
6.1 DS3/E3 Framed LIU Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
JA Off, B3ZS or HDB3 001 0 0
JA RX, B3ZS or HDB3 010 0 0
TLEN
PORT.CR2
JA TX, B3ZS or HDB3 011 0 0
JA Off, AMI 001 1 0
JA RX, AMI 010 1 0
JA TX, AMI 011 1 0
18 of 233
Figure 6-1. DS3/E3 Framed LIU Mode
TPOS/TDAT
TNEG
TLCLK
TXP
TXN
RPOS/RDAT
RNEG/RCLV
RLCLK
DS3/E3
Transmit
LIU
ALB
B3ZS/
HDB3
Encoder
LLB
TUA1
TAIS
DLB
FEAC
TOH
TOHEN
DS3 / E3
Transmit
Formatter
Trail
Trace
Buffer
TOHCLK
TOHSOF
HDLC
DS3170 DS3/E3 Single-Chip Transceiver
TCLKO/TGCLK
TSOFO/TDEN
TCLKI
TSER
TSOFI
TX
BERT
RX
PLB
BERT
RXP
RXN
DS3/E3
Receive
LIU
Clock Rate
Adapter
SPI
RST
REFCLK
Serial Interface Mode:
SPI (SCLK, MOSI, and MISO)
D[15:0]
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
ALE
A[8:1]
DS3 / E3
Receive
Framer
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
RDY
MODE
INT
WIDTH
GPIO[8:1]
ROH
ROHCLK
ROHSOF
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
JTDO
RSER
RCLKO/RGCLK
RSOFO/RDEN
19 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6.2 DS3/E3 Unframed LIU Mode
The frame mode determines the CLAD clock rate, LIU mode and selects B3ZS or HDB3.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
JA Off, B3ZS or HDB3 001 0 0
JA RX, B3ZS or HDB3 010 0 0
JA TX, B3ZS or HDB3 011 0 0
JA Off, AMI 001 1 0
JA RX, AMI 010 1 0
JA TX, AMI 011 1 0
Figure 6-2. DS3/E3 Unframed LIU Mode
TPOS
TNEG
TLCLK
TXP
TXN
RPOS
RNEG
RLCLK
RXP
RXN
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
TAIS
TUA1
TCLKO
TDEN
TCLKI
TSER
TX
BERT
DLB
PLB
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
INT
RDY
MODE
WIDTH
GPIO[8:1]
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
20 of 233
6.3 DS3/E3 Framed POS/NEG Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
LIU Off, B3ZS or HDB3 000 0 1
LIU Off, AMI 000 1 1
Figure 6-3. DS3/E3 Framed POS/NEG Mode
DS3170 DS3/E3 Single-Chip Transceiver
TPOS
TNEG
TLCLK
RPOS
RNEG
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
SPI
RST
Serial Interface Mode:
(SCLK, MOSI, and MISO)
ALE
D[15:0]
A[8:1]
A[0]/BSWAP
TAIS
TUA1
DLB
CS
RD/DS
TOHCLK
TOH
TOHSOF
TOHEN
TCLKO/TGCLK
TSOFO/TDEN
DS3 / E3
Transmit
Formatter
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
Buffer
PLB
DS3 / E3
Receive
Framer
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
ROH
ROHCLK
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO/RGCLK
RSOFO/RDEN
JTDO
21 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6.4 DS3/E3 Unframed POS/NEG Mode
The frame mode determines the CLAD clock rate if used as the transmit clock and selects B3ZS or HDB3.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
LIU Off, B3ZS or HDB3 000 0 1
LIU Off, AMI 000 1 1
Figure 6-4. DS3/E3 Unframed POS/NEG Mode
TPOS
TNEG
TLCLK
RPOS
RNEG
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inte face
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
A[0]/BSWAP
TAIS
TUA1
DLB
CS
RD/DS
TCLKO
TDEN
TCLKI
TSER
TX
BERT
RX
PLB
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
22 of 233
6.5 DS3/E3 Framed UNI Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
Unipolar Mode 1XX X 1
Figure 6-5. DS3/E3 Framed UNI Mode
TOHCLK
TOH
TOHSOF
TOHEN
DS3170 DS3/E3 Single-Chip Transceiver
TDAT
TLCLK
RDAT
RLCV
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
LLB
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
TAIS
TUA1
DS3 / E3
Transmit
Formatter
TCLKO/TGC LK
TSOFO/TDE N
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
DLB
Buffer
DS3 / E3
Receive
PLB
Framer
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
RDY
MODE
WIDTH
INT
ROH
ROHCLK
GPIO[8:1]
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
JTDO
RSER
RCLKO/RGCLK
RSOFO/RDEN
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DS3170 DS3/E3 Single-Chip Transceiver
6.6 DS3/E3 Unframed UNI Mode
The frame mode determines the CLAD clock rate if used as the transmit clock.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
Unipolar Mode 1XX X 1
Figure 6-6. DS3/E3 Unframed UNI Mode
TAIS
TUA1
TDAT
TLCLK
TX
BERT
TCLKO
TDEN
TCLKI
TSER
RDAT
RLCV
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
LLB
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
A[0]/BSWAP
CS
DLB
RD/DS
RX
PLB
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
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DS3170 DS3/E3 Single-Chip Transceiver
7 PIN DESCRIPTIONS
Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for
isolation of interconnect failures.
7.1 Short Pin Descriptions
Table 7-1. DS3170 Short Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional in/out)
NAME TYPE FUNCTION
Line IO
TLCLK O Transmit Line Clock Output
TPOS / TDAT O Transmit Positive AMI / Data E9 67
TNEG O Transmit Negative AMI D9 70
TXP Oa Transmit Positive analog E1, E2 12, 13
TXN Oa Transmit Negative analog F1, F2 16, 17
RLCLK I Receive Clock Input A8 81
RXP Ia Receive Positive analog A4 94
RXN Ia Receive Negative analog A3 97
RPOS / RDAT Ia Positive AMI / Data F10 62
RNEG / RLCV Ia Negative AMI / Line Code Violation F9 63
DS3/E3 Overhead Interface
TOH I Transmit Overhead C7 83
TOHEN I Transmit Overhead Enable E10 66
TOHCLK O Transmit Overhead Clock D7 82
TOHSOF O Transmit Overhead Start Of Frame G9 60
ROH O Receive Overhead B6 88
ROHCLK O Receive Overhead Clock C9 73
ROHSOF O Receive Overhead Start Of Frame F8 61
DS3/E3 Serial Data DS3/E3 Overhead Interface
TCLKI I Transmit Line Clock Input C10 72
TSOFI I Transmit Start Of Frame Input A9 78
TSER I Transmit Serial Data B10 75
TCLKO / TGCLK O Transmit Clock Output / Gapped Clock B9 77
TSOFO / TDEN O Transmit Framer Start Of Frame / Data Enable C8 79
RSER O Receive Serial Data C6 86
RCLKO / RGCLK O Receive / Clock Output / Gapped Clock A6 87
RSOFO / RDEN O Receive Framer Start Of Frame / Data Enable B8 80
Microprocessor Interface
D[15] IO Data [15] G8 58
D[14] IO Data [14] H10 56
D[13] IO Data [13] H9 55
D[12] IO Data [12] H8 54
D[11] IO Data [11] J10 53
D[10] IO Data [10] J9 52
D[9] IO Data [9] G6 40
D[8] IO Data [8] J8 48
D[7]/SPI_CPOL IO Data [7] / SPI Interface Clock Polarity K8 47
D[6]/SPI_CPHA IO Data [6] / SPI Interface Clock Phase H7 46
D[5]/SPI_SWAP IO Data [5:3] / SPI Bit Order Swap J7 45
D[4] IO Data [4] K7 44
D[3] IO Data [3] H6 43
BGA LQFP
B7 85
PIN
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DS3170 DS3/E3 Single-Chip Transceiver
NAME TYPE FUNCTION
BGA LQFP
PIN
D[2]/SPI_SCLK IO Data [2] / SPI Serial Interface Clock < 10 MHz J6 42
D[1]/SPI_MOSI IO Data [1] / SPI Serial Interface Data Master-out
Slave-in
D[0]SPI_MISO IO Data [0] / SPI Serial Interface Data Master-in
Slave-out
A[8]
I Address [8:1] H5
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
K9 50
J5 38
36
J4
H4
K3
J3
H3
K2
J2
35
33
31
30
29
28
27
A[0]/BSWAP Address [0] / Byte Swap mode K5 37
ALE I Address Latch Enable G4 32
CS
RD/DS
WR / R/W
RDY
INT
I Chip Select (active low)
I Read Strobe (active low) / Data Strobe (active
low)
I Write Strobe (active low) / R/W Select
Oz Ready Handshake (active low)
O Interrupt (open drain active low)
A1 1
B2 2
C2 5
J1 25
D8 71
MODE I Mode Select (RD/WR or DS strobe mode) F3 18
WIDTH I Width Select (8 or 16 bit interface) H2 23
SPI I SPI Serial bus mode C3 4
Misc I/O
GPIO[8]
GPIO[7]
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
TEST
HIZ
RST
IO General Purpose IO [8:1] D4
D3
G5
F6
G7
F7
E7
E8
I Test enable (active low)
I High impedance test enable (active low)
I Reset (active low)
F5 24
B4 95
E6 74
7
8
39
49
57
64
65
68
JTAG
JTCLK I JTAG Clock A5 91
JTMS Ipu JTAG Mode Select (with pullup) B3 98
JTDI Ipu JTAG Data Input (with pullup) C4 96
JTDO Oz JTAG Data Output D5 90
JTRST
Ipu JTAG Reset (active low with pullup)
E5 99
CLAD
REFCLK I Reference Clock H1 22
POWER
VSS PWR Ground, 0 Volt potential C1, K1, K6,
G10, A10,
A2
VDD PWR Digital 3.3V B1, D1, K4,
K10, D10,
A7
6, 26, 41,
59, 76, 100
3, 9, 34, 51,
69, 84
AVDDR PWR Analog 3.3V for Receive LIU C5 93
AVDDT PWR Analog 3.3V for Transmit LIU F4 15
AVDDJ PWR Analog 3.3V for Jitter Attenuator E3 11
AVDDC PWR Analog 3.3V for CLAD G3 21
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DS3170 DS3/E3 Single-Chip Transceiver
NAME TYPE FUNCTION
BGA LQFP
PIN
AVSSR PWR Analog Gnd for Receive LIU B5 92
AVSST PWR Analog Gnd for Transmit LIU E4 14
AVSSJ PWR Analog Gnd for Jitter Attenuator D2 10
AVSSC PWR Analog Gnd for CLAD G1 19
UNUSED
UNUSED1 N/A Unused D6 89
UNUSED2 N/A Unused G2 20
7.2 Detailed Pin Descriptions
Table 7-2. Detailed Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional inout)
PIN NAME TYPE PIN DESCRIPTION
Line IO
TLCLK O Transmit Line Clock Output
TLCLK: This signal is available when the transmit line interface pins are enabled
TLEN). This clock is typically used as the clock reference for the TDAT
20 ppm
20 ppm
TLEN), a high on this pin
TLEN), the un-encoded transmit signal is
20ppm
20ppm
TPOS /
TDAT
(PORT.CR2.
and TNEG signals, but can also be used as the reference for the TSOFI, TSER, and
TSOFO / TDEN signals.
This output signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
O Transmit Positive AMI / Data Output
TPOS: When the port line interface is configured for B3ZS, HDB3 or AMI mode and
the transmit line interface pins are enabled (PORT.CR2.
indicates that a positive pulse should be transmitted on the line. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TLCLK line clock output pins, but it can be referenced to the
TCLKO, TCLKI, RLCLK or RCLKO pins. This output signal can be disabled when the
TX LIU is enabled.
This output signal can be inverted.
TDAT: When the port line interface is configured for UNI mode and the transmit line
interface pins are enabled (PORT.CR2.
output on this pin. The signal is updated on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the TLCLK line clock output
pins, but it can be referenced to the TCLKO, TCLKI, RLCLK or RCLKO pins
This output signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
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DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
TNEG O Transmit Negative AMI / Line OH Mask
TNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the
transmit line interface pins are enabled (PORT.CR2.
indicates that a negative pulse should be transmitted on the line. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLK line clock output pins, but it can be referenced to
the TCLKO, TCLKI, RLCLK or RCLKO pins.
This output signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
TXP Oa Transmit Positive Analog
TXP: This pin and the TXN pin form a differential AMI output which is coupled to the
outbound 75W coaxial cable through a 2:1 step-down transformer (Figure 1-1
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
TXN Oa Transmit Negative Analog
TXN: This pin and the TXP pin form a differential AMI output which is coupled to the
outbound 75W coaxial cable through a 2:1 step-down transformer (Figure 1-1
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RXP Ia Receive Positive analog
RXP: This pin and the RXN pin form a differential AMI input which is coupled to the
outbound 75W coaxial cable through a 2:1 step-up transformer (Figure 1-1
is used when the RX LIU is enabled and is ignored when the LIU is disabled.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RXN Ia Receive Negative analog
RXN: This pin and the RXP pin form a differential AMI input which is coupled to the
outbound 75W coaxial cable through a 2:1 step-up transformer (Figure 1-1
is used when the LIU is enabled and is ignored when the LIU is disabled.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RLCLK I Receive Line Clock Input
RLCLK: This clock is typically used for the reference clock for the RPOS / RDAT,
RNEG / RLCV signals but can also be used as the reference clock for the RSER,
RSOFO / RDEN, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.
This input is ignored when the LIU is enabled.
This input signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
20 ppm
20 ppm
TLEN), a high on this pin
). This
). This
). This input
). This input
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DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
RPOS /
RDAT
Iad Receive Positive AMI / Data
RPOS: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
disabled, a high on this pin indicates that a positive pulse has been detected using an
external LIU. The signal is sampled on the positive clock edge of the referenced clock
pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of
the clock. The signal is typically referenced to the RLCLK line clock input pins, but it
can be referenced to the RCLKO output pins.
This input signal can be inverted.
RDAT: When the port line interface is configured for UNI mode, the un-encoded
receive signal is input on this pin. The signal is sampled on the positive clock edge of
the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled
on the falling edge of the clock. The signal is typically referenced to the RLCLK line
clock input pins, but it can be referenced to the RCLK output pins.
This input signal can be inverted.
RNEG /
RLCV
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
Iad Receive Negative AMI / Line Code Violation / Line OH Mask input
RNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
20ppm
20ppm
disabled, a high on this pin indicates that a negative pulse has been detected using
an external LIU. The signal is sampled on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling
edge of the clock. The signal is typically referenced to the RLCLK line clock input
pins, but it can be referenced to the RCLKO output pins.
This input signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RLCV: When the port line interface is configured for UNI mode, the BPV counter in
the encoder/decoder block is incremented each clock when this signal is high. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock
pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The
signal is typically referenced to the RLCLK line clock input pins, but it can be
referenced to the RCLKO output pins.
This input signal can be inverted.
DS3/E3 Overhead Interface
TOH I Transmit Overhead
TOH: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used to over-write the DS3 or E3 framing overhead bits when
TOHEN is active. In T3 mode, the X-bits, P-bits, M-bits, F-bits, and C-bits are input. In
G.751 E3 mode, all of the FAS, RAI, and National Use bits are input. In G.832 E3
mode, all of the FA1, FA2, EM, TR, MA, NR, and GC bytes are input. The TOHSOF
signal marks the start of the framing bit sequence. This signal is sampled at the same
time as the TOHCLK signal transitions high to low.
This signal can be inverted.
TOHEN I Transmit Overhead Enable / Start Of Frame Input
TOHEN: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used the determine which DS3 or E3 framing overhead bits to overwrite with the signal on the TOH pin. The TOHSOF signal marks the start of the
framing bit sequence. This signal is sampled at the same time as the TOHCLK signal
transitions high to low.
This signal can be inverted.
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DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
TOHCLK O Transmit Overhead Clock
TOHCLK: When the port framer is configured for one of the DS3 or E3 framing
modes, this clock is used for the transmit overhead port signals TOH, TOHEN and
TOHSOF. The TOHSOF output signal is updated and the TOH and TOHEN input
signals are sampled at the same time this clock signal transitions from high to low.
The external logic is expected to sample TOHSOF signal and update the TOH and
TOHEN signals on the rising edge of this clock signal. This clock is a low frequency
clock.
This signal can be inverted.
TOHSOF O Transmit Overhead Start Of Frame
TOHSOF: When the port framer is configured for one of the DS3 or E3 framing
modes, this signal is used to mark the start of a DS3 or E3 overhead sequence on the
TOH pin. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the
FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The
sequence starts on the same high to low transition of the TOHCLK clock that this
signal is high. This signal is updated at the same time as the TOHCLK signal
transitions high to low.
This signal can be inverted.
ROH O Receive Overhead
ROH: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal outputs the value of the receive overhead bits. The ROHSOF signal marks
the start of the framing bit sequence. In T3 mode, the X-bits, P-bits, M-bits, F-bits,
and C-bits are output (Note: In M23 mode, the C-bits are extracted even though they
are marked as data at the payload interface). In G.751 E3 mode, all of the FAS, RAI,
and National Use bits are output. In G.832 E3 mode, all of the FA1, FA2, EM, TR,
MA, NR, and GC bytes are output.
This signal is updated at the same time as the ROHCLK signal transitions high to low.
This signal can be inverted.
ROHCLK O Receive Overhead Clock
ROHCLK: When the port framer is configured for one of the DS3 or E3 framing
modes, this clock is used for the receive overhead port signals ROH and ROHSOF.
The ROHSOF and ROH output signals are updated at the same time this clock signal
transitions from high to low. The external logic is expected to sample ROHSOF and
ROH signal on the rising edge of this clock signal. This clock is a low frequency clock.
This signal can be inverted.
ROHSOF O Receive Overhead Start Of Frame
ROHSOF: When the port framer is configured for one of the DS3 or E3 framing
modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the
ROH pins. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the
FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The
sequence starts on the same high to low transition of the ROHCLK clock that this
signal is high. This signal is updated at the same time as the ROHCLK signal
transitions high to low.
This signal can be inverted.
DS3/E3 Serial Data Overhead Interface
TCLKI I Transmit Line Clock Input
TCLKI: This clock is typically used for the reference clock for the TSOFI, TSER, and
TSOFO / TDEN signals but can also be used as the reference for the TPOS / TDAT
and TNEG signals. This clock is not used when the part is in loop time mode or the
CLAD clocks are used as the transmit clock source. (PORT.CR3.CLADC)
This input signal can be inverted.
o DS3: 44.736 MHz +20 ppm
o E3: 34.368 MHz +
20 ppm
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