r
www.maxim-ic.com
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceive
GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS
Access Concentrators
Routers and Switches
SONET/SDH ADM
SONET/SDH Muxes
PBXs Test Equipment
Demultiplexer
Multiservice Access
Platforms (MSAPs)
Multiservice Protocol
Platform (MSPPs)
Digital Cross Connect PDH Multiplexer/
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3170 0°C to +70°C
DS3170L 0°C to +70°C
DS3170N -40°C to +85°C
DS3170LN -40°C to +85°C
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
FUNCTIONAL DIAGRAM
DS3/E3 LINE
DS3/
E3
LIU
DS3170
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES
§ Single-Chip Transceiver for DS3 and E3
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
§ Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
§ On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
§ Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
§ Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
§ Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
§ CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
§ Software Compatible with DS3171–DS3174 SCT
Product Family
§ 8-/16-Bit Parallel and Slave SPI Serial (≤10Mbps)
Microprocessor Interface
§ Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
§ 100-Pin Small 11mm (1mm) CSBGA and 14mm
(1.4mm) LQFP Package Options
§ Industrial Temperature Operation: -40°C to +85°C
§ IEEE1149.1 JTAG Test Port
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1 of 233
REV: 101404
.
DS3170 DS3/E3 Single-Chip Transceiver
DETAILED DESCRIPTION
The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has
independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and
data input. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard
pulse-shape waveforms onto 75W coaxial cable and can be bypassed for direct clock and data output. The jitter
attenuator can be put in the transmit or receive data path when the LIU is enabled. Built-in DS3/E3 framers transmit
and receive data in properly formatted C-bit DS3, M23 DS3, G.751 E3 or G.832 E3 data streams. Functions not
used are powered down to reduce system power requirements. The DS3170 conforms to the telecommunications
standards listed in Section 3.2
.
1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at the LIU interface for proper operation. Figure 1-2 shows the
functional block diagram of the one channel DS3/E3 SCT.
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170
Transmit
DS3/E3 LIU Interface
TXP
W
330
(1%)
VDD
VDD
0.01uF
0.01uF
0.1uF
0.1uF
1uF
1uF
3.3V
Power
Plane
TXN
1:2ct
VDD
0.01uF
0.1uF
1uF
Receive
1:2ct
330
(1%)
RXP
W
RXN
VSS
VSS
VSS
Ground
Plane
2 of 233
Figure 1-2. Block Diagram
DS3170 DS3/E3 Single-Chip Transceiver
TOHCLK
TOH
TOHSOF
TOHEN
TPOS/TDAT
TNEG
TLCLK
TXP
TXN
RPOS/RDAT
RNEG/RCLV
RLCLK
RXP
RXN
DS3170
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
SPI
RST
REFCLK
Serial Interface Mode:
SPI (SCLK, MOSI, and MISO)
D[15:0]
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
ALE
TUA1
Serial or Parallel
uP Inteface
CS
A[8:1]
A[0]/BSWAP
TAIS
DLB
RD/DS
TCLKO/TGCLK
TSOFO/TDEN
DS3 / E3
Transmit
Formatter
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
Buffer
PLB
DS3 / E3
Receive
Framer
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
ROH
ROHCLK
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO/RGCLK
RSOFO/RDEN
JTDO
3 of 233
DS3170 DS3/E3 Single-Chip Transceiver
TABLE OF CONTENTS
1 BLOCK DIAGRAMS 2
2 APPLICATIONS 12
3 FEATURE DETAILS 13
3.1 GLOBAL FEATURES........................................................................................................................................ 13
3.2 RECEIVE DS3/E3 LIU FEATURES .................................................................................................................. 13
3.3 JITTER ATTENUATOR FEATURES..................................................................................................................... 13
3.4 RECEIVE DS3/E3 FRAMER FEATURES ........................................................................................................... 13
3.5 TRANSMIT DS3/E3 FORMATTER FEATURES .................................................................................................... 14
3.6 TRANSMIT DS3/E3 LIU FEATURES................................................................................................................. 14
3.7 CLOCK RATE ADAPTER FEATURES ................................................................................................................. 14
3.8 HDLC CONTROLLER FEATURES..................................................................................................................... 14
3.9 FEAC CONTROLLER FEATURES ..................................................................................................................... 14
3.10 TRAIL TRACE BUFFER FEATURES ................................................................................................................... 15
3.11 BIT ERROR-RATE TESTER (BERT) FEATURES ................................................................................................ 15
3.12 LOOPBACK FEATURES ................................................................................................................................... 15
3.13 MICROPROCESSOR INTERFACE FEATURES ..................................................................................................... 15
3.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ................................................................................ 15
3.15 TEST FEATURES............................................................................................................................................ 15
4 STANDARDS COMPLIANCE 16
5 ACRONYMS AND GLOSSARY 17
6 MAJOR OPERATIONAL MODES 18
6.1 DS3/E3 FRAMED LIU MODE.......................................................................................................................... 18
6.2 DS3/E3 UNFRAMED LIU MODE ..................................................................................................................... 20
6.3 DS3/E3 FRAMED POS/NEG MODE............................................................................................................... 21
6.4 DS3/E3 UNFRAMED POS/NEG MODE .......................................................................................................... 22
6.5 DS3/E3 FRAMED UNI MODE ......................................................................................................................... 23
6.6 DS3/E3 UNFRAMED UNI MODE..................................................................................................................... 24
7 PIN DESCRIPTIONS 25
7.1 SHORT PIN DESCRIPTIONS............................................................................................................................. 25
7.2 DETAILED PIN DESCRIPTIONS......................................................................................................................... 27
7.3 PIN FUNCTIONAL TIMING ................................................................................................................................37
7.3.1 Line IO.................................................................................................................................................. 37
7.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 40
7.3.3 DS3/E3 Serial Data Interface ............................................................................................................... 41
7.3.4 Microprocessor Interface Functional Timing ........................................................................................ 43
7.3.5 JTAG Functional Timing....................................................................................................................... 50
8 INITIALIZATION AND CONFIGURATION 51
8.1 MONITORING AND DEBUGGING ....................................................................................................................... 52
9 FUNCTIONAL DESCRIPTION 53
9.1 PROCESSOR BUS INTERFACE ......................................................................................................................... 53
9.1.1 SPI Serial Port Mode............................................................................................................................ 53
9.1.2 8/16 Bit Bus Widths.............................................................................................................................. 53
9.1.3 Ready Signal (
9.1.4 Byte Swap Modes ................................................................................................................................ 53
9.1.5 Read-Write/Data Strobe Modes ........................................................................................................... 53
9.1.6 Clear on Read/Clear on Write Modes .................................................................................................. 53
9.1.7 Interrupt and Pin Modes....................................................................................................................... 54
9.1.8 Interrupt Structure ................................................................................................................................ 54
9.2 CLOCKS ........................................................................................................................................................ 55
9.2.1 Line Clock Modes................................................................................................................................. 55
9.2.2 Sources of Clock Output Pin Signals ................................................................................................... 57
9.2.3 Line IO Pin Timing Source Selection ................................................................................................... 59
9.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 62
4 of 233
RDY
) ............................................................................................................................. 53
DS3170 DS3/E3 Single-Chip Transceiver
9.2.5
Gapped Clocks..................................................................................................................................... 63
9.3 RESET AND POWER-DOWN ............................................................................................................................ 63
9.4 GLOBAL RESOURCES..................................................................................................................................... 66
9.4.1 Clock Rate Adapter (CLAD)................................................................................................................. 66
9.4.2 8 kHz Reference Generation ............................................................................................................... 66
9.4.3 One Second Reference Generation..................................................................................................... 67
9.4.4 General-Purpose IO Pins ..................................................................................................................... 68
9.4.5 Performance Monitor Counter Update Details ..................................................................................... 69
9.4.6 Transmit Manual Error Insertion .......................................................................................................... 70
9.5 PORT RESOURCES ........................................................................................................................................71
9.5.1 Loopbacks ............................................................................................................................................ 71
9.5.2 Loss Of Signal Propagation ................................................................................................................. 73
9.5.3 AIS Logic .............................................................................................................................................. 73
9.5.4 Loop Timing Mode ............................................................................................................................... 75
9.5.5 HDLC Overhead Controller .................................................................................................................. 75
9.5.6 Trail Trace ............................................................................................................................................ 75
9.5.7 BERT.................................................................................................................................................... 75
9.5.8 System Port Pins.................................................................................................................................. 76
9.5.9 Framing Modes .................................................................................................................................... 77
9.5.10 Line Interface Modes............................................................................................................................ 77
9.6 DS3/E3 FRAMER / FORMATTER ..................................................................................................................... 79
9.6.1 General Description ............................................................................................................................. 79
9.6.2 Features ............................................................................................................................................... 79
9.6.3 Transmit Formatter............................................................................................................................... 80
9.6.4 Receive Framer.................................................................................................................................... 80
9.6.5 C-bit DS3 Framer/Formatter ................................................................................................................ 84
9.6.6 M23 DS3 Framer/Formatter ................................................................................................................. 87
9.6.7 G.751 E3 Framer/Formatter................................................................................................................. 89
9.6.8 G.832 E3 Framer/Formatter................................................................................................................. 91
9.7 HDLC OVERHEAD CONTROLLER.................................................................................................................... 96
9.7.1 General Description ............................................................................................................................. 96
9.7.2 Features ............................................................................................................................................... 97
9.7.3 Transmit FIFO ...................................................................................................................................... 97
9.7.4 Transmit HDLC Overhead Processor .................................................................................................. 98
9.7.5 Receive HDLC Overhead Processor ................................................................................................... 98
9.7.6 Receive FIFO ....................................................................................................................................... 99
9.8 TRAIL TRACE CONTROLLER............................................................................................................................ 99
9.8.1 General Description ............................................................................................................................. 99
9.8.2 Features ............................................................................................................................................. 100
9.8.3 Functional Description........................................................................................................................ 100
9.8.4 Transmit Data Storage ....................................................................................................................... 101
9.8.5 Transmit Trace ID Processor ............................................................................................................. 101
9.8.6 Transmit Trail Trace Processing ........................................................................................................ 101
9.8.7 Receive Trace ID Processor .............................................................................................................. 101
9.8.8 Receive Trail Trace Processing ......................................................................................................... 101
9.8.9 Receive Data Storage ........................................................................................................................ 102
9.9 FEAC CONTROLLER ................................................................................................................................... 102
9.9.1 General Description ........................................................................................................................... 102
9.9.2 Features ............................................................................................................................................. 103
9.9.3 Functional Description........................................................................................................................ 103
9.10 LINE ENCODER/DECODER............................................................................................................................ 104
9.10.1 General Description ........................................................................................................................... 104
9.10.2 Features............................................................................................................................................. 105
9.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 105
9.10.4 Transmit Line Interface ...................................................................................................................... 105
9.10.5 Receive Line Interface ....................................................................................................................... 106
9.10.6 B3ZS/HDB3 Decoder......................................................................................................................... 106
9.11 BERT......................................................................................................................................................... 108
9.11.1 General Description ........................................................................................................................... 108
5 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9.11.2
Features ............................................................................................................................................. 108
9.11.3 Configuration and Monitoring ............................................................................................................. 108
9.11.4 Receive Pattern Detection ................................................................................................................. 109
9.11.5 Transmit Pattern Generation.............................................................................................................. 111
9.12 LIU – LINE INTERFACE UNIT ........................................................................................................................ 112
9.12.1 General Description ........................................................................................................................... 112
9.12.2 Features ............................................................................................................................................. 112
9.12.3 Detailed Description ........................................................................................................................... 112
9.12.4 Transmitter ......................................................................................................................................... 113
9.12.5 Receiver ............................................................................................................................................. 114
10 OVERALL REGISTER MAP 117
11 REGISTER MAPS AND DESCRIPTIONS 119
11.1 REGISTERS BIT MAPS.................................................................................................................................. 119
11.1.1 Global Register Bit Map ..................................................................................................................... 119
11.1.2 HDLC Register Bit Map...................................................................................................................... 121
11.1.3 T3 Register Bit Map ........................................................................................................................... 123
11.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
11.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
11.2 GLOBAL REGISTERS ....................................................................................................................................126
11.2.1 Register Bit Descriptions.................................................................................................................... 126
11.3 PORT REGISTER.......................................................................................................................................... 133
11.3.1 Register Bit Descriptions.................................................................................................................... 133
11.4 BERT......................................................................................................................................................... 144
11.4.1 BERT Register Map ........................................................................................................................... 144
11.4.2 BERT Register Bit Descriptions ......................................................................................................... 144
11.5 B3ZS/HDB3 LINE ENCODER/DECODER ....................................................................................................... 151
11.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 151
11.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 152
11.6 HDLC......................................................................................................................................................... 156
11.6.1 HDLC Transmit Side Register Map.................................................................................................... 156
11.6.2 HDLC Receive Side Register Map..................................................................................................... 159
11.7 FEAC CONTROLLER ................................................................................................................................... 163
11.7.1 FEAC Transmit Side Register Map.................................................................................................... 163
11.7.2 FEAC Receive Side Register Map ..................................................................................................... 165
11.8 TRAIL TRACE............................................................................................................................................... 168
11.8.1 Trail Trace Transmit Side ................................................................................................................... 168
11.8.2 Trail Trace Receive Side Register Map ............................................................................................. 169
11.9 DS3/E3 FRAMER......................................................................................................................................... 174
11.9.1 Transmit DS3 ..................................................................................................................................... 174
11.9.2 Receive DS3 Register Map................................................................................................................ 176
11.9.3 Transmit G.751 E3 ............................................................................................................................. 183
11.9.4 Receive G.751 E3 Register Map ....................................................................................................... 186
11.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 191
11.9.6 Receive G.832 E3 Register Map ....................................................................................................... 194
12 JTAG INFORMATION 202
12.1 JTAG DESCRIPTION .................................................................................................................................... 202
12.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................. 203
12.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................................... 205
12.4 JTAG ID CODES......................................................................................................................................... 206
12.5 JTAG FUNCTIONAL TIMING.......................................................................................................................... 207
12.6 IO PINS ...................................................................................................................................................... 207
13 PIN CONFIGURATIONS 208
14 PACKAGE INFORMATION 213
15 PACKAGE THERMAL INFORMATION 215
16 DC ELECTRICAL CHARACTERISTICS 216
17 AC TIMING CHARACTERISTICS 218
6 of 233
DS3170 DS3/E3 Single-Chip Transceiver
17.1
FRAMER DATA PATH AC CHARACTERISTICS ................................................................................................. 220
17.2 OVERHEAD PORT AC CHARACTERISTICS...................................................................................................... 221
17.3 MICRO INTERFACE AC CHARACTERISTICS .................................................................................................... 222
17.3.1 SPI Bus Mode ....................................................................................................................................222
17.3.2 Parallel Bus Mode .............................................................................................................................. 224
17.4 CLAD JITTER CHARACTERISTICS ................................................................................................................. 227
17.5 LIU INTERFACE AC CHARACTERISTICS ........................................................................................................ 227
17.5.1 Waveform Templates ......................................................................................................................... 227
17.5.2 LIU Input/Output Characteristics ........................................................................................................ 230
17.6 JTAG INTERFACE AC CHARACTERISTICS..................................................................................................... 232
18 REVISION HISTORY 233
7 of 233
DS3170 DS3/E3 Single-Chip Transceiver
LIST OF FIGURES
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170 ....................................................................... 2
Figure 1-2. Block Diagram ........................................................................................................................................... 3
Figure 2-1. DS3/E3 Line Card ................................................................................................................................... 12
Figure 6-1. DS3/E3 Framed LIU Mode ...................................................................................................................... 19
Figure 6-2. DS3/E3 Unframed LIU Mode .................................................................................................................. 20
Figure 6-3. DS3/E3 Framed POS/NEG Mode ........................................................................................................... 21
Figure 6-4. DS3/E3 Unframed POS/NEG Mode........................................................................................................ 22
Figure 6-5. DS3/E3 Framed UNI Mode ..................................................................................................................... 23
Figure 6-6. DS3/E3 Unframed UNI Mode .................................................................................................................. 24
Figure 7-1. Tx Line IO B3ZS Functional Timing Diagram.......................................................................................... 37
Figure 7-2. Tx Line IO HDB3 Functional Timing Diagram ......................................................................................... 38
Figure 7-3. Rx Line IO B3ZS Functional Timing Diagram ......................................................................................... 38
Figure 7-4. Rx Line IO HDB3 Functional Timing Diagram......................................................................................... 39
Figure 7-5. Tx Line IO UNI Functional Timing Diagram ............................................................................................ 39
Figure 7-6. Rx Line IO UNI Functional Timing Diagram ............................................................................................ 40
Figure 7-7. DS3 Framing Receive Overhead Port Timing......................................................................................... 40
Figure 7-8. E3 G.751 Framing Receive Overhead Port Timing ................................................................................ 40
Figure 7-9. E3 G.832 Framing Receive Overhead Port Timing ................................................................................ 40
Figure 7-10. DS3 Framing Transmit Overhead Port Timing...................................................................................... 41
Figure 7-11. E3 G.751 Framing Transmit Overhead Port Timing ............................................................................. 41
Figure 7-12. E3 G.832 Framing Transmit Overhead Port Timing ............................................................................. 41
Figure 7-13. DS3 Framed Mode Transmit Serial Interface Pin Timing ..................................................................... 42
Figure 7-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing ............................................................. 42
Figure 7-15. E3 G.832 Framed Mode Transmit Serial Interface Pin Timing ............................................................. 42
Figure 7-16. DS3 Framed Mode Receive Serial Interface Pin Timing ...................................................................... 43
Figure 7-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing .............................................................. 43
Figure 7-18. E3 G.832 Framed Mode Receive Serial Interface Pin Timing .............................................................. 43
Figure 7-19. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0 .............................................. 44
Figure 7-20. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................ 44
Figure 7-21. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................ 44
Figure 7-22. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................ 44
Figure 7-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................ 45
Figure 7-24. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................ 45
Figure 7-25. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................ 45
Figure 7-26. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................ 45
Figure 7-27. 16-Bit Mode Write.................................................................................................................................. 46
Figure 7-28. 16-Bit Mode Read ................................................................................................................................. 46
Figure 7-29. 8-Bit Mode Write.................................................................................................................................... 47
Figure 7-30. 8-Bit Mode Read ................................................................................................................................... 47
Figure 7-31. 16-Bit Mode without Byte Swap ............................................................................................................ 48
Figure 7-32b 16-Bit Mode with Byte Swap ................................................................................................................ 48
Figure 7-33. Clear Status Latched Register on Read................................................................................................ 49
Figure 7-34. Clear Status Latched Register on Write................................................................................................ 49
Figure 7-35. RDY Signal Functional Timing Write ..................................................................................................... 50
Figure 7-36. RDY Signal Functional Timing Read ..................................................................................................... 50
Figure 9-1. Interrupt Structure ................................................................................................................................... 55
Figure 9-2. Internal Tx Clock ..................................................................................................................................... 58
Figure 9-3. Internal Rx Clock ..................................................................................................................................... 59
Figure 9-4. Example IO Pin Clock Muxing................................................................................................................. 63
Figure 9-5. Reset Sources......................................................................................................................................... 64
Figure 9-6. 8KREF Logic ........................................................................................................................................... 67
Figure 9-7. Performance Monitor Update Logic ........................................................................................................ 70
Figure 9-8. Transmit Error Insert Logic...................................................................................................................... 71
Figure 9-9. Loopback Modes ..................................................................................................................................... 72
Figure 9-10. ALB Mux ................................................................................................................................................ 72
Figure 9-11. AIS Signal Flow ..................................................................................................................................... 74
Figure 9-12. Framer Detailed Block Diagram ............................................................................................................ 79
8 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Figure 9-13. DS3 Frame Format................................................................................................................................ 81
Figure 9-14. DS3 Subframe Framer State Diagram .................................................................................................. 81
Figure 9-15. DS3 Multiframe Framer State Diagram................................................................................................. 82
Figure 9-16. G.751 E3 Frame Format ....................................................................................................................... 89
Figure 9-17. G.832 E3 Frame Format ....................................................................................................................... 92
Figure 9-18. MA Byte Format .................................................................................................................................... 92
Figure 9-19. HDLC Controller Block Diagram ........................................................................................................... 97
Figure 9-20. Trail Trace Controller Block Diagram .................................................................................................. 100
Figure 9-21. Trail Trace Byte (DT = Trail Trace Data)............................................................................................. 102
Figure 9-22. FEAC Controller Block Diagram.......................................................................................................... 103
Figure 9-23. FEAC Codeword Format.................................................................................................................... 104
Figure 9-24. Line Encoder/Decoder Block Diagram ................................................................................................ 105
Figure 9-25. B3ZS Signatures ................................................................................................................................. 107
Figure 9-26. HDB3 Signatures................................................................................................................................. 107
Figure 9-27. BERT Block Diagram .......................................................................................................................... 108
Figure 9-28. PRBS Synchronization State Diagram ................................................................................................ 110
Figure 9-29. Repetitive Pattern Synchronization State Diagram ............................................................................. 111
Figure 9-30. LIU Functional Diagram....................................................................................................................... 112
Figure 9-31. DS3/E3 LIU Block Diagram ................................................................................................................. 113
Figure 9-32. Receiver Jitter Tolerance .................................................................................................................... 116
Figure 12-1. JTAG Block Diagram........................................................................................................................... 202
Figure 12-2. JTAG TAP Controller State Machine .................................................................................................. 203
Figure 12-3. JTAG Functional Timing...................................................................................................................... 207
Figure 13-1. DS3170 Pin Assignments—100-Ball CSBGA (Top View) .................................................................. 212
Figure 13-2. DS3170 Pin Assignments—100-Pin LQFP ......................................................................................... 212
Figure 14-1. Mechanical Dimensions—100-Ball CSBGA........................................................................................ 213
Figure 14-2. Mechanical Dimensions—100-Pin LQFP ............................................................................................ 214
Figure 17-1. Clock Period and Duty Cycle Definitions............................................................................................. 218
Figure 17-2. Rise Time, Fall Time, and Jitter Definitions ........................................................................................ 218
Figure 17-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 218
Figure 17-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 219
Figure 17-5. To/From Hi Z Delay Definitions (Rising Clock Edge) .......................................................................... 219
Figure 17-6. To/From Hi Z Delay Definitions (Falling Clock Edge) ......................................................................... 219
Figure 17-7. SPI Interface Timing Diagram ............................................................................................................. 223
Figure 17-8. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 225
Figure 17-9. Micro Interface Multiplexed Read Cycle.............................................................................................. 226
Figure 17-10. DS3 Pulse Mask Template................................................................................................................ 228
Figure 17-11 E3 Waveform Template...................................................................................................................... 229
9 of 233
DS3170 DS3/E3 Single-Chip Transceiver
LIST OF TABLES
Table 4-1. Standards Compliance ............................................................................................................................. 16
Table 7-1. DS3170 Short Pin Descriptions ................................................................................................................ 25
Table 7-2. Detailed Pin Descriptions ......................................................................................................................... 27
Table 8-1. Configuration of Port Register Settings .................................................................................................... 52
Table 9-1. LIU Enable Table ...................................................................................................................................... 57
Table 9-2. All Possible Clock Sources Based on Mode and Loopback..................................................................... 57
Table 9-3. Source Selection of TLCLK Clock Signal ................................................................................................. 58
Table 9-4. Source Selection of TCLKO (Internal Tx Clock)....................................................................................... 59
Table 9-5. Source Selection of RCLKO Clock Signal (Internal Rx Clock)................................................................. 59
Table 9-6. Transmit Line Interface Signal Pin Valid Timing Source Select ............................................................... 60
Table 9-7. Transmit Framer Pin Signal Timing Source Select .................................................................................. 61
Table 9-8. Receive Line Interface Pin Signal Timing Source Select ......................................................................... 61
Table 9-9. Receive Framer Pin Signal Timing Source Select ................................................................................... 62
Table 9-10. Reset and Power-Down Sources ........................................................................................................... 65
Table 9-11. CLAD Clock Source Settings ................................................................................................................. 66
Table 9-12. Global 8 kHz Reference Source Table ................................................................................................... 67
Table 9-13. Port 8 kHz Reference Source Table....................................................................................................... 67
Table 9-14. GPIO Global Signals .............................................................................................................................. 68
Table 9-15. GPIO Pin Global Mode Select Bits......................................................................................................... 68
Table 9-16. GPIO Port Alarm Monitor Select ............................................................................................................ 69
Table 9-17. Loopback Mode Selections .................................................................................................................... 71
Table 9-18. Line AIS Enable Modes .......................................................................................................................... 75
Table 9-19. Payload (Downstream) AIS Enable Modes ............................................................................................ 75
Table 9-20. TSOFI Input Pin Functions ..................................................................................................................... 76
Table 9-21. TSOFO/TDEN/Output Pin Functions...................................................................................................... 76
Table 9-22 TCLKO/TGCLK Output Pin Functions ..................................................................................................... 76
Table 9-23. RSOFO/RDEN Output Pin Functions ..................................................................................................... 77
Table 9-24. RCLKO/RGCLK Output Pin Functions ................................................................................................... 77
Table 9-25. Framing Mode Select Bits FM[2:0] ......................................................................................................... 77
Table 9-26. Line Mode Select Bits LM[2:0]................................................................................................................ 78
Table 9-27. C-Bit DS3 Frame Overhead Bit Definitions ............................................................................................ 85
Table 9-28. M23 DS3 Frame Overhead Bit Definitions ............................................................................................. 87
Table 9-29. G.832 E3 Frame Overhead Bit Definitions ............................................................................................. 92
Table 9-30. Payload Label Match Status.................................................................................................................. 96
Table 9-31. Pseudo-Random Pattern Generation ................................................................................................... 109
Table 9-32. Repetitive Pattern Generation .............................................................................................................. 109
Table 9-33. Transformer Characteristics ................................................................................................................. 114
Table 9-34. Recommended Transformers............................................................................................................... 115
Table 10-1. Register Address Map .......................................................................................................................... 117
Table 11-1. Global Register Bit Map........................................................................................................................ 119
Table 11-2. Port Register Bit Map ........................................................................................................................... 119
Table 11-3. BERT Register Bit Map ........................................................................................................................ 120
Table 11-4. Line Register Bit Map .......................................................................................................................... 121
Table 11-5. HDLC Register Bit Map ........................................................................................................................ 121
Table 11-6. FEAC Register Bit Map ........................................................................................................................ 122
Table 11-7. Trail Trace Register Bit Map................................................................................................................. 123
Table 11-8. T3 Register Bit Map.............................................................................................................................. 123
Table 11-9. E3 G.751 Register Bit Map................................................................................................................... 124
Table 11-10. E3 G.832 Register Bit Map................................................................................................................. 125
Table 11-11. Global Register Map........................................................................................................................... 126
Table 11-12. Port Register Map............................................................................................................................... 133
Table 11-13. BERT Register Map............................................................................................................................ 144
Table 11-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 151
Table 11-15. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 152
Table 11-16. Transmit Side HDLC Register Map .................................................................................................... 156
Table 11-17. Receive Side HDLC Register Map ..................................................................................................... 159
Table 11-18. FEAC Transmit Side Register Map .................................................................................................... 163
10 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Table 11-19. FEAC Receive Side Register Map ..................................................................................................... 165
Table 11-20. Transmit Side Trail Trace Register Map............................................................................................. 168
Table 11-21. Trail Trace Receive Side Register Map.............................................................................................. 169
Table 11-22. Transmit DS3 Framer Register Map .................................................................................................. 174
Table 11-23. Receive DS3 Framer Register Map ................................................................................................... 176
Table 11-24. Transmit G.751 E3 Framer Register Map .......................................................................................... 183
Table 11-25. Receive G.751 E3 Framer Register Map ........................................................................................... 186
Table 11-26. Transmit G.832 E3 Framer Register Map .......................................................................................... 191
Table 11-27. Receive G.832 E3 Framer Register Map ........................................................................................... 194
Table 12-1. JTAG Instruction Codes ....................................................................................................................... 205
Table 12-2. JTAG ID Codes .................................................................................................................................... 206
Table 13-1. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Signal Name)............................................... 208
Table 13-2. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Pin #) ........................................................... 209
Table 13-3. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Signal Name)........................................... 210
Table 13-4. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Ball #) ...................................................... 211
Table 15-1. Thermal Information for 100-Pin CSBGA ............................................................................................. 215
Table 15-2. Thermal Information for 100-Pin LQFP ................................................................................................ 215
Table 16-1. Recommended DC Operating Conditions ............................................................................................ 216
Table 16-2. DC Electrical Characteristics ................................................................................................................ 216
Table 16-3. Output Pin Drive ................................................................................................................................... 217
Table 17-1. Framer Interface Timing ....................................................................................................................... 220
Table 17-2. System Port Interface Timing ............................................................................................................... 220
Table 17-3. Misc Timing .......................................................................................................................................... 221
Table 17-4. Overhead Port Timing .......................................................................................................................... 221
Table 17-5. SPI Bus Mode Timing........................................................................................................................... 222
Table 17-6. Micro Interface Timing .......................................................................................................................... 224
Table 17-7. DS3 Waveform Template ..................................................................................................................... 227
Table 17-8. DS3 Waveform Test Parameters and Limits ........................................................................................ 227
Table 17-9. E3 Waveform Test Parameters and Limits........................................................................................... 228
Table 17-10. Receiver Input Characteristics—DS3 Mode....................................................................................... 230
Table 17-11. Receiver Input Characteristics—E3 Mode ......................................................................................... 230
Table 17-12. Transmitter Output Characteristics—DS3 Modes .............................................................................. 231
Table 17-13. Transmitter Output Characteristics—E3 Mode................................................................................... 231
Table 17-14. JTAG Interface Timing........................................................................................................................ 232
11 of 233
2 APPLICATIONS
· Access Concentrators
· Multiservice Access Platforms
· ATM and Frame Relay Equipment
· Routers and Switches
· SONET/SDH ADM
· SONET/SDH Muxes
· PBXs
· Digital Cross Connect
· PDH Multiplexer/Demultiplexer
· Test Equipment
· Integrated Access Device (IAD)
Figure 2-1
Figure 2-1. DS3/E3 Line Card
show s a DS3170 application.
DS3170 DS3/E3 Single-Chip Transceiver
DS3/E3
Line
DS3/E3
Line
T3/E3 Line Card (#1)
T3/E3
Trans-
formers
DS3170
DS3/E3
SCT
T3/E3 Line Card (#n)
T3/E3
Trans-
formers
DS3170
DS3/E3
SCT
DS3/E3
Backplane
Signals
Digital Cross
Connect (DCS)
DS3/E3
Backplane
Signals
DS3/E3
Backplane
Singals
T3/E3 Line Card (#n+1)
DS3170
DS3/E3
SCT
T3/E3
Trans-
formers
T3/E3 Line Card (#n+n)
DS3170
DS3/E3
SCT
T3/E3
Trans-
formers
12 of 233
DS3170 DS3/E3 Single-Chip Transceiver
3 FEATURE DETAILS
The following sections describe the features provided by the DS3170 SCT.
3.1 Global Features
§ Supports the following transmission formats:
C-Bit DS3
M23 DS3
G.751 E3
G.832 E3
§ All controls and status fields are software accessible over either an 8/16-bit microprocessor port or a slave
serial bus communication port up to 10 Mbps (SPI)
§ On-chip clock rate adapter incorporates two separate internal PLLs to generate the necessary DS3 or E3 clock
used internally from an input clock reference (DS3, E3, 51.84 MHz, 77.76 MHz, or 19.44 MHz) and to provide
an output reference clock for external usage
§ Optional transmit loop timed clock mode using the receive clock
§ Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
§ Clock, data and control signals can be inverted to allow a glueless interface to other devices
§ Detection of loss of transmit clock and loss of receive clock
§ Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
§ Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
§ Automatic one-second, external or manual update of performance monitoring counters
§ Framing and line code error insertion available
3.2 Receive DS3/E3 LIU Features
§ Performs equalization, gain control, and clock and data recovery for incoming DS3 and E3 signals
§ AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
§ Interfaces directly to a DSX-3 monitor signal (20 dB flat loss) using built-in pre-amp
§ Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
§ Loss-of-lock status indication for internal phase-locked loop
3.3 Jitter Attenuator Features
§ Fully integrated, requires no external components
§ Standards-compliant jitter attenuation/jitter transfer
§ Can be inserted into the receive path or the transmit path
§ 16-bit buffer depth
3.4 Receive DS3/E3 Framer Features
§ B3ZS/HDB3 decoding
§ Frame synchronization for M23 and C-bit Parity DS3, G.751 E3 and G.832 E3
§ Detection of RAI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit, DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
§ Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
§ Manual or automatic one-second update of performance monitoring counters
§ The E3 national bit (Sn) is forwarded to a status register bit, the HDLC controller or the FEAC controller
§ HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit, or G.832
NR or GC channels
§ FEAC controller with four-codeword FIFO for DS3 FEAC channel
§ 16-byte Trail Trace Buffer compares and stores G.832 trail access point identifier
§ DS3 M23 C-bits configurable as payload or overhead, stored in registers for software inspection
§ Most framing overhead fields presented on the receive overhead port
§ Framer pass-through mode for clear-channel applications and externally defined frame formats
13 of 233
DS3170 DS3/E3 Single-Chip Transceiver
3.5 Transmit DS3/E3 Formatter Features
§ Frame insertion for M23 and C-bit parity DS3, G.751 E3 and G.832 E3
§ B3ZS/HDB3 encoding
§ Formatter pass-through mode for clear channel applications and externally defined frame formats
§ Generation of RAI, AIS, DS3 idle signal, and G.832-E3 RDI
§ Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors,
M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
§ The E3 national bit (Sn) can be sourced from a control register, from the HDLC controller, or from the FEAC
controller
§ Most framing overhead fields can be sourced from transmit overhead port
§ HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit, or G.832
NR or GC channels
§ FEAC controller for DS3 FEAC channel can be configured to send one codeword, one codeword continuously,
or two different codewords back-to-back to send DS3 Line Loopback commands
§ 16-byte Trail Trace Buffer sources the G.832 trail access point identifier
§ Insertion of G.832 payload type, and timing marker bits from registers
§ DS3 M23 C-bits configurable as payload or overhead; as overhead they can be controlled from registers or the
transmit overhead port
3.6 Transmit DS3/E3 LIU Features
§ Drives standards-compliant DS3 and E3 waveshapes onto 75W coaxial cable
§ Waveshape template compliance over all cable lengths without LBO adjustment
§ Tri-state line driver outputs support protection switching applications
§ Line driver monitor circuit and alarm output
§ Wide 50±20% transmit clock duty cycle
§ Line Build-Out (LBO) control
§ Output driver monitor
3.7 Clock Rate Adapter Features
§ Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input
reference clock
§ Input reference clock can be 77.76 MHz, 51.84 MHz, 44.736MHz, 34.368 MHz, or 19.44 MHz
§ Internally derived clock can be used as references for LIU and jitter attenuator
§ Derived clock can be transmitted off-chip for external system use through TCLKO pin
§ Standards-compliant jitter and wander requirements
3.8 HDLC Controller Features
§ Designed to handle multiple LAPD messages without Host intervention
§ 256 byte receive and transmit FIFOs are large enough to handle the three DS3 PMDL messages (Path ID, Idle
Signal ID, and Test Signal ID) that are sent and received once per second
§ Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
§ Programmable high or low water marks for the transmit and receive FIFOs
§ Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode or the G.751 Sn bit or the G.832 NR or
GC channels
3.9 FEAC Controller Features
§ Designed to handle multiple FEAC codewords without Host intervention
§ Receive FEAC automatically validates incoming codewords and stores them in a 4-codeword FIFO
§ Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different
codewords back-to-back to send DS3 Line Loopback commands
§ Terminates the FEAC channel in DS3 C-Bit Parity mode or the Sn bit in E3 mode
14 of 233
DS3170 DS3/E3 Single-Chip Transceiver
3.10 Trail Trace Buffer Features
§ Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
§ Insertion of the outgoing trail access point identifier from a 16-byte transmit register
§ Receive trace identifier unstable status indication
3.11 Bit Error-Rate Tester (BERT) Features
§ Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
§ Supports pattern insertion/extraction in DS3/E3 payload, or entire data stream
§ Large 24-bit error counter allows testing to proceed for long periods without host intervention
§ Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
§ Off-line monitoring on the Receive BERT
3.12 Loopback Features
§ LIU terminal loopback (transmit to receive) - ALB
§ Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - LLB
§ Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal toward
line/tributary interface - DLB
§ Simultaneous line facility loopback (LLB) and framer diagnostic loopback (DLB)
§ Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - PLB
3.13 Microprocessor Interface Features
§ Multiplexed or nonmultiplexed 8- or 16-bit control port
§ Intel and Motorola bus compatible
§ Global reset input pin
§ Global interrupt output pin
§ Eight programmable I/O pins (GPIOx)
3.14 Slave Serial Peripheral Interface (SPI) Features
§ Three-wire synchronous serial data link operating in full duplex slave mode up to 10 Mbps
§ Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260 and
microcontrollers such as M68HC11
§ Software provision ability for active phase of the serial clock (i.e. rising edge versus falling edge), bit ordering of
the serial data (most significant first versus least significant bit first)
3.15 Test Features
§ Five pin JTAG port
§ All functional pins are inout pins in JTAG mode
§ Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
§ Custom JTAG instructions to use RAM BIST
§ RAM BIST on all internal RAM
§ HIZ pin to force all digital output and inout pins into HIZ
§ TEST pin for manufacturing scan test modes
15 of 233
DS3170 DS3/E3 Single-Chip Transceiver
4 STANDARDS COMPLIANCE
Table 4-1. Standards Compliance
SPECIFICATION SPECIFICATION TITLE
ANSI
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
T1.646-1995
ATM Forum
af-phy-0034.000
af-phy-0054.000
ETSI
ETS 300 686
TBR 24
ETS EN 300 689
ETS 300 689
IETF
RFC 2496
ISO
ISO 3309:1993
ITU-T
G.703
G.704
G.751
G.775
G.823
G.824
G.832
I.432
O.151
Q.921
TELCORDIA
GR-499-CORE
GR-820-CORE
IEEE
IEEE Std 1149-
1990
Digital Hierarchy – Electrical Interfaces
Digital Hierarchy – Formats Specification
Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation – DS3 Metallic Interface Specification
Broadband ISDN – Physical Layer Specification for User-Network Interfaces Including
DS1/ATM
E3 Public UNI, August, 1995
DS3 Physical Layer Interface Specification, January, 1996
Business TeleCommunications; 34Mbps and 140Mbits/s digital leased lines (D34U, D34S,
D140U and D140S); Network interface presentation, 1996
Business TeleCommunications; 34Mbit/s digital unstructured and structured lease lines;
attachment requirements for terminal equipment interface, 1997
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications (BTC); 34 Mbps digital leased lines (D34U and D34S),
Terminal equipment interface, V 1.2.1, 2001-07
Definition of Managed Objects for the DS3/E3 Interface Type, January, 1999
Information Technology – Telecommunications & information exchange between systems –
High Level Data Link Control (HDLC) procedures – Frame structure, Fifth Edition, 1993
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Synchronous Frame Structures Used at 1544, 6312, 2048, 8488 and 44 736 kbit/s
Hierarchical Levels, July, 1995
Digital Multiplex Equipment Operating at the Third Order Bit Rate of 34,368 kbit/s and the
Fourth Order bit Rate of 139,264 kbit/s and Using Positive Justification, 1993
Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November, 1994
The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048
kbit/s Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Transport of SDH Elements on PDH Networks – Frame and Multiplexing Structures,
November, 1995
B-ISDN User-Network Interface – Physical Layer Specification, March, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October, 1992
ISDN User-Network Interface – Data Link Layer Specification, March 1993
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2,
December 1998
Generic Digital Transmission Surveillance, Issue 1, November 1994
IEEE Standard Test Access Port and Boundary-Scan Architecture, (Includes IEEE Std
1149-1993) October 21, 1993
16 of 233
DS3170 DS3/E3 Single-Chip Transceiver
5 ACRONYMS AND GLOSSARY
Definition of the terms used in this data sheet:
· CCM—Clear-Channel Mode
· CLAD—Clock Rate Adapter
· Clear Channel—A Datastream with no framing included, also known as Unframed
· FRM—Frame Mode
· FSCT—Framer Single-Chip Transceiver Mode
· HDLC—High-Level Data-Link Control
· Packet—HDLC Packet
· SCT—Single-Chip Transceiver (Framer and LIU)
· SCT Mode—DS3/E3 Framer and LIU
· Unchannelized—See Clear Channel
17 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6 MAJOR OPERATIONAL MODES
The major operational modes are determined by the FM[2:0] framer mode bits, as well as a few other control bits.
Unused features are powered down and the data paths are held in reset. The configuration registers of the unused
features can be written to and read from. Some of the IO pins change functions in different operational modes. The
line interface operational modes are determined by the LM[2:0] bits.
6.1 DS3/E3 Framed LIU Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
JA Off, B3ZS or HDB3 001 0 0
JA RX, B3ZS or HDB3 010 0 0
TLEN
PORT.CR2
JA TX, B3ZS or HDB3 011 0 0
JA Off, AMI 001 1 0
JA RX, AMI 010 1 0
JA TX, AMI 011 1 0
18 of 233
Figure 6-1. DS3/E3 Framed LIU Mode
TPOS/TDAT
TNEG
TLCLK
TXP
TXN
RPOS/RDAT
RNEG/RCLV
RLCLK
DS3/E3
Transmit
LIU
ALB
B3ZS/
HDB3
Encoder
LLB
TUA1
TAIS
DLB
FEAC
TOH
TOHEN
DS3 / E3
Transmit
Formatter
Trail
Trace
Buffer
TOHCLK
TOHSOF
HDLC
DS3170 DS3/E3 Single-Chip Transceiver
TCLKO/TGCLK
TSOFO/TDEN
TCLKI
TSER
TSOFI
TX
BERT
RX
PLB
BERT
RXP
RXN
DS3/E3
Receive
LIU
Clock Rate
Adapter
SPI
RST
REFCLK
Serial Interface Mode:
SPI (SCLK, MOSI, and MISO)
D[15:0]
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
ALE
A[8:1]
DS3 / E3
Receive
Framer
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
RDY
MODE
INT
WIDTH
GPIO[8:1]
ROH
ROHCLK
ROHSOF
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
JTDO
RSER
RCLKO/RGCLK
RSOFO/RDEN
19 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6.2 DS3/E3 Unframed LIU Mode
The frame mode determines the CLAD clock rate, LIU mode and selects B3ZS or HDB3.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
JA Off, B3ZS or HDB3 001 0 0
JA RX, B3ZS or HDB3 010 0 0
JA TX, B3ZS or HDB3 011 0 0
JA Off, AMI 001 1 0
JA RX, AMI 010 1 0
JA TX, AMI 011 1 0
Figure 6-2. DS3/E3 Unframed LIU Mode
TPOS
TNEG
TLCLK
TXP
TXN
RPOS
RNEG
RLCLK
RXP
RXN
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
TAIS
TUA1
TCLKO
TDEN
TCLKI
TSER
TX
BERT
DLB
PLB
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
INT
RDY
MODE
WIDTH
GPIO[8:1]
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
20 of 233
6.3 DS3/E3 Framed POS/NEG Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
LIU Off, B3ZS or HDB3 000 0 1
LIU Off, AMI 000 1 1
Figure 6-3. DS3/E3 Framed POS/NEG Mode
DS3170 DS3/E3 Single-Chip Transceiver
TPOS
TNEG
TLCLK
RPOS
RNEG
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inteface
SPI
RST
Serial Interface Mode:
(SCLK, MOSI, and MISO)
ALE
D[15:0]
A[8:1]
A[0]/BSWAP
TAIS
TUA1
DLB
CS
RD/DS
TOHCLK
TOH
TOHSOF
TOHEN
TCLKO/TGCLK
TSOFO/TDEN
DS3 / E3
Transmit
Formatter
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
Buffer
PLB
DS3 / E3
Receive
Framer
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
ROH
ROHCLK
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO/RGCLK
RSOFO/RDEN
JTDO
21 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6.4 DS3/E3 Unframed POS/NEG Mode
The frame mode determines the CLAD clock rate if used as the transmit clock and selects B3ZS or HDB3.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
LIU Off, B3ZS or HDB3 000 0 1
LIU Off, AMI 000 1 1
Figure 6-4. DS3/E3 Unframed POS/NEG Mode
TPOS
TNEG
TLCLK
RPOS
RNEG
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
Serial or Parallel
uP Inte face
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
A[0]/BSWAP
TAIS
TUA1
DLB
CS
RD/DS
TCLKO
TDEN
TCLKI
TSER
TX
BERT
RX
PLB
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
22 of 233
6.5 DS3/E3 Framed UNI Mode
FRAME MODE FM[2:0]
DS3 C-bit Framed 000
DS3 M23 Framed 001
E3 G.751 Framed 010
E3 G.832 Framed 011
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
Unipolar Mode 1XX X 1
Figure 6-5. DS3/E3 Framed UNI Mode
TOHCLK
TOH
TOHSOF
TOHEN
DS3170 DS3/E3 Single-Chip Transceiver
TDAT
TLCLK
RDAT
RLCV
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
LLB
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
TAIS
TUA1
DS3 / E3
Transmit
Formatter
TCLKO/TGC LK
TSOFO/TDE N
TCLKI
TSER
TSOFI
TX
BERT
Trail
FEAC
Trace
HDLC
DLB
Buffer
DS3 / E3
Receive
PLB
Framer
UA1
GEN
CS
RD/DS
WR/R/W
A[0]/BSWAP
RDY
MODE
WIDTH
INT
ROH
ROHCLK
GPIO[8:1]
ROHSOF
RX
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
JTDO
RSER
RCLKO/RGCLK
RSOFO/RDEN
23 of 233
DS3170 DS3/E3 Single-Chip Transceiver
6.6 DS3/E3 Unframed UNI Mode
The frame mode determines the CLAD clock rate if used as the transmit clock.
FRAME MODE FM[2:0]
DS3 Unframed 100
E3 Unframed 110
LIU MODE LM[2:0] TZSD & RZSD
TLEN
PORT.CR2
Unipolar Mode 1XX X 1
Figure 6-6. DS3/E3 Unframed UNI Mode
TAIS
TUA1
TDAT
TLCLK
TX
BERT
TCLKO
TDEN
TCLKI
TSER
RDAT
RLCV
RLCLK
ALB
Clock Rate
Adapter
REFCLK
SPI
LLB
Serial or Parallel
uP Inteface
SPI
RST
ALE
D[15:0]
A[8:1]
Serial Interface Mode:
(SCLK, MOSI, and MISO)
A[0]/BSWAP
CS
DLB
RD/DS
RX
PLB
UA1
GEN
INT
RDY
MODE
WIDTH
WR/R/W
GPIO[8:1]
BERT
IEEE P1149.1
JTAG Test
Access Port
JTDI
JTMS
JTRST
JTCLK
RSER
RCLKO
RDEN
JTDO
24 of 233
DS3170 DS3/E3 Single-Chip Transceiver
7 PIN DESCRIPTIONS
Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for
isolation of interconnect failures.
7.1 Short Pin Descriptions
Table 7-1. DS3170 Short Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional in/out)
NAME TYPE FUNCTION
Line IO
TLCLK O Transmit Line Clock Output
TPOS / TDAT O Transmit Positive AMI / Data E9 67
TNEG O Transmit Negative AMI D9 70
TXP Oa Transmit Positive analog E1, E2 12, 13
TXN Oa Transmit Negative analog F1, F2 16, 17
RLCLK I Receive Clock Input A8 81
RXP Ia Receive Positive analog A4 94
RXN Ia Receive Negative analog A3 97
RPOS / RDAT Ia Positive AMI / Data F10 62
RNEG / RLCV Ia Negative AMI / Line Code Violation F9 63
DS3/E3 Overhead Interface
TOH I Transmit Overhead C7 83
TOHEN I Transmit Overhead Enable E10 66
TOHCLK O Transmit Overhead Clock D7 82
TOHSOF O Transmit Overhead Start Of Frame G9 60
ROH O Receive Overhead B6 88
ROHCLK O Receive Overhead Clock C9 73
ROHSOF O Receive Overhead Start Of Frame F8 61
DS3/E3 Serial Data DS3/E3 Overhead Interface
TCLKI I Transmit Line Clock Input C10 72
TSOFI I Transmit Start Of Frame Input A9 78
TSER I Transmit Serial Data B10 75
TCLKO / TGCLK O Transmit Clock Output / Gapped Clock B9 77
TSOFO / TDEN O Transmit Framer Start Of Frame / Data Enable C8 79
RSER O Receive Serial Data C6 86
RCLKO / RGCLK O Receive / Clock Output / Gapped Clock A6 87
RSOFO / RDEN O Receive Framer Start Of Frame / Data Enable B8 80
Microprocessor Interface
D[15] IO Data [15] G8 58
D[14] IO Data [14] H10 56
D[13] IO Data [13] H9 55
D[12] IO Data [12] H8 54
D[11] IO Data [11] J10 53
D[10] IO Data [10] J9 52
D[9] IO Data [9] G6 40
D[8] IO Data [8] J8 48
D[7]/SPI_CPOL IO Data [7] / SPI Interface Clock Polarity K8 47
D[6]/SPI_CPHA IO Data [6] / SPI Interface Clock Phase H7 46
D[5]/SPI_SWAP IO Data [5:3] / SPI Bit Order Swap J7 45
D[4] IO Data [4] K7 44
D[3] IO Data [3] H6 43
BGA LQFP
B7 85
PIN
25 of 233
DS3170 DS3/E3 Single-Chip Transceiver
NAME TYPE FUNCTION
BGA LQFP
PIN
D[2]/SPI_SCLK IO Data [2] / SPI Serial Interface Clock < 10 MHz J6 42
D[1]/SPI_MOSI IO Data [1] / SPI Serial Interface Data Master-out
Slave-in
D[0]SPI_MISO IO Data [0] / SPI Serial Interface Data Master-in
Slave-out
A[8]
I Address [8:1] H5
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
K9 50
J5 38
36
J4
H4
K3
J3
H3
K2
J2
35
33
31
30
29
28
27
A[0]/BSWAP Address [0] / Byte Swap mode K5 37
ALE I Address Latch Enable G4 32
CS
RD/DS
WR / R/W
RDY
INT
I Chip Select (active low)
I Read Strobe (active low) / Data Strobe (active
low)
I Write Strobe (active low) / R/W Select
Oz Ready Handshake (active low)
O Interrupt (open drain active low)
A1 1
B2 2
C2 5
J1 25
D8 71
MODE I Mode Select (RD/WR or DS strobe mode) F3 18
WIDTH I Width Select (8 or 16 bit interface) H2 23
SPI I SPI Serial bus mode C3 4
Misc I/O
GPIO[8]
GPIO[7]
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
TEST
HIZ
RST
IO General Purpose IO [8:1] D4
D3
G5
F6
G7
F7
E7
E8
I Test enable (active low)
I High impedance test enable (active low)
I Reset (active low)
F5 24
B4 95
E6 74
7
8
39
49
57
64
65
68
JTAG
JTCLK I JTAG Clock A5 91
JTMS Ipu JTAG Mode Select (with pullup) B3 98
JTDI Ipu JTAG Data Input (with pullup) C4 96
JTDO Oz JTAG Data Output D5 90
JTRST
Ipu JTAG Reset (active low with pullup)
E5 99
CLAD
REFCLK I Reference Clock H1 22
POWER
VSS PWR Ground, 0 Volt potential C1, K1, K6,
G10, A10,
A2
VDD PWR Digital 3.3V B1, D1, K4,
K10, D10,
A7
6, 26, 41,
59, 76, 100
3, 9, 34, 51,
69, 84
AVDDR PWR Analog 3.3V for Receive LIU C5 93
AVDDT PWR Analog 3.3V for Transmit LIU F4 15
AVDDJ PWR Analog 3.3V for Jitter Attenuator E3 11
AVDDC PWR Analog 3.3V for CLAD G3 21
26 of 233
DS3170 DS3/E3 Single-Chip Transceiver
NAME TYPE FUNCTION
BGA LQFP
PIN
AVSSR PWR Analog Gnd for Receive LIU B5 92
AVSST PWR Analog Gnd for Transmit LIU E4 14
AVSSJ PWR Analog Gnd for Jitter Attenuator D2 10
AVSSC PWR Analog Gnd for CLAD G1 19
UNUSED
UNUSED1 N/A Unused D6 89
UNUSED2 N/A Unused G2 20
7.2 Detailed Pin Descriptions
Table 7-2. Detailed Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional inout)
PIN NAME TYPE PIN DESCRIPTION
Line IO
TLCLK O Transmit Line Clock Output
TLCLK: This signal is available when the transmit line interface pins are enabled
TLEN). This clock is typically used as the clock reference for the TDAT
20 ppm
20 ppm
TLEN), a high on this pin
TLEN), the un-encoded transmit signal is
20ppm
20ppm
TPOS /
TDAT
(PORT.CR2.
and TNEG signals, but can also be used as the reference for the TSOFI, TSER, and
TSOFO / TDEN signals.
This output signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
O Transmit Positive AMI / Data Output
TPOS: When the port line interface is configured for B3ZS, HDB3 or AMI mode and
the transmit line interface pins are enabled (PORT.CR2.
indicates that a positive pulse should be transmitted on the line. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TLCLK line clock output pins, but it can be referenced to the
TCLKO, TCLKI, RLCLK or RCLKO pins. This output signal can be disabled when the
TX LIU is enabled.
This output signal can be inverted.
TDAT: When the port line interface is configured for UNI mode and the transmit line
interface pins are enabled (PORT.CR2.
output on this pin. The signal is updated on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the TLCLK line clock output
pins, but it can be referenced to the TCLKO, TCLKI, RLCLK or RCLKO pins
This output signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
27 of 233
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
TNEG O Transmit Negative AMI / Line OH Mask
TNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the
transmit line interface pins are enabled (PORT.CR2.
indicates that a negative pulse should be transmitted on the line. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLK line clock output pins, but it can be referenced to
the TCLKO, TCLKI, RLCLK or RCLKO pins.
This output signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
TXP Oa Transmit Positive Analog
TXP: This pin and the TXN pin form a differential AMI output which is coupled to the
outbound 75W coaxial cable through a 2:1 step-down transformer (Figure 1-1
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
TXN Oa Transmit Negative Analog
TXN: This pin and the TXP pin form a differential AMI output which is coupled to the
outbound 75W coaxial cable through a 2:1 step-down transformer (Figure 1-1
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RXP Ia Receive Positive analog
RXP: This pin and the RXN pin form a differential AMI input which is coupled to the
outbound 75W coaxial cable through a 2:1 step-up transformer (Figure 1-1
is used when the RX LIU is enabled and is ignored when the LIU is disabled.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RXN Ia Receive Negative analog
RXN: This pin and the RXP pin form a differential AMI input which is coupled to the
outbound 75W coaxial cable through a 2:1 step-up transformer (Figure 1-1
is used when the LIU is enabled and is ignored when the LIU is disabled.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RLCLK I Receive Line Clock Input
RLCLK: This clock is typically used for the reference clock for the RPOS / RDAT,
RNEG / RLCV signals but can also be used as the reference clock for the RSER,
RSOFO / RDEN, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.
This input is ignored when the LIU is enabled.
This input signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
20 ppm
20 ppm
TLEN), a high on this pin
). This
). This
). This input
). This input
28 of 233
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
RPOS /
RDAT
Iad Receive Positive AMI / Data
RPOS: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
disabled, a high on this pin indicates that a positive pulse has been detected using an
external LIU. The signal is sampled on the positive clock edge of the referenced clock
pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of
the clock. The signal is typically referenced to the RLCLK line clock input pins, but it
can be referenced to the RCLKO output pins.
This input signal can be inverted.
RDAT: When the port line interface is configured for UNI mode, the un-encoded
receive signal is input on this pin. The signal is sampled on the positive clock edge of
the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled
on the falling edge of the clock. The signal is typically referenced to the RLCLK line
clock input pins, but it can be referenced to the RCLK output pins.
This input signal can be inverted.
RNEG /
RLCV
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
Iad Receive Negative AMI / Line Code Violation / Line OH Mask input
RNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
20ppm
20ppm
disabled, a high on this pin indicates that a negative pulse has been detected using
an external LIU. The signal is sampled on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling
edge of the clock. The signal is typically referenced to the RLCLK line clock input
pins, but it can be referenced to the RCLKO output pins.
This input signal can be inverted.
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
20ppm
20ppm
RLCV: When the port line interface is configured for UNI mode, the BPV counter in
the encoder/decoder block is incremented each clock when this signal is high. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock
pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The
signal is typically referenced to the RLCLK line clock input pins, but it can be
referenced to the RCLKO output pins.
This input signal can be inverted.
DS3/E3 Overhead Interface
TOH I Transmit Overhead
TOH: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used to over-write the DS3 or E3 framing overhead bits when
TOHEN is active. In T3 mode, the X-bits, P-bits, M-bits, F-bits, and C-bits are input. In
G.751 E3 mode, all of the FAS, RAI, and National Use bits are input. In G.832 E3
mode, all of the FA1, FA2, EM, TR, MA, NR, and GC bytes are input. The TOHSOF
signal marks the start of the framing bit sequence. This signal is sampled at the same
time as the TOHCLK signal transitions high to low.
This signal can be inverted.
TOHEN I Transmit Overhead Enable / Start Of Frame Input
TOHEN: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used the determine which DS3 or E3 framing overhead bits to overwrite with the signal on the TOH pin. The TOHSOF signal marks the start of the
framing bit sequence. This signal is sampled at the same time as the TOHCLK signal
transitions high to low.
This signal can be inverted.
29 of 233
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
TOHCLK O Transmit Overhead Clock
TOHCLK: When the port framer is configured for one of the DS3 or E3 framing
modes, this clock is used for the transmit overhead port signals TOH, TOHEN and
TOHSOF. The TOHSOF output signal is updated and the TOH and TOHEN input
signals are sampled at the same time this clock signal transitions from high to low.
The external logic is expected to sample TOHSOF signal and update the TOH and
TOHEN signals on the rising edge of this clock signal. This clock is a low frequency
clock.
This signal can be inverted.
TOHSOF O Transmit Overhead Start Of Frame
TOHSOF: When the port framer is configured for one of the DS3 or E3 framing
modes, this signal is used to mark the start of a DS3 or E3 overhead sequence on the
TOH pin. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the
FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The
sequence starts on the same high to low transition of the TOHCLK clock that this
signal is high. This signal is updated at the same time as the TOHCLK signal
transitions high to low.
This signal can be inverted.
ROH O Receive Overhead
ROH: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal outputs the value of the receive overhead bits. The ROHSOF signal marks
the start of the framing bit sequence. In T3 mode, the X-bits, P-bits, M-bits, F-bits,
and C-bits are output (Note: In M23 mode, the C-bits are extracted even though they
are marked as data at the payload interface). In G.751 E3 mode, all of the FAS, RAI,
and National Use bits are output. In G.832 E3 mode, all of the FA1, FA2, EM, TR,
MA, NR, and GC bytes are output.
This signal is updated at the same time as the ROHCLK signal transitions high to low.
This signal can be inverted.
ROHCLK O Receive Overhead Clock
ROHCLK: When the port framer is configured for one of the DS3 or E3 framing
modes, this clock is used for the receive overhead port signals ROH and ROHSOF.
The ROHSOF and ROH output signals are updated at the same time this clock signal
transitions from high to low. The external logic is expected to sample ROHSOF and
ROH signal on the rising edge of this clock signal. This clock is a low frequency clock.
This signal can be inverted.
ROHSOF O Receive Overhead Start Of Frame
ROHSOF: When the port framer is configured for one of the DS3 or E3 framing
modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the
ROH pins. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the
FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The
sequence starts on the same high to low transition of the ROHCLK clock that this
signal is high. This signal is updated at the same time as the ROHCLK signal
transitions high to low.
This signal can be inverted.
DS3/E3 Serial Data Overhead Interface
TCLKI I Transmit Line Clock Input
TCLKI: This clock is typically used for the reference clock for the TSOFI, TSER, and
TSOFO / TDEN signals but can also be used as the reference for the TPOS / TDAT
and TNEG signals. This clock is not used when the part is in loop time mode or the
CLAD clocks are used as the transmit clock source. (PORT.CR3.CLADC)
This input signal can be inverted.
o DS3: 44.736 MHz +20 ppm
o E3: 34.368 MHz +
20 ppm
30 of 233
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
TSOFI I Transmit Start Of Frame Input
See Table 9-20
.
TSOFI: This signal can be used to align the start of the DS3 or E3 frames on the
TSER pin to an external signal. In framed modes, the TSOFI signal can be used to
align the start of frame signal position on the TSER/TOH pin to the rising edge of a
signal on this pin. The signal edge does not need to occur on every frame and can be
tied high or low. The signal is sampled on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling
edge of the clock. The signal is typically referenced to the TCLKI transmit clock input
pins, but it can be referenced to the TLCLK, TCLKO, RCLKO and RLCLK clock pins.
This signal can be inverted.
TSER I Transmit Serial Data
TSER: When the port framer is configured for either the DS3 or E3 framed modes,
this pin is used as the source of the DS3/E3 payload data. When the port is
configured for a clear channel mode, this pin is used as the source of the DS3/E3
data signal. The signal is sampled on the positive clock edge of the referenced clock
pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of
the clock. The signal is typically referenced to the TCLKI transmit clock input pins, but
it can be referenced to the TLCLK, TCLKO / TGCLK, RCLKO and RLCLK clock pins
This signal can be inverted.
TCLKO /
TGCLK
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
O Transmit Clock Output / Gapped Clock
See Table 9-22
.
20ppm
20ppm
TCLKO: When TCLKO is selected by PORT.CR3
enabled. This clock is the same clock as the internal framer transmit clock. This clock
is typically used for the reference clock for the TSOFI, TSER, and TSOFO / TDEN
signals but can also be used as the reference for the TPOS / TDAT and TNEG
signals.
This signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
20 ppm
20 ppm
TGCLK: When TGCLK is selected by PORT.CR3
enabled. This gapped clock is the same clock as the internal framer transmit clock
and is gated by TDEN. This clock is typically used for the reference clock for the
TSER signal.
This signal can be inverted.
.TCLKS, this clock output is
.TCLKS, this gated output clock is
31 of 233
DS3170 DS3/E3 Single-Chip Transceiver
p
PIN NAME TYPE PIN DESCRIPTION
TSOFO /
TDEN
O Framer Start Of Frame / Data Enable
See Table 9-21
.
TSOFO: When the port framer is configured for the DS3 or E3 framed modes and the
TSOFO pin function is selected, this signal is used to indicate the start of the DS3/E3
frame on the TSER pin. This signal pulses high three clocks before the first overhead
bit in a DS3 or E3 frame that will be input on TSER. The signal is updated on the
positive clock edge of the referenced clock pin if the clock pin signal is not inverted,
otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TCLKI transmit clock input pins, but it can be referenced to the
TLCLK, TCLKO, RCLKO and RLCLK clock pins.
This signal can be inverted.
TDEN: When the port framer is configured for the DS3 or E3 framed modes and the
TDEN pin function is selected, this signal is used to mark the DS3/E3 frame bits on
the TSER pin. The signal goes high three clocks before the start of DS3/E3 payload
bits and goes low three clocks before the end of the DS3/E3 payload bits. The signal
is updated on the positive clock edge of the referenced clock pin if the clock pin signal
is not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TCLKI transmit clock input pins, but it can be referenced to
the TLCLK, TCLKO, RCLKO and RLCLK clock pins.
This signal can be inverted.
RSER O Receive Serial Data
RSER: When the port framer is configured for the DS3 or E3 framed modes, this pin
outputs the receive data signal from the LIU or receive line pins. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the RCLKO receive clock output pin, but it can be referenced to the
RGCLK and RLCLK clock pins.
This signal can be inverted
RCLKO /
RGCLK
o DS3: 44.736 Mbps +
o E3: 34.368 Mbps +
O Receive Clock Output / Gapped Clock
See Table 9-24
.
20ppm
20ppm
RCLKO: When the port framer is configured for the DS3 or E3 framed modes and
RCLKO is selected, this clock output signal is active. It is the same as the internal
receive framer clock. This clock is typically used for the reference clock for the RSER,
RSOFO / RDEN signals but can also be used as the reference for the RPOS / RDAT,
RNEG / RLCV, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.
This signal can be inverted.
o DS3: 44.736 MHz +
o E3: 34.368 MHz +
20 ppm
20 ppm
RGCLK: When the port is configured for DS3/E3 framed mode and RGCLK is
selected, this gated clock output signal is active. It is the same as the internal receive
framer clock gated by RDEN. This clock is typically used for the reference clock for
the RSER.
This signal can be inverted
RSOFO /
RDEN
O Receive Framer Start Of Frame /Data Enable
See Table 9-23
.
RSOFO: When the port framer is configured for the DS3 or E3 framed modes and the
RSOFO pin function is enabled, this signal is used to indicate the start of the DS3/E3
frame. This signal indicates the first DS3/E3 overhead bit on the RSER pin when high.
The signal is updated on the positive clock edge of the referenced clock pin if the
clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock.
The signal is typically referenced to the RCLKO receive clock output pin, but it can be
referenced to the RLCLK clock input pin.
This signal can be inverted.
RDEN: When the port framer is configured for the DS3 or E3 framed modes and the
RDEN
in function is enabled, this signal is used to indicate the DS3/E3 payload bit
32 of 233
DS3170 DS3/E3 Single-Chip Transceiver
g
PIN NAME TYPE PIN DESCRIPTION
positions of the data on the RSER pin. The signal goes high during each DS3/E3
payload bit and goes low during each DS3/E3 overhead bit. The signal is updated on
the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the RCLKO receive clock output pin, but it can be referenced to the
RLCLK clock input pin.
This signal can be inverted.
Microprocessor Interface
D[15:8] IO Upper 8 Bits of the Bi-directional 16 or 8 bit data bus
D[15:8]: Upper bits of the 16-bit or 8-bit data bus used to input data during register
writes, and data outputs during register reads. The upper 8 bits are not used in 8 bit
D[7]/
SPI_CPOL
bus mode. Not driven when
IO Bit 7 of Bi-directional data bus / SPI Bus Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes, and
CS=1 or RST=0.
data outputs during register reads. Not driven when
SPI_CPOL: This signal selects the clock polarity when SPI = 1. See Section 7.3.4.1
for detailed timing and functionality information. Default setting is low.
D[6]/
SPI_CPHA
IO Bit 6 of Bi-directional data bus / SPI Bus Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when
SPI_CPHA: This signal selects the clock phase when SPI = 1. See Section 7.3.4.1 for
detailed timing and functionality information. Default setting is low.
D[5]/
SPI_SWAP
IO Bit 5 of Bi-directional data bus / SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when
SPI_SWAP: This signal is active when SPI=1. The address and data bit order is
swapped when SPI_SWAP is high. The R/W and B bit positions are never changed in
the control word.
0 = MSB is transmitted and received first.
1 = LSB is transmitted and received first.
D[4:3] IO Bits 4,3 of Bi-directional data bus
D[4:3]: Bits 3,4 of the 16-bit or 8-bit data bus used to input data during register writes,
and data outputs during register reads. Not driven when
D[2]/
SPI_SCLK
IO Bit 2 of Bi-directional data bus / SPI Serial Clock Input < 10 MHz
D[2]: Bit 2 of the 16-bit or 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when
SPI_SCLK: SPI Serial Clock Input when SPI = 1.
D[1]/
SPI_MOSI
IO Bit 1 of Bi-directional data bus / SPI Serial Bus Master-out Slave-in
D[1]: Bit 1 of the 16-bit or 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when
SPI_MOSI: SPI Serial Data Input (Master-out Slave-in) when SPI = 1.
D[0]/
SPI_MISO
IO Bit 0 of Bi-directional data bus / SPI Serial Bus Master-in Slave-out
D[0]: Bit 0 of the 16-bit or 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when
SPI_MISO: SPI Serial Data Output (Master-in Slave-Out) when SPI = 1.
A[8:1] I Address bus (minus LSB) / Device Address [8:1]
A[8:1]: identifies the specific 16 bit registers, or group of 8 bit registers, being
accessed.
A[0] /
BSWAP
Address bus LSB / Byte Swap / Device Address [0]
A[0]: This signal is connected to the lower address bit in 8 bit systems. (WIDTH=0)
1 = Output register bits 15:8 on D[7:0], D[15:8] not driven
0 = Output register bits 7:0 on D[7:0], D[15:8] not driven
BSWAP: This signal is tied high or low in 16 bit systems. (WIDTH=1)
1 = Output register bits 15:8 on D[7:0], 7:0 on D[15:8]
0 = Output register bits 7:0 on D[7:0], 15:8 on D[15:8]
ALE I Address Latch Enable
ALE: This si
33 of 233
nal is used to latch the address on the A[10:0] pins in multiplexed
CS=1 or RST=0.
CS=1 or RST=0.
CS=1 or RST=0.
CS=1 or RST=0.
CS=1 or RST=0.
CS=1 or RST=0.
CS=1 or RST=0.
PIN NAME TYPE PIN DESCRIPTION
address systems. When it is high the address is fed through the address latch to the
internal logic. When it transitions to low, the address is latched and held internally
until the signal goes back high. ALE should be tied high for nonmultiplexed address
systems.
CS
I Chip Select (active low)
CS: This signal must be low during all accesses to the registers
RD /
DS
I Read Strobe (active low) / Data Strobe (active low)
RD: Read Strobe mode (MODE=0):
RD is low during a register read.
DS: Data Strobe mode (MODE=1):
DS is low during either a register read or a write.
WR /
R/
W
I Write Strobe (active low) / R/W Select
WR: Write Strobe mode (MODE=0):
WR is low during a register write.
W: Data Strobe mode (MODE=1):
R/
R/
W is high during a register read cycle, and low during a register write cycle.
RDY
Oz Ready handshake (active low)
RDY: This ready signal is driven low when the current read or write cycle can
progress. When the current read or write cycle is not ready it is driven high. When
device is not selected it is not driven. Not driven when
INT
Oz Interrupt (active low)
INT: This interrupt signal is driven low when an event is detected on any of the
enabled interrupt sources in any of the register banks. When there are no active and
enabled interrupt sources, the pin can be programmed to either drive high or not drive
high. The reset default is to not drive high when there are no active and enabled
interrupt source. All interrupt sources are disabled when
programmed to be enabled.
Not driven when
MODE I
Mode select
RST=0.
RD/WR or DS strobe mode
MODE: 1 = Data Strobe Mode, 0 = Read/Write Strobe Mode
WIDTH I Data bus width select 8 or 16-bit interface
WIDTH: 1 = 16-bits, 0 = 8 bits
SPI I SPI Serial Bus Mode Select
SPI: 1 = SPI Serial Bus Mode, 0 = Parallel Bus Mode
Misc I/O
GPIO1 IO General Purpose IO 1
GPIO1: This signal is configured to be a general purpose IO pin, or an alarm output
signal.
GPIO2 IO General Purpose IO 2
GPIO2: This signal is configured to be a general purpose IO pin, or the 8KREFO
output signal, or an alarm output signal.
GPIO3 IO General Purpose IO 3
GPIO3: This signal is configured to be a general purpose IO pin.
GPIO4 IO General Purpose IO 4
GPIO4: This signal is configured to be a general purpose IO pin, or the 8KREFI input
signal. When configured for 8KREFI mode the signal frequency should be 8,000 Hz
+/- 500 ppm and about 50% duty cycle.
GPIO5 IO General Purpose IO 5
GPIO5: This signal is configured to be a general purpose IO pin, or an alarm output
signal.
GPIO6 IO General Purpose IO 6
GPIO6: This signal is configured to be a general purpose IO pin, or the TMEI input
signal. When configured for TMEI input, the signal low time and high time must be
greater than 500 nsec.
GPIO7 IO General Purpose IO 7
34 of 233
DS3170 DS3/E3 Single-Chip Transceiver
RST=0 or CS=1.
RST =0 and they must be
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
GPIO7: This signal is configured to be a general purpose IO pin.
GPIO8 IO General Purpose IO 8
GPIO8: This signal is configured to be a general purpose IO pin, or the PMU input
signal. When configured for PMU input, the signal low time and high time must be
greater than 500 nsec.
TEST
I Test enable (active low)
TEST: This signal enables the internal scan test mode when low. For normal operation
tie high. This is an asynchronous input.
HIZ
I High impedance test enable (active low)
HIZ: This signal puts all digital output and bi-directional pins in the high impedance
state when it low and
JTRST is low. For normal operation tie high. This is an
asynchronous input.
RST
I Reset (active low)
RST: This signal resets all the internal processor registers and logic when low. This
pin should be low while power is applied and set high after the power is stable. This
is an asynchronous input.
JTAG
JTCLK I JTAG Clock
JTCLK: This clock input is typically a low frequency (less than 10 MHz) 50% duty
cycle clock signal.
JTMS Ipu JTAG Mode Select (with pullup)
JTMS: This input signal is used to control the JTAG controller state machine and is
sampled on the rising edge of JTCLK.
JTDI Ipu JTAG Data Input (with pullup)
JTDI: This input signal is used to input data into the register that is enabled by the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTDO Oz JTAG Data Output
JTDO: This output signal is the output of an internal scan shift register enabled by the
JTAG controller state machine and is updated on the falling edge of JTCLK. The pin
is in the high impedance mode when a register is not selected or when the
signal is high. The pin goes into and exits the high impedance mode after the falling
edge of JTCLK
JTRST
Ipu JTAG Reset (active low with pullup)
JTRST: This input forces the JTAG controller logic into the reset state and forces the
JTDO pin into high impedance when low. This pin should be low while power is
applied and set high after the power is stable. The pin can be driven high or low for
normal operation, but must be high for JTAG operation.
JTRST
CLAD
REFCLK I Reference Clock
CLKI: This pin must have a clock which is either 44.736 MHz, 34.368 MHz, 77.76
MHz, 51.84 MHz or 19.44 MHz +/- 20 ppm and transmission quality jitter and wander.
No IO pins have a timing relationship to this pin.
POWER
VSS
VDD
AVDDR
AVDDT
AVDDJ
AVDDC
35 of 233
PWR
PWR
PWR
PWR
PWR
PWR
Ground, 0 Volt potential
Common to digital core, digital IO and all analog circuits
Digital 3.3V
Common to digital core and digital IO
Analog 3.3V for receive LIU
Powers receive LIU
Analog 3.3V for transmit LIU
Powers transmit LIU
Analog 3.3V for jitter attenuator
Powers jitter attenuator
Analog 3.3V for CLAD
Powers clock rate adapter
DS3170 DS3/E3 Single-Chip Transceiver
PIN NAME TYPE PIN DESCRIPTION
AVSSR PWR Analog Ground for receive LIU
AVSST PWR Analog Ground for transmit LIU
AVSSJ PWR Analog Ground for jitter attenuator
AVSSC PWR Analog Ground for CLAD
36 of 233
DS3170 DS3/E3 Single-Chip Transceiver
7.3 Pin Functional Timing
7.3.1 Line IO
7.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing
There is no suggested time alignment between the TXP, TXN and TX LINE signals and the TLCLK clock signal.
The TX DATA signal is not a readily available signal, it is meant to represent the data value of the other signals.
The TXP and TXN signals are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is enabled.
The TPOS, TNEG and TLCLK signals are only available when the line is in B3ZS/HDB3 or AMI mode and the
transmit line pins are enabled. The TPOS, TNEG and TLCLK pins can be enabled at the same as the LIU is
enabled.
The TPOS and TNEG signals change a small delay after the positive edge of the reference clock if the clock pin is
not inverted, otherwise they change after the negative edge. The TLCLK clock pin is the clock reference typically
used for the TPOS and TNEG signals, but they can be time referenced to the TCLKI, TCLKO, RLCLK or RCLKO
clock pins. The TPOS and TNEG pins can be inverted, but the polarity of TXP and TXN can not be inverted.
TXP and TXN are differential analog output pins. They are biased around ½ VDD and pulse above and below the
bias voltage by about 1 Volt. These signals are connected to the windings of a 1:2 step down transformer and the
other winding of the transformer creates the TX LINE signal. The TX LINE signal is a bipolar signal that pulses
about 1 Volt positive and 1 Volt negative above and below ground (0 volts). See Figure 1-1
external connections.
for a diagram of the
Figure 7-1
and Figure 7-2 show the relationship between the analog and the digital outputs.
Figure 7-1. Tx Line IO B3ZS Functional Timing Diagram
TLCLK
(TX DATA)
TPOS
TNEG
TXP
TXN
(TX LINE)
BIAS V
0 V
B
BV
B
+
-
B
V
V
V
B3ZS CODEWORD
37 of 233
Figure 7-2. Tx Line IO HDB3 Functional Timing Diagram
TLCLK
(TX DATA)
TPOS
DS3170 DS3/E3 Single-Chip Transceiver
TNEG
TXP
TXN
(TX LINE)
BIAS V
0 V
B
BV
B
+
-
BV
V
V
HDB3 CODEWORD
7.3.1.2 B3ZS/HDB3/AMI Mode Receive Pin Functional Timing
There is no suggested time alignment between the RXP, RXN and RX LINE signals and the RLCLK clock signal.
The RX DATA signal is not an always readily available signal, it is meant to represent the data value of the other
signals. The signal on RSER in framed mode will be the same as the RX DATA signal except delayed.
The RXP and RXN pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is enabled.
The RPOS, RNEG and RLCLK pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is
disabled.
The RPOS and RNEG signals are sampled at the rising edge of the reference clock signal if the clock pin is not
inverted, otherwise they are sampled at the negative edge. The RLCLK clock pin is the clock reference used for the
RPOS and RNEG signals. The RPOS and RNEG pins can be inverted.
RXP and RXN are differential analog input pins. They are biased around ½ VDD and pulse above and below the
bias voltage by about 1 Volt with zero cable length. These signals are connected to the windings of a 1:2 step up
transformer and the other winding of the transformer is connected to the RX LINE signal. The RX LINE signal is a
bipolar signal that pulses about 1 Volt positive and 1 Volt negative above and below ground (0 volts) with zero
cable length. See Figure 1-1
for a diagram of the external connections.
Figure 7-3
and Figure 7-4 show the relationship between the analog and the digital outputs.
Figure 7-3. Rx Line IO B3ZS Functional Timing Diagram
RLCLK
(RX DATA)
RPOS
RNEG
RXP
RXN
(RX LINE)
BIAS V
0 V
+
-
B
BV
B
B
38 of 233
V
V
V
B3ZS CODEWORD
Figure 7-4. Rx Line IO HDB3 Functional Timing Diagram
RLCLK
(RX DATA)
RPOS
DS3170 DS3/E3 Single-Chip Transceiver
RNEG
RXP
RXN
(RX LINE)
BIAS V
0 V
B
BV
B
+
-
BV
V
V
HDB3 CODEWORD
7.3.1.3 UNI Mode Transmit Pin Functional Timing
The TDAT pin is available when the line interface is in the UNI mode and the transmit line pins are enabled
The TDAT signal changes a small delay after the positive edge of the reference clock signal if the clock pin is not
inverted, other wise they change after the negative edge. The TLCLK clock pin is the clock reference typically
used for the TDAT signal, but the TDAT can be time referenced to the TCLKI, TCLKO, RLCLK or RCLKO clock
pins. The TDAT pin can be inverted. Please refer to Figure 7-5
.
Figure 7-5. Tx Line IO UNI Functional Timing Diagram
TLCLK
TDAT
7.3.1.4 UNI Mode Receive Pin Functional Timing
The RDAT pin is available when the line interface is in the UNI mode. The RLCV pin is available when the line
interface is in the UNI Mode.
All bits on the RDAT pin, will come out the RSER pin, if the RSER pin is enabled.
The signal on the RLCV pin enables the BPV counter, which is in the line interface, to increment each clock it is
high.
The RDAT and RLCV signals are sampled at the rising edge of the reference clock signal if the clock pin is not
inverted, otherwise they are sampled at the negative edge. The RLCLK clock pin is the clock reference used for the
RDAT and RLCV signals. The RDAT and RLCV pins can be inverted. Please refer to Figure 7-6
.
39 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Figure 7-6. Rx Line IO UNI Functional Timing Diagram
RLCLK
RDAT
RLVC
INC BPV COUNTER TWICE INC BPV COUNTER ONCE
7.3.2 DS3/E3 Framing Overhead Functional Timing
Figure 7-7 shows the relationship between the DS3 receive overhead port pins.
Figure 7-7. DS3 Framing Receive Overhead Port Timing
ROHCLK
ROHSOF
FAS
ROH
Figure 7-8
FAS
FAS
FAS
FAS
3
2
4
FAS
10
NA
1
FAS
FAS
FAS7FAS
6
5
FAS
FAS
9
8
A
10
1234567891011121314 16171819202122232415
shows the relationship between the E3 G.751 receive overhead port pins.
FAS
N
1
2
FAS3FAS
FAS
FAS
8
6
FAS
4
5
FAS
FAS
10
9
Figure 7-8. E3 G.751 Framing Receive Overhead Port Timing
ROHCLK
ROHSOF
ROH
FAS
10
FAS
FAS
FAS
3
2
4
FAS
FAS
5
8
FAS7FAS
6
FAS
FAS
A
10
9
FAS
NA
1
FAS
N
1
1234567891011121314 16171819202122232415
Figure 7-9
shows the relationship between the E3 G.832 receive overhead port pins.
Figure 7-9. E3 G.832 Framing Receive Overhead Port Timing
ROHCLK
ROHSOF
ROH
FA1
FA1
FA1
3
2
4
FA1
FA1
FA17FA1
6
5
FA2
8
1
GC
7
6
1
8
FA1
GC
GC
FA2
FA2
3
2
1234567891011121314 16171819202122232415
FA2
FA2
5
4
FAS
FA2
2
6
FAS3FAS
FA27FA2
4
5
8
6
FAS
FAS
FAS
FAS
FAS
10
9
8
1
3
2
EM
EM
EM
EM
EM
5
4
40 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Figure 7-10
shows the relationship between the DS3 transmit overhead port pins.
Figure 7-10. DS3 Framing Transmit Overhead Port Timing
TOHCLK
TOHSOF
TOHEN
TOH
X1 F13C12F12 C13 F14 F21
F74C73F73
F11
C11
X2
C21
F22
1234567891011121314 16171819202122232415
Figure 7-11
shows the relationship between the E3 G.751 transmit overhead port pins.
Figure 7-11. E3 G.751 Framing Transmit Overhead Port Timing
TOHCLK
TOHSOF
TOHEN
TOH
Figure 7-12
FAS
10
FAS
FAS
FAS
3
2
4
FAS
FAS
FAS7FAS
6
5
FAS
NA
1
FAS
FAS
9
8
A
10
1234567891011121314 16171819202122232415
shows the relationship between the E3 G.832 transmit overhead port pins.
FAS
N
1
F23C22
FAS
2
C23 F24
FAS3FAS
F31 C31P1 C32F32
FAS
FAS
FAS
8
6
FAS
9
9
FAS
4
5
Figure 7-12. E3 G.832 Framing Transmit Overhead Port Timing
TOHCLK
TOHSOF
TOHEN
TOH
FA2
FA2
3
2
FA1
FA1
FA1
3
2
4
FA1
FA1
FA17FA1
6
5
GC
7
6
1
8
FA1
GC
GC
FA2
1
8
FA2
FA2
6
5
4
EM
8
1
FA27FA2
FA2
EM
EM
3
2
1234567891011121314 16171819202122232415
7.3.3 DS3/E3 Serial Data Interface
7.3.3.1 DS3/E3 Framed Mode Transmit Serial Interface Pin Functional Timing
The TSER pin is used to input DS3 or E3 payload data bits in all framing modes as well as the C-bits, which can be
treated as payload, in DS3 M23 and E3 G.751 framing modes. The TDEN signal is used to determine the DS3 or
E3 payload bit positions on TSER. The TDEN signal goes high three clocks before the first bit of a payload
sequence is clocked into the TSER pin and it goes low three clocks before the payload sequence is stopped being
clocked in to the TSER pin. The TSOFO signal pulses high three clocks before the start of the DS3 or E3 overhead
bit position on TSER. The TSOFI pin is used to set the DS3 or E3 frame position. When the TSOFI pin transitions
low to high, the first DS3/E3 overhead bit position on TSER will be forced to align to it
Figure 7-13
to Figure 7-15 show the relationship between the transmit serial interface pins.
EM
EM
5
4
41 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Figure 7-13. DS3 Framed Mode Transmit Serial Interface Pin Timing
TCLKO or
TCLKI
TSOFO
TSOFI
DS3 TGCLK
DS3 TSER
DS3 TDEN
TSER DATA IS OVERWRITTEN WITH OH
6 7 8 9 10 11 12 1312345 1415
Figure 7-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing
TCLKO or
TCLKI
TSOFO
TSOFI
E3 TGCLK
E3 TSER
E3 TDEN
TSER DATA IS OVERWRITTEN WITH OH
6 7 8 9 10 11 12 1312345 1415
Figure 7-15. E3 G.832 Framed Mode Transmit Serial Interface Pin Timing
TCLKO or
TCLKI
TSOFO
TSOFI
E3 TGCLK
E3 TSER
E3 TDEN
TSER DATA IS OVERWRITTEN WITH OH
6 7 8 9 10 11 12 1312345 14151617181920
7.3.3.2 DS3/E3 Framed Mode Receive Serial Interface Pin Functional Timing
The RSER signal has the DS3 or E3 payload as well as the DS3 or E3 overhead bits. The RDEN signal is used to
enable external logic for payload processing and will be high during the DS3 or E3 payload bits and low during the
DS3 or E3 overhead bits. The RGCLK signal can also be used to clock only the DS3 or E3 payload bits into
external logic since the clock is stopped during the DS3 or E3 overhead bits. The RSOFO signal marks the first
overhead bit of the DS3 or E3 frame.
Figure 7-16
42 of 233
to Figure 7-18 show the relationship between the receive serial interface pins.
DS3170 DS3/E3 Single-Chip Transceiver
Figure 7-16. DS3 Framed Mode Receive Serial Interface Pin Timing
RCLKO or
RCLKI
RSOFO
DS3 RGCLK
DS3 RSER
DS3 RDEN
X1
6 7 8 9 10 11 12 1312345 1415
Figure 7-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing
RCLKO or
RCLKI
RSOFO
E3 RGCLK
E3 RSER
E3 RDEN
FAS 1111010000
6 7 8 9 10 11 12 1312345 1415
A
N
Figure 7-18. E3 G.832 Framed Mode Receive Serial Interface Pin Timing
RCLKO or
RCLKI
RSOF
E3 RGCLK
E3 RSER
FA1 11110110
FA2 00101000
E3 RDEN
6 7 8 9 10 11 12 1312345 14151617181920
7.3.4 Microprocessor Interface Functional Timing
7.3.4.1 SPI Functional Timing Diagrams
NOTE: The transmit and receive order of the address and data bits are selected by the D[5]/SPI_SWAP pin. The
R/W (read/write) MSB bit and B (burst) LSB bit position is not effected by the D[5]/SPI_SWAP pin setting.
7.3.4.1.1 SPI Transmission Format and CPHA Polarity
When CPHA = 0,
followed by a data byte.
the data byte. When CPHA = 0,
BURST bit is set, no additional control bytes are expected after the first control byte(s) and data are transferred. If
the BURST bit is set, the address will be incremented for each additional byte of data transferred until
asserted. If
and the address for the next access will be received from that. Anytime
terminated.
When CPHA = 1,
again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are
43 of 233
CS may be de-asserted between accesses. An access is defined as one or two control bytes
CS cannot be de-asserted between the control bytes, or between the last control byte and
CS may also remain asserted between accesses. If it remains asserted and the
CS is de-
CS remains asserted and the BURST bit is not set, a control byte(s) is expected following the data byte,
CS is de-asserted, the BURST access is
CS may remain asserted for more than one access without being toggled high and then low
DS3170 DS3/E3 Single-Chip Transceiver
expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access.
Additionally,
terminated, and the next byte received when
CS may also be de-asserted between accesses when CPHA =1. In the case, any BURST access is
CS is re-asserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events
(high or low). Since the SPI port of the DS3170 acts as a slave device, the master device provides the clock. The
user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is
providing.
Figure 7-19. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0
SCK
CS*
MOSI
MISO
1A7A13 A12 A11 A10 A9 A8
A6 A5 A4 A3 A2 A1
LSBMSB
A0
B
LSBMSB
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7-20. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0
SCK
CS*
MOSI
MISO
1A7A13 A12 A11 A10 A9 A8
A6 A5 A4 A3 A2 A1
LSBMSB
A0
B
LSBMSB
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7-21. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1
SCK
CS*
LSBMSB
LSBMSB
MOSI
MISO
1A7A13 A12 A11 A10 A9 A8
A6 A5 A4 A3 A2 A1
LSBMSB
A0
B
LSBMSB
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7-22. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1
SCK
CS*
MOSI
1A7A13 A12 A11 A10 A9 A8
MISO
44 of 233
A6 A5 A4 A3 A2 A1
LSBMSB
A0
B
LSBMSB
D7 D6 D5 D4 D3 D2 D1 D0
LSBMSB
LSBMSB
DS3170 DS3/E3 Single-Chip Transceiver
Figure 7-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0
SCK
CS*
D7 D6 D5 D4 D3 D2 D1 D0
MOSI
0A13
A12A11A10A9A8A7A6A5
LSBMSB
A4 A3 A2 A1 A0
B
LSBMSB
MISO
Figure 7-24. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0
SCK
CS*
D7 D6 D5 D4 D3 D2 D1 D0
MOSI
A12A11A10A9A8A7A6A5
A13
0
LSBMSB
A4 A3 A2 A1 A0
B
LSBMSB
MISO
Figure 7-25. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 1
LSBMSB
LSBMSB
SCK
CS*
D7 D6 D5 D4 D3 D2 D1 D0
MOSI
0A13
A12A11A10A9A8A7A6A5
LSBMSB
A4 A3 A2 A1 A0
B
LSBMSB
LSBMSB
MISO
Figure 7-26. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 1
SCK
CS*
D7 D6 D5 D4 D3 D2 D1 D0
MOSI
A13
0
A12A11A10A9A8A7A6A5
LSBMSB
A4 A3 A2 A1 A0
MISO
7.3.4.2 Parallel Port Interface Diagrams
Figure 7-27
and Figure 7-29 show examples of a 16-bit databus and an 8-bit databus, respectively. In 16-bit mode,
the A[0]/BSWAP signal controls whether or not to byte swap. In 8-bit mode, the A[0]/BSWAP signal is used as the
LSB of the address bus (A[0]). The selection of databus size is determined by the WIDTH input signal. See also
Section 9.1.1
.
B
LSBMSB
LSBMSB
45 of 233
Figure 7-27. 16-Bit Mode Write
A[0]/BS WAP
DS3170 DS3/E3 Single-Chip Transceiver
A[10:1]
D[15:0]
CS
WR
RD
RDY
Note: Address 0x2B0 = 0x1234
0x2B0
0x1234
Z
Figure 7-28. 16-Bit Mode Read
A[0]/BS WAP
A[10:1]
D[15:0]
CS
0x2B0
0x1234
Z
WR
RD
RDY
Note: Address 0x2B0 = 0x1234
ZZ
46 of 233
Figure 7-29. 8-Bit Mode Write
A[0]/BS WAP
DS3170 DS3/E3 Single-Chip Transceiver
A[10:1]
D[7:0]
CS
WR
RD
RDY
Note: Address 0x2B0 = 0x34
0x2B1 = 012
0x2B0
0x34
Z
Figure 7-30. 8-Bit Mode Read
A[0]/BS WAP
A[10:1]
D[7:0]
CS
0x2B0
0x34
0x2B0
0x12
Z
Z
Z
0x2B0
0x12
WR
RD
RDY
Note: Address 0x2B0 = 0x34
0x2B1 = 012
ZZ
ZZ
Figure 7-31
and Figure 7-32 are examples of databuses without and with byte swapping enabled, respectively.
When the A[0]/BSWAP pin is set to 0, byte swapping is disabled, and when one, byte swapping is enabled. This
pin should be static and not change while operating. Note: Address bit A[0] is not used in 16-bit mode. See also
Section 9.1.3
.
47 of 233
Figure 7-31. 16-Bit Mode without Byte Swap
A[0]/BS WAP
DS3170 DS3/E3 Single-Chip Transceiver
A[10:1]
D[15:0]
CS
WR
RD
RDY
Note: Address 0x2B0 = 0x1234
0x2B2 = 0x5678
0x2B0 0x2B2
0x1234 0x5678
Z
Z
Figure 7-32b 16-Bit Mode with Byte Swap
A[0]/BS WAP
A[10:1]
D[15:0]
CS
0x2B0
0x3412
Z
Z
0x2B2
0x7856
WR
RD
RDY
Note: Address 0x2B0 = 0x1234
0x2B2 = 0x5678
Z
Z
Z
Z
Clearing status latched registers on a read or write access is selectable via the GL.CR1
.LSBCRE register bit.
Clearing on read clears all bits in the register, while the clear on write clears only those bits which are written with a
‘1’ when the user writes to the status latched register.
To use the Clear on Read method, the user must only read the status latched register. All bits are set to zero after
the read. Figure 7-33
shows a read of a status latched register and another read of the same register verifying the
register has cleared.
To use the Clear on Write method, the user must write the register with ones in the bit locations that he desires to
clear. Figure 7-34
which he wrote a ‘1.’ See also Section 9.1.6
shows a read, a write, and then a subsequent read revealing the results of clearing of the bits,
.
48 of 233
Figure 7-33. Clear Status Latched Register on Read
A[0]/BS WAP
DS3170 DS3/E3 Single-Chip Transceiver
A[10:1]
D[15:0]
CS
WR
RD
RDY
0x1C0
0xFFFF
Z
Z
Z
0x1C0
0x0000
Figure 7-34. Clear Status Latched Register on Write
A[0 ]/B SWAP
A[10:1]
D[15:0]
CS
WR
0x1C0
0xFFFF
0x1C0
0x5555
Z
0x1C0
0xAAAA
RD
RDY
Figure 7-35
Z
Z
Z
and Figure 7-36 show exaggerated views of the Ready Signal to describe the difference in access
Z
Z
Z
times to write or read to or from various memory locations on the DS3170 device. Some registers will have a faster
access time than others and if needed, the user can implement the RDY signal to maximize efficiency of read and
write accesses.
49 of 233
Figure 7-35. RDY Signal Functional Timing Write
A[0]/BSWAP
DS3170 DS3/E3 Single-Chip Transceiver
A[10:1]
D[15:0]
CS
WR
RD
RDY
0x2B0 0x3A4
0x1234 0x0078
Z
Z
Z
Figure 7-36. RDY Signal Functional Timing Read
A[0]/BSWAP
A[10:1]
D[15:0]
CS
WR
0x1C0
0xFFFF
0x3A4
Z
0xFFFF
RD
RDY
See also Figure 17-8
Z
and Figure 17-9.
7.3.5 JTAG Functional Timing
See Section 12.5.
Z
Z
Z
50 of 233
DS3170 DS3/E3 Single-Chip Transceiver
8 INITIALIZATION AND CONFIGURATION
STEP 1: Check Device ID Code.
Before any testing can be done, the device ID code, which is stored in GL.IDR, shoud be checked against the
device ID code shown below to ensure correct device is being used.
Current device ID codes is:
o DS3170 rev 1.0: 004Fh
STEP 2: Initialize the Device.
Before configuring for operation, make sure the device is in a known condition with all registers set to their default
value by initiating a Global Reset. (See Section 9.3
Global Reset bit (GL.CR1.RST). A Port Reset is not necessary since the global reset includes a reset of the port to
its default values.
STEP 3: Clear the Reset.
It is necessary to clear the RST bit to begin normal operation.
After clearing the RST bit, the device is configured for default mode.
Default mode:
Framer: C-bit DS3
LIU: Disabled
STEP 4: Clear the Data Path Resets and the Port Power-Down bit.
.) A Global Reset can be initiated via the RST pin or by the
The default value of the Data Path Resets is one, which keeps the internal logic in the reset status. The user
needs to clear the following bits:
GL.CR1.RSTDP = 0
PORT.CR1.RSTDP = 0
PORT.CR1.PD = 0
STEP 5: Configure the CLAD
If using the LIU, configure the CLAD (which supplies the clock to the Receive LIU) via the CLAD bits in
the GL.CR2
Note: The user must supply a DS3, E3, STS-1, 77.76 MHz, or 19.44 MHz clock to the REFCLK pin.
STEP 6: Select the clock source for the transmitter.
Loop Time (use the receive clock): Set PORT.CR3
CLAD Source: Set PORT.CR3
TCLKI Source: Set PORT.CR3
If using the CLAD, properly configure the CLAD by setting the CLAD bits in GL.CR2.
STEP 7: Configure the Framing Mode and the Line Mode..
PORT.CR2.LM[2:0] = 011 (LIU on, JA in rx side) or another setting. See Table 9-26
PORT.CR2.FM[2:0] set to correct mode. See Table 9-25.
STEP 8: Disable Payload AIS (downstream AIS) and Line AIS
PORT.CR1.PAIS[2:0] = 111
PORT.CR1.LAIS[1:0] = 11
STEP 9: Enable the port (for non-LIU modes)
PORT.CR2.TLEN = 1
register.
.LOOPT = 1
.CLADC = 0
.CLADC = 1
51 of 233
Table 8-1. Configuration of Port Register Settings
DS3170 DS3/E3 Single-Chip Transceiver
MODE
DS3 C-Bit Framed 0x2000 0000 0011 0000 0111 0x0000 0x0000
DS3 M13 Framed 0x2000 0000 0011 0000 1111 0x0000 0x0000
E3.751 Framed 0x2000 0000 0011 0001 0111 0x0000 0x0000
E3.823 Framed 0x2000 0000 0011 0001 111X 0x0000 0x0000
Note: The Line Mode has been configured with the LIU enabled and the JA in the receive path (LM[2:0] = 011) for all modes.
PORT.CR1
0x040
PORT.CR2
0x042
PORT.CR3
0x044
PORT.CR4
0x046
8.1 Monitoring and Debugging
To determine if the device is receiving a good signal and that the chip is correctly configured for its environment,
check the following status registers.
Receive Loss of Lock – PORT.SR
from the incoming signal. This may indicate that the LIU’s master clock does not match the frequency of the
incoming signal. Verify that the CLAD is configured to match the clock input on the REFCLK pin (DS3, E3, STS-1).
See Table 9-11
Loss of Signal – LINE.RSR
is no signal on the line, or that the signal is attenuated beyond recovery.
Loss of Frame – T3.RSR1
synchronize to the incoming data. Verify that the FM bits have been correctly configured for the correct mode of
traffic (DS3, E3 G.751, E3 G.832)
.
.LOS: This indicates that the LIU is unable to recover the clock and data because there
.LOF (or E3751.RSR1 or E3832.RSR1): This indicates that the framer was unable to
.RLOL: The clock recovery circuit of the LIU was unable to recover the clock
Other helpful techniques to utilize in diagnosing a problem include using Line Loopback and Diagnostic Loopback.
These features help to isolate and identify the source of the problem. Line Loopback will loop the receive input to
the transmit output, eliminating the transmit side input from the equation. Diagnostic Loopback will loop the transmit
output before the LIU to the receive framer, eliminating the analog Receive LIU and the receive side analog
circuitry.
One other potential problem is the Line Encoding/Decoding. The device needs to be configured in the same
mode as the far end piece of equipment. If the far end piece of equipment is transmitting and receiving HDB3/B3ZS
encoded data, the DS3170 also must be configured to do the same. This is controlled by the LINE.TCR.TZSD and
the LINE.RCR.RZSD bits.
52 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9 FUNCTIONAL DESCRIPTION
9.1 Processor Bus Interface
9.1.1 SPI Serial Port Mode
The external processor bus can be configured to operate in SPI serial bus mode. See the section 7.3.4.1 for
detailed timing diagrams.
When SPI = 1, SPI bus mode is implemented using four signals: clock (CLK), master-out slave-in data (MOSI),
master-in slave-out data (MISO), and chip select (
and D[6]/SPI_CPHA pins.
The order of the address and data bits in the serial stream is selectable using the D[5]/SPI_SWAP pin. The R/W bit
is always first and B bit is always last in the initial control word and are not effected by the D[5]/SPI_SWAP pin
setting.
9.1.2 8/16 Bit Bus Widths
The external processor bus can be sized for 8 or 16 bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the
address is composed of all the address bits including A[0], the lower 8 data lines D[7:0] are used and the upper 8
data lines D[15:8] are not used and never driven during a read cycle. When in 16-bit mode (WIDTH=1), the
address bus does not include A[0] (the LSB of the address bus is not routed to the chip) and all 16 data lines
D[15:0] are used. See Figure 7-27
and Figure 7-29 for functional timing diagrams.
CS). Clock polarity and phase can be set by the D[7]/SPI_CPOL
9.1.3 Ready Signal (RDY)
The RDY signal allows the microprocessor to use the minimum bus cycle period for maximum efficiency. When
this signal goes low, the
Note: The
design blocks. The
design blocks.
RDY signal will not go active if the user attempts to read or write unused registers not assigned to any
RD or WR cycle can be terminated. See Figure 7-35 for functional timing diagrams.
RDY signal will go active if the user writes or reads reserved registers or unused registers within
9.1.4 Byte Swap Modes
The processor interface can operate in byte swap mode when the data bus is configured for 16-bit operation. The
A[0]/BSWAP pin is used to determine whether byte swapping is enabled. This pin should be static and not change
while operating. When the A[0]/BSWAP pin is low the upper register bits REG[15:8] are mapped to the upper
external data bus lines D[15:8], and the lower register bits REG[7:0] are mapped to the lower external data bus
lines D[7:0]. When the A[0]/BSWAP pin is high the upper register bits REG[15:8] are mapped to the lower external
data bus lines D[7:0], and the lower register bits REG[7:0] are mapped to the upper external data bus lines D[15:8].
See Figure 7-31
and Figure 7-32 for functional timing diagrams.
9.1.5 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODE=0 the
read-write strobe mode is enabled and a negative pulse on
performs a write cycle. When MODE=1 the data strobe mode is enabled and a negative pulse on
high performs a read cycle, and a negative pulse on
strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the “Motorola”
mode.
RD performs a read cycle, and a negative pulse on WR
DS when R/W is
DS when R/W is low performs a write cycle. The read-write
9.1.6 Clear on Read/Clear on Write Modes
The latched status register bits can be programmed to clear on a read access or clear on a write access. The
global control register bit GL.CR1.LSBCRE controls the mode that all of the latched registers are cleared. When
LSBCRE=0, the latched register bits will be cleared when the register is written to and the write data has the
register bits to clear set. When LSBCRE=1, the latched register bits that are set will be cleared when the register is
read.
53 of 233
DS3170 DS3/E3 Single-Chip Transceiver
The clear on write mode expects the user to use the following protocol:
1. Read the latched status register
2. Write to the registers with the bits set that need to be cleared.
This protocol is useful when multiple uncoordinated software tasks access the same latched register. Each task
should only clear the bits with which it is concerned; the other tasks will clear the bits with which they are
concerned.
The clear on read mode is simpler since the bits that were read as being set will be cleared automatically. This
method will work well in a software system where multiple tasks do not read the same latched status register. The
latched status register bits in clear on read mode are carefully designed not to miss events that occur while a
register is being read when the latched bit has not already been set. Refer to Figure 7-33
and Figure 7-34.
9.1.7 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when inactive. The GL.CR1.INTM bit controls the pin
configuration. If it is set, the
impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
INT pin will drive high when inactive. After a reset, the INT pin will be in high
9.1.8 Interrupt Structure
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
status bits in the global status (GL.SR) and global status latched register (GL.SRL) are read to determine if the
interrupt source is a global event, a global performance monitor update or whether it came from the port. If the
interrupt event came from the port then the port status register (PORT.SR) and port status register latched
(PORT.SRL) can be read to determine if the interrupt source is a common port event like the performance monitor
update or LIU or whether it came from the DS3/E3 Framers, BERT, HDLC, FEAC or Trail Trace status registers. If
the interrupt came from the DS3/E3 Framers, BERT, HDLC, FEAC or Trail Trace status registers, then those
registers will need to be read to determine the event that caused the interrupt.
The source of an interrupt can be determined by reading three status registers: the global, port and block status
registers.
When a mode is not enabled, then interrupts from that source will not occur. For example, if E3 framing mode is
enabled, an interrupt source that is defined in DS3 framing, but not in E3 framing, cannot create a new interrupt.
Note that when modes are changed, the latched status bits of the new mode, as well as any other mode, may get
set. If the data path reset is set during or after the mode change, the latched status bits will be automatically
cleared. If the data path reset is not used to clear the latched status bits, then the registers must be cleared by
reading or writing to them based on the register clear method selected.
54 of 233
Figure 9-1. Interrupt Structure
SRL bit
SRIE bit
DS3170 DS3/E3 Single-Chip Transceiver
SRL bit
SRIE bit
SRL bit
SRIE bit
BLOCK LATCHED
STATUS and
INTERRUPT
ENABLE
REGISTERS
PORT.ISR bit
PORT INTERRUPT
STATUS
REGISTER
GL.ISR.PISRn
GL.ISRIE.
PISRIEn
GLOBAL
INTERRUPT
STATUS REGISTER
and INTERRUPT
ENABLE REGISTER
PORT
INTERRUPTS
GLOBAL
INTERRUPTS
INT
Figure 9-1
not only tells the user how to determine which event caused the interrupt, it also tells the user how to
enable a particular interrupt. Each block has a Status Register Interrupt Enable register which must be set in order
to enable an interrupt. The next step is to unmask the interrupt at the port level. This is controlled in the Global
Interrupt Status Register Interrupt Enable register (GL.ISRIE
). Now the device is ready to drive the INT pin low
when a particular status bit gets set.
For example, in order to enable DS3 Out of Frame interrupts, the following registers would need to be written:
Register bit Address Value Written Note
T3.RSRIE1.OOFIE 0x12C 0x0002 Unmask OOF interrupt
GL.ISRIE.PISRIE 0x012 0x0010 Unmask Port interrupts
The following status registers bits will be set upon reception of OOF:
Register bit Address Value Read Note
T3.RSRL1.OOFL 0x128 0x0002 DS3 Out of Frame
PORT.ISR.FMSR 0x050 0x0001 Framer Block Interrupt Active
GL.ISR.PISR 0x010 0x0010 Port Interrupt Active
9.2 Clocks
9.2.1 Line Clock Modes
9.2.1.1 Loop Timing Enabled
When loop timing is enabled (PORT.CR3
source. The TCLKI pin is not used as a clock source. Because loop timing is enabled, the loopback functions (LLB,
PLB and DLB) do not cause the clock sources to switch when they are activated. The transmit and receive signal
pins can be timed to a single clock reference without concern about having the clock source change during
loopbacks.
55 of 233
.LOOPT), the transmit clock source is the same as the receive clock
DS3170 DS3/E3 Single-Chip Transceiver
9.2.1.1.1 LIU Enabled, Loop Timing Enabled
In this mode, the receive LIU sources the clock for both the receive and transmit logic. The RCLKO, TCLKO and
TLCLK clock output pins will be the same. The transmit or receive line payload signal pins can be timed to any of
these clock. The use of the RCLKO pin as the timing source is suggested. If RCLKO is used as the timing source,
be sure to set PORT.CR3
.RFTS = 0 for output timing.
9.2.1.1.2 LIU Disabled, Loop Timing Enabled
In this mode, the RLCLK pin are the source of the clock for both the receive and transmit logic. The RCLKO,
TCLKO and TLCLK clock output pins will both be the same as the RLCLK clock. The transmit or receive line
payload signals can be timed to any of these clock pins. The use of the RLCLK pin as the timing source is
suggested. If RLCLK is used as the timing source, be sure to set PORT.CR3.RFTS = 1 for input timing.
9.2.1.2 Loop Timing Disabled
When loop timing is disabled, the transmit clock source can be different than the receive clock source. The
loopback functions, LLB, PLB and DLB, will cause the clock sources to switch when they are activated. Care must
be taken when selecting the clock reference for the transmit and receive signals.
The most versatile clocking option has the receive line interface signals timed to RLCLK, the transmit line interface
signals timed to TLCLK, the receive framer signals timed to RCLKO, and the transmit framer signals timed to
TCLKO. This clocking arrangement works in all modes.
When LLB is enabled, the clock on the TLCLK pin will switch to the clock from the RLCLK pin or RX LIU. It is
recommended that the transmit line interface signals be timed to the TLCLK pins. If TLCLK is used as the timing
source, be sure to set PORT.CR3
.TLTS = 0 for output timing.
When PLB is enabled, the TCLKI pin will not be used and the internal transmit clock is switched to the internal
receive clock. The clock on the TCLKO pin will switch to the clock from the RLCLK pins or RX LIU. The framer
input signals will be ignored while PLB is enabled. It is recommended that the transmit line interface signals be
timed to the TCLKO pins.
When DLB is enabled, the internal receive clock is switched to the internal transmit clock which is sourced from the
TCLKI pin or one of the CLAD clocks, and the clock on the RLCLK pin or from the RX LIU will not be used. The
clock on the RCLKO pin will switch to the clock on the TCLKI pins or one of the CLAD clocks. The receive line
signals from the RX LIU or line interface pins will be ignored. It is recommended that the receive framer pins be
timed to the RCLKO pin. If TCLKO is used as the timing source, be sure to set PORT.CR3
.TFTS = 0 for output
timing.
When both DLB and LLB are enabled, the TLCLK clock pin are connected to either the RX LIU recovered clock or
the RLCLK clock pin, and the RCLKO clock pin will be connected to the TCLKI clock pin or one of the CLAD
clocks. It is recommended that the transmit line signals be timed to the TLCLK pin, the receive line interface signals
be timed to the RLCLK pin, the receive framer signals be timed to the RCLKO pin, and the transmit framer signals
be timed to the TCLKO pin.
9.2.1.2.1 LIU Enabled - CLAD Timing Disabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
9.2.1.2.2 LIU Enabled - CLAD Timing Enabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
9.2.1.2.3 LIU Disabled - CLAD Timing Disabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
9.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
56 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9.2.2 Sources of Clock Output Pin Signals
The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks pin
(TCLKI), the receive clock input pin (RLCLK), the recovered clock in the receive LIU, and the clock signals in the
clock rate adapter circuit (CLAD). The default clock source for the receive logic is the RLCLK pin if the LIU is
disabled; otherwise the default clock is sourced from the Rx LIU clock when the RX LIU is enabled. The default
clock source for the transmit logic is the CLAD clocks.
The LIU is enabled based on the line mode bits(LM[2:0]) (see Table 9-26
CLADC are located in the port configuration registers. LIUEN is not a register bit; it is a variable based on the line
mode bits. Table 9-1
decodes the LM bits for LiUEN selection.
). The bits LM[2:0], LBM[2:0], LOOPT and
Table 9-1. LIU Enable Table
LM[2:0] LIUEN
000 0 Disabled
001 1 Enabled
010 1 Enabled
011 1 Enabled
1XX 0 Disabled
Table 9-2 identifies the framer clock source and the line clock source depending on the mode that the device is
configured. Putting the device in loopback will typically mux in a different clock than the normal clock source.
LIU
STATUS
Table 9-2. All Possible Clock Sources Based on Mode and Loopback
Rx FRAMER
MODE LOOPBACK
Loop Timed Any
Normal None
Normal LLB
Normal PLB
Normal DLB Same as Tx
Normal LLB and DLB Same as Tx
CLOCK
SOURCE
RLCLK or
RXLIU
RLCLK or
RXLIU
RLCLK or
RXLIU
RLCLK or
RXLIU
Tx FRAMER
CLOCK
SOURCE
Same as RX Same as Rx
TCLKI or
CLAD
TCLKI or
CLAD
Same as RX Same as Rx
TCLKI or
CLAD
TCLKI or
CLAD
Tx LINE
CLOCK
SOURCE
Same as Tx
Same as Rx
Same as Tx
RLCLK or
RXLIUn
57 of 233
Table 9-3
identifies the source of the output signal TLCLK based on certain variables and register bits.
Table 9-3. Source Selection of TLCLK Clock Signal
DS3170 DS3/E3 Single-Chip Transceiver
SIGNAL
TLCLK
Figure 9-2
LOOPT
(PORT.
CR3)
1 XXX NA 1 X Rx LIU
1 XXX NA 0 X RLCLK
0 010 LLB 1 X Rx LIU
0 110 LLB 1 X Rx LIU
0 010 LLB 0 X RLCLK
0 110 LLB 0 X RLCLK
0 011 PLB 1 X Rx LIU
0 011 PLB 0 X RLCLK
0 000 NO X 0 CLAD
0 001 NO X 0 CLAD
0 100 NO X 0 CLAD
0 10X NO X 0 CLAD
0 111 NO X 0 CLAD
0 000 NO X 1 TCLKI
0 001 NO X 1 TCLKI
0 100 NO X 1 TCLKI
0 10X NO X 1 TCLKI
0 111 NO X 1 TCLKI
shows the source of the TCLKO signals.
LBM[2:0]
(PORT.CR4
)
LLB or
PLB
LIUEN
CLADC
(PORT.CR3)
SOURCE
Figure 9-2. Internal Tx Clock
PORT.CR3.
CLADC
CLAD
TCLKI
0
1
RCLKO
Table 9-4
identifies the source of the output signal TCLKO based on certain variables and register bits.
PAYLOAD
LOOPBACK
0
TCLKO
1
58 of 233
Table 9-4. Source Selection of TCLKO (Internal Tx Clock)
DS3170 DS3/E3 Single-Chip Transceiver
SIGNAL
TCLKO
Figure 9-3
LOOPT
PORT.CR3
1 XXX 1 X Rx LIU
1 XXX 0 X RLCLK
0 PLB (011) 1 X Rx LIU
0 PLB (011) 0 X RLCLK
0 PLB disabled X 0 CLAD
0 PLB disabled X 1 TCLKI
shows the source of the RCLKO signals.
LBM[2:0]
(PORT.CR4)
Figure 9-3. Internal Rx Clock
LIUEN
RLCLK
0
LIUEN
DIAGNOSTIC
LOOPBACK
0
CLADC
(PORT.CR3)
SOURCE
Rx LIU CLOCK
1
RCLKO
1
TCLKO
Table 9-5
identifies the source of the output signal RCLKO based on certain variables and register bits.
Table 9-5. Source Selection of RCLKO Clock Signal (Internal Rx Clock)
SIGNAL
RCLKO
LOOPT
PORT.CR3
1 XXX 1 X Rx LIU
1 XXX 0 X RLCLK
0 DLB disabled 1 X Rx LIU
0
0 DLB (1XX) X 0 CLAD
0 DLB (1XX) or ALB (001) 0 1 TCLKI
0 DLB (1XX) 1 1 TCLKI
LBM[2:0]
(PORT.CR4)
DLB disabled & ALB
disabled
LIUEN
0 X RLCLK
CLADC
(PORT.CR3)
SOURCE
9.2.3 Line IO Pin Timing Source Selection
The line IO pins can use any input clock pin (RLCLK or TCLKI) or output clock pin (TLCLK, RCLKO, or TCLKO) for
its clock pin and meet the AC timing specifications as long as the clock signal is valid for the mode the part is in.
The clock select bit for the transmit line IO signal group PORT.CR3
timing.
59 of 233
.TLTS selects the correct input or output clock
DS3170 DS3/E3 Single-Chip Transceiver
9.2.3.1 Transmit Line Interface Pins Timing Source Selection
(TPOS/TDAT, TNEG)
The transmit line interface signal pin group has the same functional timing clock source as the TLCLK pin
described in Table 9-3
pin is always a valid output clock for external logic to use for these signals when PORT.CR3
The transmit line timing select bit (TLTS) is used to select input or output clock pin timing. When TLTS=0, output
clock timing is selected. When TLTS=1, input clock timing is selected. If TLTS is set for input clock timing and an
output clock pin is used, or if TLTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in Table 17-1
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
. Other clock pins can be used for the external timing. The TLCLK transmit line clock output
.TLTS=0.
, will not be valid. There are some combinations of TLTS=1 and other
Table 9-6. Transmit Line Interface Signal Pin Valid Timing Source Select
LOOPT
1 XXX X X 0 TLCLK, TCLKO, RCLKO
1 XXX 0 X 1 RLCLK
1 XXX 1 X 1 No valid timing to any input clock pin
0 DLB (100) X X 0 TLCLK, TCLKO, RCLKO
0 LLB (010) or PLB (011) X X 0 TLCLK, RCLKO
0 DLB & LLB (110) X X 0 TLCLK
0
0
0
0
0
9.2.3.2 Transmit Framer Pin Timing Source Selection
(TSER, TSOFI, TSOFO/TDEN)
not LLB (010), not PLB (011)
and not LLB & DLB (110)
not LLB (010) and not PLB (011)
and not LLB & DLB (110)
not LLB (010) and not PLB (011)
and not LLB & DLB (110)
LBM[2:0]
not DLB (100),
LLB (010) or PLB (011)
or DLB & LLB (110)
LLB (010) or PLB (011)
or DLB & LLB (110)
LIUEN
X X 0 TLCLK, TCLKO (default)
X 0 1 No valid timing to any input clock pin
X 1 1 TCLKI
0 X 1 RLCLK
1 X 1 No valid timing to any input clock pin
CLADC
TLTS
VALID TIMING TO THESE CLOCK PINS
The transmit framer signal pin group has the same functional timing clock source as the TCLKO pin described in
Table 9-4
valid output clock for external logic to use for these signals when TFTS=0.
The transmit framer select bit (TFTS) is used to select input or output clock pin timing. When TFTS=0, output clock
timing is selected. When TFTS=1, input clock timing is selected. If TFTS is set for input clock timing and an output
clock pin is used, or If TFTS is set for output clock timing and an input clock pin is used, then the setup, hold and
delay timings, as specified in Table 17-1
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
60 of 233
. Other clock pins can be used for the external timing. The TCLKO transmit clock output pin is always a
, will not be valid. There are some combinations of TFTS=1 and other
DS3170 DS3/E3 Single-Chip Transceiver
Table 9-7. Transmit Framer Pin Signal Timing Source Select
LBM[2:0]
LOOPT
1 XXX X X 0 TCLKO, TLCLK, RCLKO
1 XXX 0 X 1 RLCLK
1 XXX 1 X 1 No valid timing to any input clock pin
0 PLB (011) or DLB (100) or ALB 001) 0 X 0 TCLKO, TLCLK, RCLKO
0 PLB (011) or DLB (100) 1 X 0 TCLKO, TLCLK, RCLKO
0 DLB & LLB (110) X X 0 TCLKO, RCLKO
0 LLB (010) X X 0 TCLKO
0 not LLB, DLB or PLB (00X) X X 0 TCLKO, TLCLK
0 not PLB (011) X 0 1 No valid timing to any input clock pin
0 not PLB (011) X 1 1 TCLKI
0 PLB (011) 0 X 1 RLCLK
0 PLB (011) 1 X 1 No valid timing to any input clock pin
9.2.3.3 Receive Line Interface Pin Timing Source Selection
(RPOS/RDAT, RNEG/RLCV)
The receive line interface signal pin group must clocked in with the RLCLK clock input pin. When the LIU is
enabled, the receive line interface pins are not used so there is no valid clock reference.
LIUEN
CLADC
VALID TIMING TO THESE CLOCK PINS
TFTS
Table 9-8. Receive Line Interface Pin Signal Timing Source Select
LBM[2:0]
LOOPT
X XXX 0 X RLCLK
X XXX 1 X No valid timing to any clock pin
9.2.3.4 Receiver Framer Pin Timing Source Selection
(RSER, RSOFO/RDEN)
The receive framer signal pin group has the same functional timing clock source as the RCLKO pin described in
Table 9-5
Other clock pins can be used for the external timing. The RCLKO receive clock output pin is always a valid output
clock for external logic to use for these signals when PORT.CR3
The receive framer timing select bit (RFTS) is used to select input or output clock pin timing. When RFTS=0, output
clock timing is selected. When RFTS=1, input clock timing is selected. If RFTS is set for input clock timing and an
output clock pin is used, or If RFTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in Table 17-1
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
.
LIUEN
, will not be valid. There are some combinations of RFTS=1 and other
VALID TIMING TO THESE CLOCK PINS
CLADC
.RFTS=0.
61 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Table 9-9. Receive Framer Pin Signal Timing Source Select
LBM[2:0]
LOOPT
1 XXX X X 0 RCLKO, TLCLK, TCLKO
1 XXX 0 X 1 RLCLK
1 XXX 1 X 1 No valid timing to any input clock pin
0
0 PLB (011) or DLB (100) 1 X 0 RCLKO, TLCLK, TCLKO
0 DLB&LLB (110) X X 0 RCLKO, TCLKO
0 LLB (010) X X 0 RCLKO, TLCLK
0 not LLB, DLB or PLB (00X) X X 0 RCLKO
0 DLB (100) or LLB & DLB (110) X 0 1 No valid timing to any input clock pin
0 DLB (100) or LLB & DLB (110) X 1 1 TCLKI
0
0
PLB (011) or DLB (100) or ALB
(001)
not DLB (100) and
not LLB & DLB (110)
not DLB (100) and
not LLB & DLB (110)
LIUEN
0 X 0 RCLKO, TLCLK, TCLKO
0 X 1 RLCLK
1 X 1 No valid timing to any input clock pin
CLADC
VALID TIMING TO THESE CLOCK PINS
RFTS
9.2.4 Clock Structures On Signal IO Pins
The signals on the input pins (TSOFI, TSER) can be used with any of the clock pins for setup/hold timing on clock
input and output pins. There will be a flop at each input whose clock is connected to the signal from the input or
output clock source pins with as little delay as possible from the signal on the clock IO pins. This means using the
input clock signal before the delays of the internal clock tree to clock the input signals, and using the output clock
signals used to drive the output clock pins to clock the input signals.
The signals on the output pins (TPOS/TDAT, TNEG, TSOFO/TDEN, RSER, RSOFO/RDEN) can be with any of the
clock sources for delay timing. There will be a flop at each output whose clock is connected to the signal from the
input or output clock source pins with as little delay as possible from the signal on the clock IO pins. This means
using the input clock signal before the delays of the internal clock tree to clock the input signals, and using the
output clock signals used to drive the output clock pins to clock the input signals.
62 of 233
Figure 9-4. Example IO Pin Clock Muxing
DS3170 DS3/E3 Single-Chip Transceiver
TSER
PIN INVERT
TCLKI
PIN INVERT
RLCLK
PIN INVERT
RX LIU CLK
CLAD CLOCKS
DS3 CLK
E3 CLK
STS-1 CLK
DELAY
TFTS
SET
D
Q
0
1
Q
CLR
INTERNAL
SIGNAL
CLOCK TREE
INTERNAL
SIGNAL
CLOCK TREE
INTERNAL
SIGNAL
CLOCK TREE
INTERNAL
SET
D
Q
SIGNAL
Q
CLR
SET
D
Q
DELAY
Q
CLR
SET
D
Q
Q
PIN INVERT
CLR
0
1
TFTS
TDEN
TCLKO
PIN INVERT
SET
D
Q
DELAY
Q
CLR
SET
D
Q
Q
PIN INVERT
CLR
0
1
TLTS
TPOS
TLCLK
PIN INVERT
SET
D
Q
DELAY
Q
CLR
SET
D
Q
Q
PIN INVERT
CLR
0
1
RFTS
RSER
RCLKO
PIN INVERT
9.2.5 Gapped Clocks
The transmit and receive output clocks can be gapped in certain configurations. See Table 9-22 and Table 9-24 for
the configuration settings. The gapped clocks are active during DS3 or E3 framed payload bits overhead bits
depending on which mode the device is configured for.
In the internal DS3 or E3 frame modes, the transmit gapped clock is created by the logical OR of the TCLKO and
TDEN signals creating a positive or negative clock edge for each payload bit, the receive gapped clock is created
by the logical OR of the RCLKO and RDEN signals.
When the output clock is disabled, the gapped output signal is high during clock periods if the pin is not inverted,
otherwise it will be low.
The gapped clocks are very useful when the data being clocked does not need to be aligned with any frame
structure. The data is simply clocked one bit at a time as a continuous data stream.
9.3 Reset and Power-Down
The device can be reset at a global level via the GL.CR1.RST bit or the RST pin and at the port level via the
PORT.CR1
using the power on reset signal from one of the LIUs as well as from the
The external
create an internal global reset signal. The global reset signal resets all the status and control registers on the chip,
except the GL.CR1
63 of 233
.RST bit and the port can be explicitly powered down via the PORT.CR1.PD bit. The JTAG logic is reset
JTRST pin.
RST pin and the global reset bit in the global configuration register (GL.CR1.RST) are combined to
.RST bit, to their default values and resets all the other flops in the global logic and port to their
DS3170 DS3/E3 Single-Chip Transceiver
reset values. The processor bus output signals are also forced to be HIZ when the
global reset bit (GL.CR1
.RST) stays set after a one is written to it, but is reset to zero when the external RST pin is
RST pin is active (low). The
active or when a zero is written to it.
At the port level, the global reset signal combines with the port reset bit in the port control register
(PORT.CR1
the port to their default values and resets all the other flops, except PORT.CR1
reset bit (PORT.CR1
.RST) to create a port reset signal. The port reset signal resets all the status and control registers on
.RST, to their reset values. The port
.RST) stays set after a one is written to it, but is reset to zero when the global reset signal is
active or when a zero is written to it.
The data path reset function is a little different from the “general” reset function. The data path reset signal does not
reset the control register bits, but it does reset all of the status registers, counters and flops, the “general” reset
signal resets everything including the control register bits, excluding the reset bit. All clocks are functional, being
controlled by configuration bits, while data path reset is active. The LIU and CLAD circuits will be operating
normally during data path reset which allows the internal phase locked loops to settle as quickly as possible. The
LIU will be sending all zeroes (LOS) since data path reset will be forcing the transmit TPOS and TNEG to logic
zero. (NOTE: The BERT data path does not get reset when PORT.CR1
.RSTDP is active.)
The global data path reset bit (GL.CR1
data path reset bit (PORT.CR1
.RSTDP) and the port power-down bit (PORT.CR1.PD) bit gets set to one when the
.RSTDP) gets set to one when the global reset signal is active. The port
port reset signal is active. These control bits will be cleared when a zero is written to them when the port reset
signal is not active. The global data path reset signal is active when the global data path reset bit is set. The port
data path reset signal is active when either the global data path reset bit or the port data path reset bit is set. The
port power-down signal is active when the port power-down bit is set.
Figure 9-5. Reset Sources
Global Reset
RST pin
NOTE: Assumes
active high signals
SET
D
Q
GL.CR1. RST
Q
CLR
SET
D
Q
GL.CR1. RSTDP
Q
CLR
SET
D
Q
PORT.CR1.
Q
CLR
SET
Q
D
Q
CLR
PORT.CR1.
RSTDP
SET
D
Q
Q
CLR
PORT.CR1. PD
RST
Port Reset
Global Data Path Reset
Port Data Path Reset
Port Power Down
64 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Table 9-10. Reset and Power-Down Sources
PIN REGISTER BITS INTERNAL SIGNALS
RST
G:RST
G:RSTDP
P:RST
P:RSTDP
0 F0 F1 F0 F1 F1 1 1 1 1 1
1 1 F1 F0 F1 F1 1 1 1 1 1
1 0 1 1 F1 F1 0 1 1 1 1
1 0 1 0 X 1 0 1 0 1 1
1 0 1 0 X 0 0 1 0 1 0
1 0 0 1 F1 F1 0 0 1 1 1
1 0 0 0 1 1 0 0 0 1 1
1 0 0 0 1 0 0 0 0 1 0
1 0 0 0 0 1 0 0 0 1 1
P:PD
reset
Global
reset
Global dp
reset
Port reset
Port dp
Port power
dn
1 0 0 0 0 0 0 0 0 0 0
Register Bit States—F0: Forced to 0; F1: Forced to 1; 0: Set to 0; 1: Set to 1; X: Don’t care
Forced: Internally controlled; Set: User controlled
The reset signals in the device are asynchronous so they no not require a clock to put the logic into the reset state.
Clock signals may be needed to make the logic come out of the reset state.
The power-down function disables the appropriate clocks to cause the logic to generate a minimum of power. It
also puts the LIU circuits into the power-down mode. The 8KREF and ONESEC circuits can be powered down by
disabling the 8KREF source. The CLAD can also be powered down by disabling it.
After a global reset, all of the control and status registers are set to their default values and all the other flops are
reset to their reset values. The global register GL.CR1
PORT.CR1
PORT.CR1
GL.CR1
.PD bits, are set after the global reset. A valid initialization sequence would be to clear the
.PD bit, write to all of the configuration registers to set them in the desired modes, then clear the
.RSTDP and PORT.CR1.RSTDP bits. This would cause the logic in the port to start up in a repeatable
sequence. The device can also be initialized by clearing the GL.CR1
PORT.CR1
.PD them writing to all of the configuration registers to set them in the desired modes, and clearing all of
.RSTDP, and the port register PORT.CR1.RSTDP and
.RSTDP, PORT.CR1.RSTDP and
the latched status bits. The second initialization scheme could cause the device to temporarily go into modes of
operation that were not requested, but will quickly go into the requested modes of operation.
Some of the IO pins are put in a known state at reset. The transmit LIU outputs TXP and TXN are quiet and will not
drive positive or negative pulses. The global IO pins (GPIO[7:0]) are set as inputs at global reset. The port output
pins (TLCLK, TPOS/TDAT, TNEG, TOHCLK, TOHSOF, TSOFO/TDEN, TCLKO/TGCLK, ROH, ROHCLK,
ROHSOF, RSER, RSOFO/RDEN, RCLKO/RGCLK) are driven low at global or port reset and should stay low until
after the port power-down PORT.CR1
processor port three-state output pins (D[15:0],
pin is active, but not when the GL.CR1
.PD and port data path reset PORT.CR1.RSTDP bits are cleared. The
RDY, INT) are forced into the high impedance state when the RST
.RST bit is active.
After reset, the device will be in the default configuration:: The latched status bits are enabled to be cleared on
write. The CLAD is disabled. The global 8KREF and one-second timers are disabled. The line interface is in B3ZS
mode and the LIU is disabled and the transmit line pins are also disabled. The frame mode is DS3 C-bit with
automatic downstream AIS on LOS or OOF is enabled and automatic RDI on LOF, LOS, SEF or AIS is enabled
and automatic FEBE is enabled. Transmit clock comes from the REFCLK pin. The pin inversion on all pins is
disabled.
Individual blocks are reset and powered down when not used determined by the settings in the line mode bits
PORT.CR2
65 of 233
.LM[2:0] and framer mode bits PORT.CR2.FM[2:0].
DS3170 DS3/E3 Single-Chip Transceiver
9.4 Global Resources
9.4.1 Clock Rate Adapter (CLAD)
The clock rate adapter is composed of a PLL block to create the internal clock which can be used for the transmit
clock and/or LIU reference clock from a clock input on the reference input (REFCLK) pin. The device needs one of
two (DS3 or E3) internal clock rates. The input reference clock frequency can be either 44.736, 34.368. 77.78,
51.84 or 19.44 MHz.
The receive LIU is supplied a reference clock from the CLAD. The receive LIU selects the clock frequency based
upon the mode the user selects via the FM bits. The CLAD output is also available as a transmit clock source if
selected via the PORT.CR2
The user must supply at least one of the five rates (44.736, 34.368. 77.78, 51.84 or 19.4 MHz) to the REFCLK pin.
The CLAD[2:0] bits informs the PLL of the frequency applied to the pins. Selection of the clock applied to the LIU
and optionally the transmitter is controlled by the FM bits (located in PORT.CR2
flexibility to the user. The user may supply any of the five clock rates and use the CLAD to convert the rate to the
particular clock rate needed for his application.
The CLAD PLL is enabled when the CLAD input reference clock is different from the clock required for the framing
mode. The CLAD PLL is disabled and the CLAD output clock is connected directly to the CLAD input clock
(REFCLK) when the framing mode requires the same clock as the CLAD input reference clock.
.CLADC register bit.
). The CLAD allows maximum
Table 9-11. CLAD Clock Source Settings
CLAD[2:0] REFCLK (INPUT)
000 44.736 MHz
001 34.368 MHz
010 51.84 MHz
011 19.44 MHz
100 77.76 MHz
101 Undefined
11X Undefined
9.4.2 8 kHz Reference Generation
The global 8KREF signal is used to generate the one second reference signal by dividing it by 8000. This signal
can be derived from almost any clock source on the chip as well as the general purpose IO pin GPIO4. The port
8KREF signal can be sourced from the transmit or receive clocks. The minimum input frequency stability of the
8KREF input pin is +/- 500 ppm.
The global 8KREF signal can come from an external 8000 Hz reference connected to the GPIO4 general purpose
IO pin by setting the GL.CR2
pin when the GL.CR2
The global 8KREF signal can be derived from the CLAD PLL or pins or come from any of the port 8KREF signals
by clearing GL.CR2
.G8KOS bit is set.
.G8KIS bit and selecting the source using the GL.CR2.G8KRS[2:0] bits.
.G8KIS bit. The global 8KREF signal can be output on the GPIO2 general purpose IO
The port 8KREF signal can be derived from the transmit clock input pin or from the receive LIU or input clock pin.
The PORT.CR3.
The 8KREF 8.000 kHz signal is a simple divisor of 44736 kHz (DS3 divided by 5592) or 33368 kHz (E3 divided by
4296). The correct divisor for the port 8KREF source is selected by the mode the port is configured for. The CLAD
clock chosen for the clock source selects the correct divisor for the global 8KREF. The 8KREF signal is only as
accurate as the clock source chosen to generate it.
Table 9-12
66 of 233
P8KRS[1:0] bits are used to select which source.
lists the selectable sources for global 8 kHz reference.
Table 9-12. Global 8 kHz Reference Source Table
DS3170 DS3/E3 Single-Chip Transceiver
GL.CR2.
G8KIS
GL.CR2.
G8KRS[1:0]
SOURCE
0 00 None, the 8KHZ divider is disabled.
0 01 Derived from CLAD output clock
0 10 8KREF source selected by P8KRS[1:0]
0 11 Undefined
1 XX GPIO4
Table 9-13
lists the selectable sources for port 8 kHz reference sources.
Table 9-13. Port 8 kHz Reference Source Table
PORT.CR3.P8KRS[1:0] SOURCE
0X Undefined
10 Internal receive framer clock
11 Internal transmit framer clock
Figure 9-6 shows the 8 kHz reference logic tree.
Figure 9-6. 8KREF Logic
FRAME MODE
FROM CLAD
G8KRS
DS3 CLK
E3 CLK
CLOCK DIVIDER
G8KIS
GLOBAL 8KREF
GPIO4
P8KRS
RX CLOCK
TX CLOCK
CLOCK DIVIDER
PORT 8KREF
FRAME MODE
9.4.3 One Second Reference Generation
The one second reference signal is used as an option to update the performance registers on a precise one
second interval. The generated internal signal should be about 50% duty cycle and it is derived from the Global 8
kHz reference signal by dividing it by 8000. The low to high edge on this signal will set the GL.SRL
one second detect bit which can generate an interrupt when the GL.SRIE
low to high edge can also be used to generate performance monitor updates when GL.CR1
.ONESIE interrupt enable bit is set. The
.GPM[1:0]=1X.
.ONESL latched
67 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9.4.4 General-Purpose IO Pins
There are eight general-purpose IO pins that can be used for general IO, global signals and framer alarm signals.
Each pin is independently configurable to be a general-purpose input, general-purpose output, global signal or
framer alarm. Two of the GPIO pins can be programmed to output one or two framer alarm statuses. One of the
two pins assigned to framer alarms can be programmed as global input or output signals. When the port is
powered down or reset and GL.GIOCR
TMEI, and PMU signals that can be sourced by the GPIO pin will be driven low into the core logic when the GPIO
pin is not selected for the source of the signal.
.GPIOx[1:0] = 01, the GPIO pin will be an output driving low. The 8KREFI,
Table 9-14
lists the purpose and control thereof of the General-Purpose IO Pins.
Table 9-14. GPIO Global Signals
PIN GLOBAL SIGNAL CONTROL BIT
GPIO2 8KREFO output GL.CR2.G8KOS
GPIO4 8KREFI input GL.CR2.G8KIS
GPIO6 TMEI input GL.CR1.MEIMS
GPIO8 PMU input GL.CR1.GPM[1:0]
Table 9-15 describes the selection of mode for the GPIO Pins.
Table 9-15. GPIO Pin Global Mode Select Bits
GL.GIOCR.GPIOSx GPIO PIN MODE
00 Input
01
10 Output logic 0
11 Output logic 1
x = A or B, valid when a GPIO pin is not selected for a global signal
Framer alarm status selected
by port GPIO
Table 9-16
located in the PORT.CR4
68 of 233
lists the various port alarm monitors that can be output on the GPIO pins. The GPIO(A/B)[3:0] bits are
Register.
Table 9-16. GPIO Port Alarm Monitor Select
PORT.CR4
GPIO(A/B)[3:0]
LINE LOS
DS3/E3 OOF
DS3/E3 LOF
DS3/E3 AIS
DS3/E3 RAI
DS3 IDLE
0000 X
0001 X
0010 X
0011 X
0100 X
0101 X
0110
0111
1000
1001
1010
1011 X X X
1100
1101 X X X
1110 X X
1111 X X X X X X
DS3170 DS3/E3 Single-Chip Transceiver
9.4.5 Performance Monitor Counter Update Details
The performance monitor counters are designed to count at least one second of events before saturating to the
maximum count. There is a status bit associated with some of the performance monitor counters that is set when
the its counter is greater than zero, and a latched status bit that gets set when the counter changes from zero to
one. There is also a latched status bit that gets set on every event that causes the error counter to increment.
There is a read register for each performance monitor counter. The count value of the counter gets loaded into this
register and the counter is cleared when the update-clear operation is performed. If there is an event to be counted
at the exact moment (clock cycle) that the counter is to be cleared then the counter will be set to a value of one so
that that event will be counted.
The Performance Monitor Update signal affects the counter registers of the following blocks: the BERT, the DS3/E3
framer, the Line Encoder/Decoder.
The update-clear operation is controlled by the Performance Monitor Update signal (PMU). The update-clear
operation will update the error counter registers with the value of the error counter and also reset each counter.
The PMU signal can be created in hardware or software. The hardware sources can come from the one second
counter or one of the general-purpose IO pins, which can be programmed to source this signal. The software
sources can come from one of the port control register bits or one of the global control register bits. When using the
software update method, the PMU control bit should be set to initiate the process and when the PMS status bit gets
set, the PMU control bit should be cleared making it ready for the next update. When using the hardware update
method, the PMS bit will be set shortly after the hardware signal goes high, and cleared shortly after the hardware
signal goes low. The latched PMS signal can be used to generate an interrupt for reading the count registers. If the
port is not configured for global PMU signals, the PMS signal from that port should be blocked from affecting the
global PMS status.
69 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Figure 9-7. Performance Monitor Update Logic
PORT.CR1.PMUM
PORT.CR1.PMU
GL.CR1.GPMU
GPIO8(GPMU) PIN
ONE SEC
GL.CR1.GPM
00
01
1X
0
1
9.4.6 Transmit Manual Error Insertion
Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register bits in
the functional blocks, using the global GL.CR1
pin configured for TMEI mode.
There is a transmit error insertion register in the functional blocks that allow error insertion. The MEIMS bit controls
whether the error is inserted using the bits in the error insertion register or using error insertion signals external to
that block. When bit MEIMS=0, errors are inserted using other bits in the transmit error insertion register. When bit
MEIMS=1, errors are inserted using a signal generated in the port or global control registers or using the external
GPIO6 pin configured for TMEI operation.
other port counters
GL.SR.GPMS
PMU PMS
PERF
COUNTER
GTZ
.TMEI bit, using the port PORT.CR1.TMEI bit, or by using the GPIO6
PORT.SR.PMS
70 of 233
Figure 9-8. Transmit Error Insert Logic
BERT.TEICR.MEIMS
DS3170 DS3/E3 Single-Chip Transceiver
PORT.CR.MEIMS
PORT.CR.TMEI
GL.CR1.MEIMS
GL.CR1.TMEI
GPIO6 PIN
(TMEI)
BERT.TEICR error
0
1
0
1
insertion bit
T3.TEIR error
insertion bit
0
BERT ERROR
INSERT
1
T3.TEIR.MEIMS
0
T3 ERROR
INSERT
1
0
1
9.5 Port Resources
9.5.1 Loopbacks
There are several loop back paths available. The following table lists the loopback modes available for analog
loopback (ALB), line loopback (LLB), payload loopback (PLB) and diagnostic loopback (DLB). The LBM bits are
located in PORT.CR4.
Table 9-17. Loopback Mode Selections
LBM[2:0] ALB LLB PLB DLB
000 0 0 0 0
001 1 0 0 0
010 0 1 0 0
011 0 0 1 0
10X 0 0 0 1
110 0 1 0 1
111 0 0 0 1
71 of 233
Figure 9-9
highlights where each loopback mode is located and gives an overall view of the various loopback paths
available.
Figure 9-9. Loopback Modes
TUA1
DS3170 DS3/E3 Single-Chip Transceiver
TAIS
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
DLB
DS3 / E3
Transmit
Formatter
Trail
FEAC
Trace
Buffer
DS3 / E3
Receive
Framer
IEEE P1149.1
JTAG Test
Access Port
HDLC
UA1
GEN
TX BERT
PLB
RX BERT
Microprocessor
Interface
9.5.1.1 Analog Loopback (ALB)
Analog loopback is enabled by setting PORT.CR4
when the port is configured for loop timed mode (set via the PORT.CR3
.LBM[2:0] = 001. Analog loopback mode will not be enabled
.LOOPT bit).
The analog loopback is a loopback as close to the pins as possible. When both the Tx and RX LIU is enabled, it
loops back TXP and TXN to RXP and RXN, respectively. If the transmit signals on TXP and TXN are not
terminated properly, this loopback path may have data errors or loss of signal. When the LIU is not enabled, it
loops back TLCLK,TPOS / TDAT,TNEG to RLCLK, RPOS / RDAT , RNEG.
Figure 9-10. ALB Mux
TXP
TXN
RXP
RXN
72 of 233
TX
LIU
RX
LIU
9.5.1.2 Line Loopback (LLB)
DS3170 DS3/E3 Single-Chip Transceiver
Line loopback is enabled by setting PORT.CR4
.LBM[2:0] = X10. DLB and LLB are enabled at the same time when
LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010.
The clock from the receive LIU or the RLCLK pin will be output to the transmit LIU or TCLKO pin. The POS and
NEG data from the receive LIU or the RPOS and RNEG pin will be sampled with the receive clock to time it to the
LIU or pin interface.
When LLB is enabled, unframed all ones AIS can optionally be automatically enabled on the receive data path.
This AIS signal will be output on the RSER pin in framed modes. When DLB and LLB is enabled, the AIS signal
will not be transmitted. See Figure 9-9
.
9.5.1.3 Payload Loopback (PLB)
Payload loopback is enabled by setting PORT.CR4
.LBM[2:0] = 011.
The payload loopback copies the payload data from the receive framer to the transmit framer which then re-frames
the payload before transmission. Payload loopback is operational in all framing modes.
When PLB is enabled, unframed all ones AIS transmission can optionally be automatically enabled on the receive
data path. This AIS signal will be output on the RSER. In all PLB modes, the TSOFI input pin is ignored.
The external transmit output pins TDEN and TSOFO/TDEN can optionally be disabled by forcing a zero when PLB
is enabled. See Figure 9-9
.
9.5.1.4 Diagnostic Loopback (DLB)
Diagnostic loopback is enabled by setting PORT.CR4
.LBM[2:0] = 1XX. DLB and LLB are enabled at the same time
when LBM[2:0] = 110, only DLB is enabled when LBM[2:0] = 10X or 111.
The Diagnostic loopback sends the transmit data, before line encoding, back to the receive side.
Transmit AIS can still be enabled using PORT.CR1
.LAIS[2:0] even when DLB is enabled. See Figure 9-9.
9.5.2 Loss Of Signal Propagation
The Loss Of Signal (LOS) is detected in the line decoder logic. In unipolar (UNI) line interface modes LOS is never
detected. The LOS signal from the line decoder is sent to the DS3/E3 framer and the top level payload AIS logic
except when DLB is activated. When DLB is activated the LOS signal to the framer and AIS logic is never active.
The LOS status in the line decoder status register is valid in all frame and loop back modes, though it is always off
in the line interface is in the UNI mode.
9.5.3 AIS Logic
There is AIS logic in both the framers and at the top level logic of the port. The framer AIS is enabled by setting the
TAIS bit in the appropriate framer transmit control register (T3, E3-G.751, E3-G.832, or Clear Channel). The top
level AIS is enabled by setting the PORT.CR1
ones pattern or a DS3 framed 101010… pattern depending on the FM[2:0] mode bits. The DS3 Framed Alarm
Indication Signal (AIS) is a DS3 signal with valid F-bits, M-bits, and P-bits (P
set to one, all C-bits (C
XY) are set to zero, and the payload bits are set to a 1010 pattern starting with a one
immediately after each overhead bit. The DS3 framed AIS pattern is only available in DS3 modes. The unframed
all ones pattern is available in all framing modes including the DS3 modes. The transmit line interface can send
both unframed all ones AIS and DS3 framed AIS patterns from either the AIS generator in the framer or the AIS
generator at the top level.
The AIS signal generated in the framer can be initiated and terminated without introducing any errors in the signal.
When the unframed AIS signal is initiated or terminated, there will be no BPV or CV errors introduced, but there will
be framing errors if a framed mode is enabled. When the DS3 framed AIS signal is initiated or terminated, in
addition to no BPV or CV errors, there should be no framing or P-bit (parity) or CP-bit errors introduced.
.LAIS[2:0] bits (see Table 9-18). The AIS signal is an unframed all
1 and P2). The X-bits (X1 and X2) are
The AIS signal generated at the top level will not generate BPV errors but may generate P-bit and CP-bit errors
when the signal is initiated and terminated. The framed DS3 AIS signal will not cause the far end receiver to resync when the signal is initiated, but it may cause a re-sync when terminated if the DS3 frame position in the
framer is changed while the DS3 AIS signal is being generated. A sequence of events can be executed which will
enable the initiation and termination of DS3 AIS or unframed all ones at the top level without any errors introduced.
73 of 233
DS3170 DS3/E3 Single-Chip Transceiver
The sequence will only work when the automatic AIS generation is not enabled. CV and P-bit errors can occur
when AIS is automatically generated and can not be avoided. This sequence to generate an error free DS# AIS at
the top level is to have the DS3 AIS or unframed all ones signal initiate in the DS3 framer, and a few frames sent
before initiating or terminating the DS3 AIS or unframed all ones at the top level. After the top level AIS signal is
activated, the AIS signal in the framer can be terminated, DLB activated and diagnostic patterns generated. The
DS3 AIS signal generated at the top level will not change frame alignment after starting even if the DS3 frame
position in the framer is changed.
The transmit line AIS generator at the top level can generate AIS signals even when the framer is looped back
using DLB, but not when the line is looped back using LLB. The AIS signal generated in the framer will be looped
back to the receive side when DLB is activated.
The receive framer can detect both unframed all ones AIS and DS3 framed AIS patterns. When in DS3 framing
modes, both framed DS3 AIS and unframed all ones can be detected. In E3 framing modes E3 AIS, which is
unframed all ones, is detected.
The receive payload interface going to the RSER pin or the BERT logic can have an unframed all ones AIS signal
replacing the receive signal, this is called Payload AIS. The all ones AIS signal is generated from either the
DS3/E3 framer or the downstream top level unframed all ones AIS generator. The unframed all ones AIS signal
generated in the framer will be looped back to the transmit side when PLB is activated. The unframed all ones AIS
signal generated at the top level will be sent to the RSER pin and other receive logic, but not to the transmit side
while PLB is activated. The top level AIS generator is used when a downstream AIS signal is desired while
payload loop back is activated and is enabled by default after rest and must be cleared during configuration. Note
that the downstream AIS circuit in the framer, when a DS3 mode is selected, enforces the OOF to be active for 2.5
msec before activating when automatic AIS in the framer is enabled. The top level downstream AIS will be
generated with no delay when OOF is detected when automatic AIS at the top level is enabled.
There is no detection of any AIS signal on the transmit payload signal from the TSER pin or anywhere on the
transmit data path.
The transmit AIS generator at the top level can also be activated with a software bit or automatically when DLB is
activated. The receive AIS generator in the framer can be activated with a software bit, and automatically when
AIS, LOS or OOF are detected. The receive payload AIS generator at the top level can be activated with a software
bit or automatically when LOS, DS3/E3 OOF, LLB, or PLB is activated.
Figure 9-11
shows the AIS signal flow through the device.
Figure 9-11. AIS Signal Flow
TRANSMIT
PAYLOAD
SYSTEM/
TRUNK SIDE
RECEIVE
PAYLOAD
TRANSMIT
LINE
LINE/TRIBUTARY
SIDE
RECEIVE
LINE
LLB
FRAMER
optional
0
1
B3ZS/
HDB3
encoder
optional
B3ZS/
HDB3
decoder
0
1
TAIS
DS3/
UA1
AIS
TSOFO
1
0
DLB
0
1
TAIS
DS3/UA1
AIS
detector
UA1
AIS
DS3/
UA1
AIS
DAIS
0
1
PLB
0
1
UA1
0
1
DAIS
AIS
74 of 233
Table 9-18
lists the LAIS decodes for various line AIS enable modes.
Table 9-18. Line AIS Enable Modes
DS3170 DS3/E3 Single-Chip Transceiver
LAIS[1:0]
PORT.CR1
00
00 E3 Automatic AIS when DLB is enabled UA1
01 Any Send UA1 UA1
10 DS3 Send AIS DS3AIS
10 E3 Send AIS UA1
11 Any Disable none
Table 9-19 lists the PAIS decodes for various payload AIS enable modes.
FRAME MODE DESCRIPTION AIS CODE
DS3
Automatic AIS when DLB is enabled
(PORT.CR4
.LBM = 1XX)
DS3AIS
Table 9-19. Payload (Downstream) AIS Enable Modes
PAIS[2:0]
PORT.CR1
000 Always UA1
001 When LLB (no DLB) active UA1
010 When PLB active UA1
011 When LLB(no DLB) or PLB active UA1
WHEN AIS IS SENT AIS CODE
100 When LOS (no DLB) active UA1
101 When OOF active UA1
110 When OOF, LOS. LLB (no DLB), or
PLB active
111 Never none
UA1
9.5.4 Loop Timing Mode
Loop timing mode is enabled by setting the PORT.CR3.LOOPT bit. This mode replaces the clock from the TCLKI
pin with the internal receive clock from either the RLCLK pin if the RX LIU is disabled, or the recovered clock from
the RX LIU if it is enabled. The loop timing mode can be activated in any framing or line interface mode.
9.5.5 HDLC Overhead Controller
The data signal to the receive HDLC controller will be forced to a one while still being clocked when the framer
(DS3, E3), to which the HDLC is connected, detects LOF or AIS. Forcing the data signal to all ones will cause an
HDLC packet abort if the data started to look like a packet instead of allowing a bad, and possibly very long, HDLC
packet.
9.5.6 Trail Trace
There is a single Trail Trace controller for use in line maintenance protocols. The E3-G.832 framer has access to
the trail trace controller.
9.5.7 BERT
There is a Bit Error Rate Test (BERT) circuit for use in generating and detecting test signals in the payload bits.
The BERT can generate and detect PRBS patterns up to 2^32-1 bits as well as repeating patterns up to 32 bits
75 of 233
DS3170 DS3/E3 Single-Chip Transceiver
long. The generated BERT signal replaces the data on the TSER pin in framed modes when the BERT is enabled
by setting the PORT.CR1.BENA.
When the BERT is enabled The TDEN and RDEN pins will still be active but the data on the TSER pin will be
discarded.
9.5.8 System Port Pins
The system port pins have multiple functions based on the framing mode the device is in as well as other pin mode
select bits.
9.5.8.1 Transmit System Port Pins
The transmit system pins are TSOFI, TSER, TSOFO / TDEN, and TCLKO / TGCLK. They have different functions
based on the framing mode and other pin mode bits. Unused input pin functions should drive a logic zero into the
device circuits expecting a signal from that pin. The control bits that configure the pins’ modes are
PORT.CR2
.FM[2:0], PORT.CR3.TPFPE, PORT.CR3.TSOFOS and PORT.CR3.TCLKS.
Table 9-20
pins.
to Table 9-22 describe the function selected by the FM bits and other pin mode bits for the multiplexed
Table 9-20. TSOFI Input Pin Functions
FM[2:0]
PORT.CR2
0XX (FRM) TSOFI
1XX (UFRM) Not used
PIN
FUNCTION
Table 9-21. TSOFO/TDEN/Output Pin Functions
FM[2:0]
PORT.CR2
0XX (FRM) 0 TDEN
0XX (FRM) 1 TSOFO
1XX (UFRM) X High
TSOFOS
PORT.CR3
PIN
FUNCTION
Table 9-22 TCLKO/TGCLK Output Pin Functions
FM[2:0]
PORT.CR2
TCLKS
PORT.CR3
PIN
FUNCTION
GAP SOURCE
0XX (FRM) 0 TGCLK TDEN
0XX (FRM) 1 TCLKO none
1XX (UFRM) X TCLKO none
9.5.8.2 Receive System Port Pins
The receive system pins are RSER, RSOFO / RDEN and RCLKO / RGCLK. They have different functions based
on the framing mode and other pin mode bits. Unused input pin functions should drive a logic zero into the device
circuits expecting a signal from that pin. The control bits that configure these pins are PORT.CR2
PORT.CR3
Table 9-23
pins.
76 of 233
.RPFPE, PORT.CR3.RSOFOS and PORT.CR3.RCLKS.
to Table 9-24 describe the function selected by the FM bits and other pin mode bits for the multiplexed
.FM[2:0],
Table 9-23. RSOFO/RDEN Output Pin Functions
DS3170 DS3/E3 Single-Chip Transceiver
FM[2:0]
PORT.CR2
0XX (FRM) 0 RDEN
0XX (FRM) 1 RSOFO
1XX (UFRM) X High
RSOFOS
PORT.CR3
PIN
FUNCTION
Table 9-24. RCLKO/RGCLK Output Pin Functions
FM[2:0]
PORT.CR2
0XX (FRM) 0 RGCLK RDEN
0XX (FRM) 1 RCLKO none
1XX (UFRM) X RCLKO none
RCLKS
PORT.CR3
9.5.9 Framing Modes
The framing modes are selected independently of the line interface modes using the PORT.CR2.FM[2:0] control
bits. Different blocks are used in different framing modes. The bit error test (BERT) function can be enabled in any
mode. The LIU, JA and line encoder/decoder blocks are selected by the line mode (LM[2:0]) code.
PIN
FUNCTION
GAP SOURCE
Table 9-25. Framing Mode Select Bits FM[2:0]
FM[2:0] DESCRIPTION LINE CODE FIGURE
0 00 DS3 C-bit Framed B3ZS/AMI/UNI Figure 6-1
0 01 DS3 M23 Framed B3ZS/AMI/UNI Figure 6-1
0 10 E3 G.751 Famed HDB3/AMI/UNI Figure 6-1
0 11 E3 G.832 Framed HDB3/AMI/UNI Figure 6-1
1 00 DS3 Unframed B3ZS/AMI/UNI Figure 6-2
1 01 Undefined ---
1 10 E3 Unframed HDB3/AMI/UNI Figure 6-2
1 11 Undefined ---
9.5.10 Line Interface Modes
The line interface modes can be selected semi-independently of the framing modes using the PORT.CR2.LM[2:0]
control bits. The major blocks controlled are the transmit LIU (Tx LIU), receive LIU (RX LIU), jitter attenuator (JA)
and the line encoder/decoder. The line encoder/decoder is used for B3ZS, HDB3 and AMI line interface encoding
modes. The line encoder-decoder block is not used for line encoding or decoding in the UNI mode but the BPV
counter in it can be used to count external pulses on the RNEG / RCLV pin. The jitter attenuator (JA) can be off
(OFF) or put in either the transmit (Tx) or receive (RX) path with the Tx LIU or RX LIU. Both Tx LIU and RX LIU can
be enabled (ON) or disabled (OFF).
The “Analog Loop Back” (ALB) is available when the LIU is enabled or disabled. It is an actual loop back of the
analog positive and negative pulses from the TX LIU to the RX LIU when the LIU is enabled. If the LIU is disabled,
It is a digital loop back of the TLCLK, TPOS, TNEG signals to the RLCLK, RPOS and RNEG signals.
When the line is configured for B3ZS/HDB3/AMI line codes, the line codes are determined by the framing mode
and the AMI line mode selection is controlled by the TZCDS and RZCDS bits in the line encoder/decoder blocks.
The DS3 modes select the B3ZS line coding, the E3 modes select the HDB3 line codes. Refer to Table 9-26
configuration.
for
77 of 233
Table 9-26. Line Mode Select Bits LM[2:0]
DS3170 DS3/E3 Single-Chip Transceiver
LINE.TCR.TZSD &
LINE.RCR
.RZSD
0 000 B3ZS/HDB3 OFF OFF
0 001 B3ZS/HDB3 ON OFF
0 010 B3ZS/HDB3 ON TX
0 011 B3ZS/HDB3 ON RX
1 000 AMI OFF OFF
1 001 AMI ON OFF
1 010 AMI ON TX
1 011 AMI ON RX
X 1XX UNI OFF OFF
LM[2:0]
(PORT.CR2
Line Code LIU JA
)
78 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9.6 DS3/E3 Framer / Formatter
9.6.1 General Description
The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the
DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates
framing, inserts DS3/E3 overhead, and outputs a unipolar DS3/E3 signal in the transmit direction.
The Receive DS3/E3 Framer receives a DS3/E3 signal from the Receive LIU or RDAT (or RPOS and RNEG),
determines the frame alignment, extracts the DS3/E3 overhead, and outputs the payload with frame and overhead
The Transmit DS3/E3 Formatter receives a DS3/E3 payload on TSER, generates a DS3/E3 frame, optionally
inserts DS3/E3 overhead, and transmits the DS3/E3 signal.
Refer to Figure 9-12
for the location of the DS3/E3 Framer/Formatter blocks in the DS3170.
Figure 9-12. Framer Detailed Block Diagram
TAIS
TUA1
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
DLB
DS3 / E3
Transmit
Formatter
Trail
FEAC
Trace
Buffer
DS3 / E3
Receive Framer
IEEE P1149.1
JTAG Test
Access Port
HDLC
UA1
GEN
TX BERT
RX BERT
PLB
Microprocessor
Interface
9.6.2 Features
9.6.2.1 Transmit Formatter
· Programmable DS3 or E3 formatter – Accepts a DS3 (M23 or C-bit) or E3 (G.751 or G.832) signal and
performs DS3/E3 overhead generation.
· Arbitrary framing format support – Generates a signal with an arbitrary framing format. The line
overhead/stuff periods are added into the data stream using an overhead mask signal.
· Generates alarms and errors – DS3 alarm conditions (AIS, RDI, and Idle) and errors (framing, parity, and
FEBE), or E3 alarm conditions (AIS and RDI/RAI) and errors (framing, parity, and REI) can be inserted into the
outgoing data stream.
· Externally controlled serial DS3/E3 overhead insertion port – Can insert all DS3 or E3 overhead via a
serial interface. DS3/E3 overhead insertion is fully controlled via the serial overhead interface.
· HDLC overhead insertion – An HDLC channel can be inserted into the DS3 or E3 data stream.
· FEAC insertion – A FEAC channel can be inserted into the DS3 or E3 data stream.
· Trail Trace insertion – Inputs and inserts the G.832 E3 TR byte.
9.6.2.2 Receive Framer
· Programmable DS3 or E3 framer – Accepts a DS3 (M23 or C-bit) or E3 (G.751 or G.832) signal and performs
DS3/E3 overhead termination.
79 of 233
DS3170 DS3/E3 Single-Chip Transceiver
· Arbitrary framing format support – Accepts a signal with an arbitrary framing format. The Line overhead/stuff
periods are removed from the data stream using an overhead mask signal.
· Detects alarms and errors – Detects DS3 alarm conditions (SEF, OOMF, OOF, LOF, COFA, AIS, AIC, RDI,
and Idle) and errors (framing, parity, and FEBE), or E3 alarm conditions (OOF, LOF, COFA, AIS, and RDI/RAI)
and errors (framing, parity, and REI).
· Serial DS3/E3 overhead extraction port – Extracts all DS3 or E3 overhead and outputs it on a serial
interface.
· HDLC overhead extraction – An HDLC channel can be extracted from the DS3 or E3 data stream.
· FEAC extraction – A FEAC channel can be extracted from the DS3 or E3 data stream.
· Trail Trace extraction – Extracts and outputs the G.832 E3 TR byte.
9.6.3 Transmit Formatter
The Transmit Formatter receives a DS3 or E3 data stream and performs framing generation, error insertion,
overhead insertion, and AIS/Idle generation for C-bit DS3, M23 DS3, G.751 E3, or G.832 E3 framing protocols.
The bits in a byte are transmitted MSB first, LSB last. When they are input serially, they are input in the order they
are to be transmitted. The bits in a byte in an outgoing signal are numbered in the order they are transmitted, 1
(MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7),
and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a byte in a register and the
corresponding byte in a signal.
9.6.4 Receive Framer
The Receive Framer receives the incoming DS3,or E3, ine/tributary data stream, performs appropriate framing, and
terminates and extracts the associated overhead bytes.
The Receive Framer processes a C-bit format DS3, M23 format DS3, G.751 format E3, or G.832 format E3 data
stream, performing framing, performance monitoring, overhead extraction, and generates downstream AIS, if
necessary.
The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB
last. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8 (LSB).
However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7), and the LSB is
stored in the lowest numbered bit (0). This is to differentiate between a byte in a register and the corresponding
byte in a signal.
Some bits, bit groups, or bytes (data) are integrated before being stored in a register. Integration requires the data
to have the same new data value for five consecutive occurrences before the new data value will be stored in the
data register. Unless stated otherwise, integrated data may have an associated unstable indication. Integrated data
is considered unstable if the received data value does not match the currently stored (integrated) data value or the
previously received data value for eight consecutive occurrences. The unstable condition is terminated when the
same value is received for five consecutive occurrences.
9.6.4.1.1 Receive DS3 Framing
DS3 framing determines the DS3 frame boundary. In order to identify the DS3 frame boundary, first the subframe
boundary must be found. The subframe boundary is found by identifying the subframe alignment bits F
and F
, which have a value of one, zero, zero, and one respectively. See Figure 9-13. Once the subframe
X4
, FX2, FX3,
X1
boundary is found, the multiframe frame boundary can be found. The multiframe boundary is found by identifying
the multiframe alignment bits M
, M2, and M3, which have a value of zero, one, and zero respectively. The DS3
1
framer is an off-line framer that only updates the data path frame counters when either an out of frame (OOF) or an
out of multiframe (OOMF) condition is present. The use of an off-line framer reduces the average time required to
reframe, and reduces data loss caused by burst error. The DS3 framer has a Maximum Average Reframe Time
(MART) of approximately 1.0 ms.
80 of 233
Figure 9-13. DS3 Frame Format
DS3170 DS3/E3 Single-Chip Transceiver
X
X
P
P
M
M
M
1
2
1
2
1
2
3
F
11
F
21
F
31
F
41
F
51
F
61
F
71
C
11
C
21
C
31
C
41
C
51
C
61
C
71
F
12
F
22
F
32
F
42
F
52
F
62
F
72
C
12
C
22
C
32
C
42
C
52
C
62
C
72
F
13
F
23
F
33
F
43
F
53
F
63
F
73
C
13
C
23
C
33
C
43
C
53
C
63
C
73
F
14
F
24
F
34
F
44
F
54
F
64
F
74
7 SubFrames
680 Bits
The subframe framer continually searches four adjacent bit positions for a subframe boundary. A subframe
alignment bit (F-bit) checker checks each bit position. All four bit positions must fail before any other bit positions
are checked for a subframe boundary. There are 170 possible bit positions that must be checked, and four
positions are checked simultaneously. Therefore up to 43 checks may be needed to identify the subframe
boundary. The subframe framer enables the multiframe frame once it has identified a subframe boundary. Refer to
Figure 9-14
for the subframe framer state diagram.
Figure 9-14. DS3 Subframe Framer State Diagram
Sync
A
l
l
r
o
d
e
l
i
a
f
s
n
o
e
i
t
v
i
s
s
t
o
i
p
b
-
t
i
F
b
6
3
1
All 4 bit positions failed
d
e
i
f
i
r
4
b
i
t
p
o
s
i
t
i
o
n
s
f
a
i
l
e
d
LoadVerify
2 F-bits loaded
The multiframe framer checks for a multiframe boundary. When the multiframe framer identifies a multiframe
boundary, it updates the data path frame counters if either an OOF or OOMF condition is present. The multiframe
framer waits until a subframe boundary has been identified. Then, each bit position is checked for the multiframe
81 of 233
DS3170 DS3/E3 Single-Chip Transceiver
boundary. The multiframe boundary is found by identifying the three multiframe alignment bits (M-bits). Since there
are seven multiframe bits and three bits are required to identify the multiframe boundary, up to 9 checks may be
needed to find the multiframe boundary. Once the multiframe boundary is identified, it is checked in each
subsequent frame. The data path frame counters are updated if the three multiframe alignment bits are error free,
and an OOF or OOMF condition exists. If the multiframe framer checks more than fifteen multiframe bit (X-bits, Pbits, and M-bits) positions without identifying the multiframe boundary, the multiframe framer times out, and forces
the subframe framer back into the load state. Refer to Figure 9-15
for the multiframe framer state diagram.
9.6.4.1.2 Receive DS3 Performance Monitoring
Performance monitoring checks the DS3 frame for alarm conditions and errors. The alarm conditions detected are
OOMF, OOF, SEF, LOF, COFA, LOS, AIS, Idle, RUA1, and RDI. The errors accumulated are framing, P-bit parity,
C-bit parity (C-bit format only), and Far-End Block Error (FEBE) (C-bit format only) errors.
An Out Of MultiFrame (OOMF) condition is declared when a multiframe alignment bit (M-bit) error has been
detected in two or more of the last four consecutive DS3 frames, or when a manual resynchronization is requested.
An OOMF condition is terminated when no M-bit errors have been detected in the last four consecutive DS3
frames, or when the DS3 framer updates the data path frame counters. Refer to Figure 9-15
for the multiframe
framer state diagram.
Figure 9-15. DS3 Multiframe Framer State Diagram
Sync
M
-
b
i
d
e
i
f
i
t
n
e
d
i
s
t
i
b
-
M
r
o
r
r
e
t
i
b
-
M
Timeout
t
e
r
r
o
r
a
n
d
t
i
m
e
o
u
t
LoadVerify
2 multiframe loaded
If multiframe alignment OOF is disabled, an Out Of Frame (OOF) condition is declared when three or more out of
the last sixteen consecutive subframe alignment bits (F-bits) have been errored, or a manual resynchronization is
requested. If multiframe alignment OOF is enabled, an OOF condition is declared when three or more out of the
last sixteen consecutive F-bits have been errored, when an OOMF condition is declared, or when a manual
resynchronization is requested. If multiframe alignment OOF is disabled, an OOF condition is terminated when
none of the last sixteen consecutive F-bits has been errored, or when the DS3 framer updates the data path frame
counters. If multiframe alignment OOF is enabled, an OOF condition is terminated when an OOMF condition is not
active and none of the last sixteen consecutive F-bits has been errored, or when the DS3 framer updates the data
path frame counters. Multiframe alignment OOF is programmable (on or off).
A Severely Errored Frame (SEF) condition is declared when three or more out of the last sixteen consecutive F-bits
have been errored, or when a manual resynchronization is requested. An SEF condition is terminated when an
OOF condition is absent.
82 of 233
DS3170 DS3/E3 Single-Chip Transceiver
A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active for a total of T
ms. The LOF integration counter is active (increments count) when an OOF condition is present, it is inactive (holds
count) when an OOF condition is absent, and it is reset when an OOF condition is absent for T continuous ms. T is
programmable (0, 1, 2, or 3). An LOF condition is terminated when an OOF condition is absent for T continuous
ms.
A Change Of Frame Alignment (COFA) is declared when the DS3 framer updates the data path frame counters
with a frame alignment that is different from the current data path DS3 frame alignment.
A Loss Of Signal (LOS) condition is declared when the B3ZS encoder is active, and it declares an LOS condition.
An LOS condition is terminated when the B3ZS encoder is inactive, or it terminates an LOS condition.
An Alarm Indication Signal (AIS) is a DS3 signal with valid F-bits and M-bits. The X-bits (X
the P-bits (P
and P2) are set to zero, all C-bits (CXY) are set to zero, and the payload bits are set to a 1010 pattern
1
and X2) are set to one,
1
starting with a one immediately after each DS3 overhead bit. An AIS signal is present when a DS3 frame is
received with valid F-bits and M-bits, both X-bits set to one, both P-bits set to zero, all C-bits set to zero, and all but
seven or fewer payload data bits matching the DS3 overhead aligned 1010 pattern. An AIS signal is absent when a
DS3 frame is received that does not meet the aforementioned criteria for an AIS signal being present. The AIS
integration counter declares an AIS condition when it has been active for a total of 10 to 17 DS3 frames. The AIS
integration counter is active (increments count) when an AIS signal is present, it is inactive (holds count) when an
AIS signal is absent, and it is reset when an AIS signal is absent for 10 to 17 consecutive DS3 frames. An AIS
condition is terminated when an AIS signal is absent for 10 to 17 consecutive DS3 frames.
A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less
zeros are detected and an OOF condition is continuously present . A RUA1 condition is terminated if in each of 4
consecutive 2047 bit windows, six or more zeros are detected or an OOF condition is continuously absent.
An Idle Signal (Idle) is a DS3 signal with valid F-bits, M-bits, and P-bits (P
to one, C
, C32, and C33 are set to zero, and the payload bits are set to a 1100 pattern starting with 11 immediately
31
and P2). The X-bits (X1 and X2) are set
1
after each overhead bit. In C-bit mode, an Idle signal is present when a DS3 frame is received with valid F-bits, Mbits, and P-bits, both X-bits set to one, C
, C32, and C33 set to zero, and all but seven or fewer payload data bits
31
matching the T3 overhead aligned 1100 pattern. In M23 mode, an Idle signal is present when a T3 frame is
received with valid F-bits, M-bits, and P-bits, both X-bits set to one, and all but seven or fewer payload data bits
matching the overhead aligned 1100 pattern. An Idle signal is absent when a DS3 frame is received that does not
meet aforementioned criteria for an Idle signal being present. The Idle integration counter declares an Idle
condition when it has been active for a total of 10 to 17 DS3 frames. The Idle integration counter is active
(increments count) when an Idle signal is present, it is inactive (holds count) when an Idle signal is absent, and it is
reset when an Idle signal is absent for 10 to 17 consecutive DS3 frames. An Idle condition is terminated when an
Idle signal is absent for 10 to 17 consecutive DS3 frames.
A Remote Defect Indication (RDI) condition (also called a far-end SEF/AIS defect condition) is declared when four
consecutive DS3 frames are received with the X-bits (X
and X2) set to zero. An RDI condition is terminated when
1
four consecutive DS3 frames are received with the X-bits set to one.
A DS3 Framing Format Mismatch (DS3FM) condition is declared when the DS3 format programmed (M13, C-bit)
does not match the incoming DS3 signal framing format. A DS3FM condition is terminated when the incoming
DS3 signal framing format is the same format as programmed. Framing errors are determined by comparing F-bits
and M-bits to their expected values. The type of framing errors accumulated is programmable (OOFs, F & M, F, or
M). An OOF error increments the count whenever an OOF condition is first detected . An F & M error increments
the count once for each F-bit or M-bit that does not match its expected value (up to 31 per DS3 frame). An F error
increments the count once for each F-bit that does not match its expected value (up to 28 per DS3 frame). An M
error increments the count once for each M-bit that does not match its expected value (up to 3 per DS3 frame).
P-bit parity errors are determined by calculating the parity of the current DS3 frame (payload bits only), and
comparing the calculated parity to the P-bits (P
match P
or P2, a single P-bit parity error is declared.
1
and P2) in the next DS3 frame. If the calculated parity does not
1
C-bit parity errors (C-bit format only) are determined by calculating the parity of the current DS3 frame (payload bits
only), and comparing the calculated parity to the C-bits in subframe three (C
If the calculated parity does not match C
, C32, or C33, a single C-bit parity error is declared.
31
, C32, and C33) in the next DS3 frame.
31
83 of 233
DS3170 DS3/E3 Single-Chip Transceiver
FEBE errors (C-bit format only) are determined by the C-bits in subframe four (C
, C42, and C43). A value of 111
41
indicates no error and any other value indicates an error.
The receive alarm indication (RAI) bit will be set high in the transmitter when one or more of the indicated alarm
conditions is present, and low when all of the indicated alarm conditions are absent. Setting the receive alarm
indication on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The Application Identification Channel (AIC) is stored in a register bit. It is determined from the C
set to one (C-bit format) if the C
format) if the C
bit is set to zero in four of the last thirty-one consecutive multiframes. Note: The stored AIC bit
11
bit is set to one in thirty-one consecutive multiframes. The AIC is set to zero (M23
11
bit. The AIC is
11
must not change when an LOS, OOF, or AIS condition is present.
A FEBE is transmitted by default upon reception of a DS3 frame in which a C-bit parity error or a framing error is
detected and counted.
9.6.5 C-bit DS3 Framer/Formatter
9.6.5.1 Transmit C-bit DS3 Frame Processor
The C-bit DS3 frame format is shown in Figure 9-13
.
Figure 9-13. DS3 Frame Format
X
1
X
2
P
1
P
2
F
11
F
21
F
31
F
41
C
11
C
21
C
31
C
41
F
12
F
22
F
32
F
42
C
12
C
22
C
32
C
42
F
13
F
23
F
33
F
43
C
13
C
23
C
33
C
43
F
14
F
24
F
34
F
44
7 SubFrames
M
1
M
2
M
3
Table 9-27
F
51
F
61
F
71
C
51
C
61
C
71
F
52
F
62
F
72
C
52
C
62
C
72
F
53
F
63
F
73
680 Bits
shows the function of each overhead bit in the DS3 Frame
C
53
C
63
C
73
F
54
F
64
F
74
84 of 233
Table 9-27. C-Bit DS3 Frame Overhead Bit Definitions
BIT DEFINITION
X1, X2 Remote Defect Indication
(RDI)
P1, P2 Parity Bits
M1, M2, and M3 Multiframe Alignment Bits
FXY Subframe Alignment Bits
C11 Application Identification
Channel (AIC)
C12 Reserved
C13 Far-End Alarm and Control
(FEAC) signal
C21, C22, and C23 Unused
C31, C32, and C33 C-bit parity bits
C41, C42, and C43 Far-End Block Error (FEBE)
bits
DS3170 DS3/E3 Single-Chip Transceiver
C51, C52, and C53 Path Maintenance Data Link
(or HDLC) bits
C61, C62, and C63 Unused
C71, C72, and C73 Unused
X1 and X2 are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P1 and P2 are
the parity bits used for line error monitoring. M
alignment bits. C
value of one. C
of one. C
, C32, and C33 are the C-bit parity bits used for path error monitoring. C41, C42, and C43 are the Far-End
31
is the Application Identification Channel (AIC). C12 is reserved for future network use, and has a
11
is the Far-End Alarm and Control (FEAC) signal. C21, C22, and C23 are unused, and have a value
13
Block Error (FEBE) bits used for remote path error monitoring. C
(or HDLC) bits. C
, C62, and C63 are unused, and have a value of one. C71, C72, and C73 are unused, and have a
61
, M2, and M3 are the multiframe alignment bits. FXY are the subframe
1
, C52, and C53 are the path maintenance data link
51
value of one. The X-bit, P-bit, M-bit, C-bit, and F-bit positions are overhead bits, and the other bit positions in the
T3 frame are payload bits regardless of how they are marked by TDEN.
9.6.5.2 Transmit C-bit DS3 Frame Generation
C-bit DS3 frame generation receives the incoming payload data stream, and overwrites all of the overhead bit
locations.
The multiframe alignment bits (M
, M2, and M3) are overwritten with the values zero, one, and zero (010)
1
respectively.
The subframe alignment bits (F
, FX2, FX3, and FX4) are overwritten with the values one, zero, zero, and one (1001)
X1
respectively.
The X-bits (X
and X2) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
1
programmable (automatic, 1, or 0). If the RDI is generated automatically, the X-bits are set to zero when one or
more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are
absent. Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
and P2) are both overwritten with the calculated payload parity from the previous DS3 frame. The
1
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
The bits C
The bit C
85 of 233
, C12, C21, C22, C23, C61, C62, C63, C71, C72, and C73 are all overwritten with a one.
11
is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller.
13
DS3170 DS3/E3 Single-Chip Transceiver
The bits C
The bits C
, C32, and C33 are all overwritten with the calculated payload parity from the previous DS3 frame.
31
, C42, and C43 are all overwritten with the Far-End Block Error (FEBE) bit. The FEBE bit can be
41
generated automatically or inserted from a register bit. The FEBE bit source is programmable (automatic or
register). If the FEBE bit is generated automatically, it is zero when at least one C-bit parity error has been detected
during the previous frame.
The bits C
, C52, and C53 are overwritten with the path maintenance data link input from the HDLC controller.
51
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on to error insertion. Frame generation is programmable
(on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
9.6.5.3 Transmit C-bit DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors, P-bit parity errors, C-bit parity errors, and Far-End Block Error (FEBE) errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe
alignment bit (F
error in all the subframe alignment bits in a subframe (F
alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
) error. An M-bit error is a single multiframe alignment bit (M1, M2, or M3) error. An SEF error is an
XY
, M2, or M3) error in two consecutive DS3 frames.
1
, FX2, FX3, and FX4). An OOMF error is a single multiframe
X1
and P2) in a single DS3 frame. P-bit parity
1
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
A C-bit parity error is generated by is inverting the value of the C
, C32, and C33 bits in a single DS3 frame. C-bit
31
parity error(s) can be inserted one error at a time, or continuously. The C-bit parity error insertion mode (single or
continuous) is programmable.
A FEBE error is generated by forcing the C
, C42, and C43 bits in a single multiframe to zero. FEBE error(s) can be
41
inserted one error at a time, or continuously. The FEBE error insertion rate (single or continuous) is programmable.
Each error type (framing, P-bit parity, C-bit parity, or FEBE) has a separate enable. Continuous error insertion
mode inserts errors at every opportunity. Single error insertion mode inserts an error at the next opportunity when
requested. the framing multi-error modes (SEF or OOMF) insert the indicated number of error(s) at the next
opportunities when requested; i.e., a single request will cause multiple errors to be inserted. The requests can be
initiated by a register bit(TSEI) or by the manual error insertion input (TMEI). The error insertion initiation type
(register or input) is programmable. The insertion of each particular error type is individually enabled. Once all error
insertion has been performed, the data stream is passed on to overhead insertion.
9.6.5.4 Transmit C-bit DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
, P1, P2, MX, FXY, and CXY can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
X
2
TOHSOF). The P-bits (P
and P2) and C31, C32, and C33 bits are received as an error mask (modulo 2 addition of
1
1
the input bit and the internally generated bit). The DS3 overhead insertion is fully controlled by the transmit
overhead interface. If the transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit
overhead signal (TOH) is inserted into the output data stream. Insertion of bits using the TOH signal overwrites
internal overhead insertion.
9.6.5.5 Transmit C-bit DS3 AIS/Idle Generation
C-bit DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the
data stream payload is forced to a 1100 pattern with two ones immediately following each DS3 overhead bit. M
M
, and M3 bits are overwritten with the values zero, one, and zero (010) respectively. FX1, FX2, FX3, and FX4 bits are
2
overwritten with the values one, zero, zero, and one (1001) respectively. X
, P
P
1
, C32, and C33 are overwritten with the calculated payload parity from the previous output DS3 frame.
2, C31
and X2 are overwritten with 11. And,
1
1
If transmit AIS is enabled, the data stream payload is forced to a 1010 pattern with a one immediately following
each DS3 overhead bit. M
F
, FX2, FX3, and FX4 bits are overwritten with the values one, zero, zero, and one (1001) respectively. X1 and X2
X1
are overwritten with 11. P
output DS3 frame. And, C
86 of 233
, M2, and M3 bits are overwritten with the values zero, one, and zero (010) respectively.
1
1
, P
X1
, C32, and C33 are overwritten with the calculated payload parity from the previous
2, C31
, CX2, and CX3 (X ¹ 3) are overwritten with 000. AIS will overwrite a transmit Idle signal.
,
,
9.6.5.5.1 Receive C-bit DS3 Frame Format
DS3170 DS3/E3 Single-Chip Transceiver
The DS3 frame format is shown in Figure 9-13
to as the far-end SEF/AIS bits). P
and P2 are the parity bits used for line error monitoring. M1, M2, and M3 are the
1
multiframe alignment bits that define the multiframe boundary. F
subframe boundary. Note: Both the M-bits and F-bits define the DS3 frame boundary. C
Identification Channel (AIC). C
Alarm and Control (FEAC) signal. C
is reserved for future network use, and has a value of one. C13 is the Far-End
12
, C22, and C23 are unused, and have a value of one. C31, C32, and C33 are the
21
C-bit parity bits used for path error monitoring. C
remote path error monitoring. C
are unused, and have a value of one. C
, C52, and C53 are the path maintenance data link (or HDLC) bits. C61, C62, and C63
51
71
. X1 and X2 are the Remote Defect Indication (RDI) bits (also referred
are the subframe alignment bits that define the
XY
, C42, and C43 are the Far-End Block Error (FEBE) bits used for
41
is the Application
11
, C72, and C73 are unused, and have a value of one.
9.6.5.5.2 Receive C-bit DS3 Overhead Extraction
Overhead extraction extracts all of the DS3 overhead bits from the C-bit DS3 frame. All of the DS3 overhead bits
X
, X2, P1, P2, MX, FXY, and CXY are output on the receive overhead interface (ROH, ROHSOF, and ROHCLK). The
1
P
, P2, C31, C32, and C33 bits are output as an error indication (modulo 2 addition of the calculated parity and the
1
bit). The C
bit is sent over to the receive FEAC controller. The C51, C52, and C53 bits are sent to the receive HDLC
13
overhead controller.
9.6.6 M23 DS3 Framer/Formatter
9.6.6.1 Transmit M23 DS3 Frame Processor
The M23 DS3 frame format is shown in Figure 9-13
are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P
bits used for line error monitoring. M
alignment bits. C
is the Application Identification Channel (AIC). CX1, CX2, and CX3 are the stuff control bits for
11
, M2, and M3 are the multiframe alignment bits. FXY are the subframe
1
tributary #X. The X-bit, P-bit, M-bit, C-bit, and F-bit positions are overhead bits, and the remainder of the bit
positions in the T3 frame are payload bits regardless of how they are marked by TDEN.
. Table 9-28 defines the framing bits for M23 DS3. X1 and X2
and P2 are the parity
1
Table 9-28. M23 DS3 Frame Overhead Bit Definitions
BIT DEFINITION
X1, X2 Remote Defect Indication
(RDI)
P1, P2 Parity Bits
M1, M2, and M3 Multiframe Alignment Bits
FXY Subframe Alignment Bits
C11 Application Identification
Channel (AIC)
CX1, CX2, and CX3 Stuff Control Bits for Tributary
#X
9.6.6.2 Transmit M23 DS3 Frame Generation
M23 DS3 frame generation receives the incoming payload data stream, and overwrites all of the DS3 overhead bit
locations.
The multiframe alignment bits (M
respectively.
The subframe alignment bits (F
respectively.
, M2, and M3) are overwritten with the values zero, one, and zero (010)
1
, FX2, FX3, and FX4) are overwritten with the values one, zero, zero, and one (1001)
X1
The X-bits (X
and X2) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
1
programmable (automatic, 1, or 0). If the RDI is generated automatically, the X-bits are set to zero when one or
87 of 233
DS3170 DS3/E3 Single-Chip Transceiver
more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are
absent. Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
and P2) are both overwritten with the calculated payload parity from the previous DS3 frame. The
1
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
If C-bit generation is enabled, the bit C
bits (C
) are overwritten with zeros. If C-bit generation is disabled, then all of the C-bit timeslots (CXY) will be
XY
is overwritten with an alternating one zero pattern, and all of the other C-
11
treated as payload data, and passed through. C-bit generation is programmable (on or off). Note: Overhead
insertion may still overwrite the C-bit time slots even if C-bit generation is disabled.
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
9.6.6.3 Transmit M23 DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors and P-bit parity errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe
alignment bit (F
error in all the subframe alignment bits in a subframe (F
alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
) error. An M-bit error is a single multiframe alignment bit (M1, M2, or M3) error. An SEF error is an
XY
, M2, or M3) error in each of two consecutive DS3 frames.
1
, FX2, FX3, and FX4). An OOMF error is a single multiframe
X1
and P2) in a single DS3 frame. P-bit parity
1
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
Each error type (framing or P-bit parity) has a separate enable. Continuous error insertion mode inserts errors at
every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The
framing multi-error insertion modes (SEF or OOMF) insert the indicated number of error(s) at the next opportunities
when requested; i.e., a single request will cause multiple errors to be inserts. The requests can be initiated by a
register bit(TSEI) or by the manual error insertion input (TMEI). The error insertion request source (register or
input) is programmable. The insertion of each particular error type is individually enabled. Once all error insertion
has been performed, the data stream is passed on to overhead insertion.
9.6.6.4 Transmit M23 DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
X
, P1, P2, MX, FXY, and CXY can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
2
TOHSOF). The P-bits (P
and P2) are received as an error mask (modulo 2 addition of the input bit and the
1
1
internally generated bit). The DS3 overhead insertion is fully controlled by the transmit overhead interface. If the
transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit overhead signal (TOH) is
inserted into the output data stream. Insertion of bits using the TOH signal overwrites internal overhead insertion.
9.6.6.5 Transmit M23 DS3 AIS/Idle Generation
M23 DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the
data stream payload is forced to a 1100 pattern with two ones immediately following each DS3 overhead bit. M
M
, and M3 bits are overwritten with the values zero, one, and zero (010) respectively. FX1, FX2, FX3, and FX4 bits are
2
overwritten with the values one, zero, zero, and one (1001) respectively. X
P
are overwritten with the calculated payload parity from the previous output DS3 frame. And, C31, C32, and C33
2
and X2 are overwritten with 11. P1 and
1
1
are overwritten with 000.
If transmit AIS is enabled, the data stream payload is forced to a 1010 pattern with a one immediately following
each DS3 overhead bit. M
F
, FX2, FX3, and FX4 bits are overwritten with the values one, zero, zero, and one (1001) respectively. X1 and X2
X1
are overwritten with 11. P
And, C
88 of 233
, CX2, and CX3 are overwritten with 000. AIS will overwrite a transmit Idle signal.
X1
, M2, and M3 bits are overwritten with the values zero, one, and zero (010) respectively.
1
and P2 are overwritten with the calculated payload parity from the previous DS3 frame.
1
,
,
9.6.6.5.1 Receive M23 DS3 Frame Format
DS3170 DS3/E3 Single-Chip Transceiver
The DS3 frame format is shown in Figure 9-13
referred to as the far-end SEF/AIS bits). P
are the multiframe alignment bits that define the multiframe boundary. F
define the subframe boundary. Note: Both the M-bits and F-bits define the DS3 frame boundary. C
Application Identification Channel (AIC). C
. The X1 and X2 are the Remote Defect Indication (RDI) bits (also
and P2 are the parity bits used for line error monitoring. M1, M2, and M3
1
, CX2, and CX3 are the stuff control bits for tributary #X.
X1
are the subframe alignment bits that
XY
is the
11
9.6.6.5.2 Receive M23 DS3 Overhead Extraction
Overhead extraction extracts all of the DS3 overhead bits from the M23 DS3 frame. All of the DS3 overhead bits
X
, X2, P1, P2, MX, FXY, and CXY are output on the receive overhead interface (ROH, ROHSOF, and ROHCLK). The
1
P
and P2 bits are output as an error indication (modulo 2 addition of the calculated parity and the bit).
1
9.6.6.5.3 Receive DS3 Downstream AIS Generation
Downstream DS3 AIS (all ‘1’s) can be automatically generated on an OOF, LOS, or AIS condition or manually
inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS or AIS condition is
declared, or no earlier than 2.25 ms and no later than 2.75 ms after an OOF condition is declared. Automatic
downstream AIS is programmable (on or off). If manual downstream AIS insertion is enabled, downstream AIS is
inserted. Manual downstream AIS insertion is programmable (on or off). Downstream AIS is removed when all
OOF, LOS, and AIS conditions are terminated and manual downstream AIS insertion is disabled.
9.6.7 G.751 E3 Framer/Formatter
9.6.7.1 Transmit G.751 E3 Frame Processor
The G.751 E3 frame format is shown in Figure 9-16
bit used to indicate the presence of an alarm to the remote terminal equipment. N is the National use bit reserved
for national use.
. FAS is the Frame Alignment Signal. A is the Alarm indication
Figure 9-16. G.751 E3 Frame Format
FAS
9.6.7.2 Transmit G.751 E3 Frame Generation
G.751 E3 frame generation receives the incoming payload data stream, and overwrites all of the E3 overhead bit
locations.
The first ten bits of the frame are overwritten with the frame alignment signal (FAS) which has a value of
1111010000b.
The eleventh bit of the frame is overwritten with the alarm indication (A) bit. The A bit can be generated
automatically, sourced from the transmit FEAC controller, set to one, or set to zero. The A bit source is
programmable (automatic, FEAC, 1, or 0). If the A bit is generated automatically, it is set to one when one or more
of the indicated alarm conditions is present, and set to zero when all of the indicated alarm conditions are absent.
Automatically setting RDI on LOS, LOF, or AIS is individually programmable (on or off).
A N
4 Rows
1524 Bit Payload
384 bits
The twelfth bit of the frame is overwritten with the national use (N) bit. The N bit can be sourced from the transmit
FEAC controller, sourced from the transmit HDLC overhead controller, set to one, or set to zero. The N bit source
is programmable (FEAC, HDLC, 1, or 0). Note: The FEAC controller will source one bit per frame regardless of
whether the A bit only, the N bit only, or both are programmed to be sourced from the FEAC controller.
89 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Once all of the E3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming E3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off).
9.6.7.3 Transmit G.751 E3 Error Insertion
Error insertion inserts framing errors into the frame alignment signal (FAS). The type of error(s) inserted into the
FAS is programmable (errored FAS bit or errored FAS). An errored FAS bit is a single bit error in the FAS. An
errored FAS is an error in all ten bits of the FAS (a value of 0000101111b is inserted in the FAS). Framing error(s)
can be inserted one error at a time, or in four consecutive frames. The framing error insertion number (single or
four) is programmable.
Single error insertion mode inserts an error at the next opportunity when requested. The multi-error insertion mode
inserts the indicated number of errors at the next opportunities when requested. I.e., a single request will cause
multiple errors to be inserted. The requests can be initiated by a register bit(TSEI) or by the manual error insertion
input (TMEI). The error insertion initiation type (register or input) is programmable. The insertion of each particular
error type is individually enabled.
Once all error insertion has been performed, the data stream is passed on to overhead insertion.
9.6.7.4 Transmit G.751 E3 Overhead Insertion
Overhead insertion can insert any (or all) of the E3 overhead bits into the E3 frame. The FAS, A bit, and N bit can
be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and TOHSOF). The E3 overhead
insertion is fully controlled by the transmit overhead interface. If the transmit overhead data enable signal (TOHEN)
is driven high, then the bit on the transmit overhead signal (TOH) is inserted into the output data stream. Insertion
of bits using the TOH signal overwrites internal overhead insertion.
9.6.7.5 Transmit G.751 E3 AIS Generation
G.751 E3 AIS generation overwrites the data stream with AIS. If transmit AIS is enabled, the data stream (payload
and E3 overhead) is forced to all ones.
9.6.7.6 Receive G.751 E3 Frame Processor
The G.751 E3 frame format is shown in Figure 9-16
. FAS is the Frame Alignment Signal. A is the Alarm indication
bit used to indicate the presence of an alarm to the remote terminal equipment. N is the National use bit reserved
for national use.
9.6.7.6.1 Receive G.751 E3 Framing
G.751 E3 framing determines the G.751 E3 frame boundary. The frame boundary is found by identifying the frame
alignment signal (FAS), which has a value of 1111010000b. The framer is an off-line framer that updates the data
path frame counters when an out of frame (OOF) condition has been detected. The use of an off-line framer
reduces the average time required to reframe, and reduces data loss caused by burst error. The G.751 E3 framer
checks each bit position for the FAS. The frame boundary is set once the FAS is identified. Since, the FAS check is
performed one bit at a time, up to 1536 checks may be needed to find the frame boundary. The data path frame
counters are updated if an error free FAS is received for two additional frames, and an OOF condition is present, or
if a manual frame resynchronization has been initiated.
9.6.7.6.2 Receive G.751 E3 Performance Monitoring
Performance monitoring checks the E3 frame for alarm conditions. The alarm conditions detected are OOF, LOF,
COFA, LOS, AIS, RUA1, and RAI. An Out Of Frame (OOF) condition is declared when four consecutive frame
alignment signals (FAS) contain one or more errors or at the next FAS check when a manual reframe is requested.
An OOF condition is terminated when three consecutive FAS’s are error free or the G.751 E3 framer updates the
data path frame counters.
A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active for a total of T
ms. The LOF integration counter is active (increments count) when an OOF condition is present, it is inactive (holds
count) when an OOF condition is absent, and it is reset when an OOF condition is absent for T continuous ms. T is
programmable (0, 1, 2, or 3). An LOF condition is terminated when an OOF condition is absent for T continuous
ms.
90 of 233
DS3170 DS3/E3 Single-Chip Transceiver
A Change Of Frame Alignment (COFA) is declared when the G.751 E3 framer updates the data path frame
counters with a frame alignment that is different from the current data path frame alignment.
A Loss Of Signal (LOS) condition is declared when the HDB3 encoder is active, and it declares an LOS condition.
An LOS condition is terminated when the HDB3 encoder is inactive, or it terminates an LOS condition.
An Alarm Indication Signal (AIS) condition is declared when 4 or less zeros are detected in each of two consecutive
frame periods. An AIS condition is terminated when 5 or more zeros are detected in each of two consecutive frame
periods.
A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less
zeros are detected and an OOF condition is continuously present. A RUA1 condition is terminated if in each of 4
consecutive 2047 bit windows, six or more zeros are detected or an OOF condition is continuously absent.
A Remote Alarm Indication (RAI) condition is declared when four consecutive frames are received with the A bit
(first bit after the FAS) set to one. An RAI condition is terminated when four consecutive frames are received with
the A bit set to zero.
Only framing errors are accumulated. Framing errors are determined by comparing the FAS to its expected value.
The type of framing errors accumulated is programmable (OOFs, bit, or word). An OOF error increments the count
whenever an OOF condition is first detected. A bit error increments the count once for each bit in the FAS that does
not match its expected value (up to 10 per frame. A word error increments the count once for each FAS that does
not match its expected value (up to 1 per frame).
The receive alarm indication (RAI) signal is high when one or more of the indicated alarm conditions is present, and
low when all of the indicated alarm conditions are absent. Setting the receive alarm indication on LOS, OOF, LOF,
or AIS is individually programmable (on or off).
9.6.7.6.3 Receive G.751 E3 Overhead Extraction
Overhead extraction extracts all of the E3 overhead bits from the G.751 E3 frame. The FAS, A bit, and N bit are
output on the receive overhead interface (ROH, ROHSOF, and ROHCLK). In addition, the A bit is integrated and
stored in a register along with a change indication, and can be output over the receive FEAC controller. The N bit is
integrated and stored in a register along with a change indication, is sent to the receive HDLC overhead controller,
and can also be sent to the receive FEAC controller. The bit sent to the receive FEAC controller is programmable
(A or N).
9.6.7.6.4 Receive G.751 Downstream AIS Generation
Downstream G.751 E3 AIS can be automatically generated on an OOF, LOS, or AIS condition or manually
inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS, OOF, or AIS
condition is declared. Automatic downstream AIS is programmable (on or off). If manual downstream AIS insertion
is enabled, downstream AIS is inserted. Manual downstream AIS insertion is programmable (on or off).
Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS
insertion is disabled. RPDT will be forced to all ones during downstream AIS.
9.6.8 G.832 E3 Framer/Formatter
9.6.8.1 Transmit G.832 E3 Frame Processor
The G.832 E3 frame format is shown in Figure 9-17
.
91 of 233
Figure 9-17. G.832 E3 Frame Format
FA1
FA2
EM
TR
MA
DS3170 DS3/E3 Single-Chip Transceiver
NR
GC
Figure 9-18. MA Byte Format
MSB
1
RDI REI SL SL SL MI MI TM
RDI - Remote Defect Indicator
REI - Remote Error Indicator
SL - Signal Label
MI - Multi-frame Indicator
TM - Timing Marker
Table 9-29
shows the function of each overhead bit in the DS3 Frame.
530 Byte Payload
59 Columns
LSB
8
9 Rows
Table 9-29. G.832 E3 Frame Overhead Bit Definitions
BYTE DEFINITION
FA1, FA2 Frame Alignment bytes
EM Error Monitoring byte
TR Trail Trace byte
MA Maintenance and Adaption
byte
NR Network Operator byte
GC General Purpose
Communication Channel byte
92 of 233
DS3170 DS3/E3 Single-Chip Transceiver
FA1 and FA2 are the Frame Alignment bytes. EM is the Error Monitoring byte used for path error monitoring. TR is
the Trail Trace byte used for end-to-end connectivity verification. MA is the Maintenance and Adaptation byte used
for far-end path status and performance monitoring.
NR is the Network Operator byte allocated for network operator maintenance purposes. GC is the General Purpose
Communications Channel byte allocated for user communications purposes.
9.6.8.2 Transmit G.832 E3 Frame Generation
G.832 E3 frame generation receives the incoming payload data stream, and overwrites all of the E3 overhead byte
locations.
The first two bytes of the first row in the frame are overwritten with the frame alignment bytes FA1 and FA2, which
have a value of F6h and 28h respectively.
The first byte in the second row of the frame is overwritten with the EM byte which is a BIP-8 calculated over all of
the bytes of the previous frame after all frame processing (frame generation, error insertion, overhead insertion,
and AIS generation) has been performed. The first byte in the third row of the frame is overwritten with the TR byte
which is input from the transmit trail trace controller.
The first byte in the fourth row of the frame is overwritten with the MA byte (see Figure 9-18
), which consists of the
RDI bit, REI bit, payload type, multiframe indicator, and timing source indicator.
The RDI bit can be generated automatically, set to one, or set to zero. The RDI source is programmable
(automatic, 1, or 0). If the RDI is generated automatically, it is set to one when one or more of the indicated alarm
conditions is present, and set to zero when all of the indicated alarm conditions are absent. Automatically setting
RDI on LOS, LOF, or AIS is individually programmable (on or off).
The REI bit can be generated automatically or inserted from a register bit. The REI source is programmable
(automatic or register). If REI is generated automatically, it is one when at least one parity error has been detected
during the previous frame.
The payload type is sourced from a register. The three register bits are inserted in the third, fourth, and fifth bits of
the MA byte in each frame.
The multiframe indicator and timing marker bits can be directly inserted from a 3-bit register or generated from a 4bit register. The multiframe indicator and timing marker insertion type is programmable (direct or generated). When
the multiframe indicator and timing marker bits are directly inserted, the three register bits are inserted in the last
three bits of the MA byte in each frame. When the multiframe indicator and timing marker bits are generated, the
four timing source indicator bits are transferred in a four-frame multiframe, MSB first. The multiframe indicator bits
(sixth and seventh bits of the MA byte) identify the phase of the multiframe (00, 01, 10, or 11), and the timing
marker bit (eighth bit of the MA byte) contains the corresponding timing source indicator bit (TMABR register bits
TTI3, TTI2, TTI1, or TTI0 respectively). Note: The initial phase of the multiframe is arbitrarily chosen.
The first byte in the fifth row of the frame is overwritten with the NR byte which can be sourced from a register, from
the transmit FEAC controller, or from the transmit HDLC controller. The NR byte source is programmable (register,
FEAC, or HDLC). Note: The HDLC controller will source eight bits per frame period regardless of whether the NR
byte only, GC byte only, or both are programmed to be sourced from the HDLC controller.
The first byte in the sixth row of the frame is overwritten with the GC byte which can be sourced from a register or
from the transmit HDLC controller. The GC byte source is programmable (register or HDLC).
Once all of the E3 overhead bytes have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming E3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off).
9.6.8.3 Transmit G.832 E3 Error Insertion
Error insertion inserts various types of errors into the different E3 overhead bytes. The types of errors that can be
inserted are framing errors, BIP-8 parity errors, and Remote Error Indication (REI) errors.
The type of framing error(s) inserted is programmable (errored frame alignment bit or errored frame alignment
word). A frame alignment bit error is a single bit error in the frame alignment word (FA1 or FA2). A frame alignment
word error is an error in all sixteen bits of the frame alignment word (the values 09h and D7h are inserted in the
FA1 and FA2 bytes respectively). Framing error(s) can be inserted one error at a time, or four consecutive frames.
The framing error insertion mode (single or four) is programmable.
93 of 233
DS3170 DS3/E3 Single-Chip Transceiver
The type of BIP-8 error(s) inserted is programmable (errored BIP-8 bit, or errored BIP-8 byte). An errored BIP-8 bit
is inverting a single bit error in the EM byte. An errored BIP-8 byte is inverting all eight bits in the EM byte. BIP-8
error(s) can be inserted one error at a time, or continuously. The BIP-8 error insertion mode (single or continuous)
is programmable.
An REI error is generated by forcing the second bit of the MA byte to a one. REI error(s) can be inserted one error
at a time, or continuously. The REI error insertion mode (single or continuous) is programmable.
Each error type (framing, BIP-8, or REI) has a separate enable. Continuous error insertion mode inserts errors at
every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The framing
multi-error insertion mode inserts the indicated number of errors at the next opportunities when requested. i.e., a
single request will cause multiple errors to be inserted. The requests can be initiated by a register bit(TSEI) or by
the manual error insertion input (TMEI). The error insertion request source (register or input) is programmable. The
insertion of each particular error type is individually enabled. Once all error insertion has been performed, the data
stream is passed on to overhead insertion.
9.6.8.4 Transmit G.832 E3 Overhead Insertion
Overhead insertion can insert any (or all) of the E3 overhead bytes into the E3 frame. The E3 overhead bytes FA1,
FA2, EM, TR, MA, NR, and GC can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
TOHSOF). The EM byte is sourced as an error mask (modulo 2 addition of the input EM byte and the generated
EM byte). The E3 overhead insertion is fully controlled by the transmit overhead interface. If the transmit overhead
data enable signal (TOHEN) is driven high, then the bit on the transmit overhead signal (TOH) is inserted into the
output data stream. Insertion of bits using the TOH signal overwrites internal overhead insertion.
9.6.8.5 Transmit G.832 E3 AIS Generation
G.832 E3 AIS generation overwrites the data stream with AIS. If transmit AIS is enabled, the data stream (payload
and E3 overhead) is forced to all ones.
9.6.8.6 Receive G.832 E3 Frame Processor
The G.832 E3 frame format is shown in Figure 9-17
. FA1 and FA2 are the Frame Alignment bytes. EM is the Error
Monitoring byte used for path error monitoring. TR is the Trail Trace byte used for end-to-end connectivity
verification. MA is the Maintenance and Adaptation byte used for far-end path status and performance monitoring
(see Figure 9-18
). NR is the Network Operator byte allocated for network operator maintenance purposes. GC is
the General Purpose Communications Channel byte allocated for user communications purposes.
9.6.8.7 Receive G.832 E3 Framing
G.832 E3 framing determines the G.832 E3 frame boundary. The frame boundary is found by identifying the frame
alignment bytes FA1 and FA2, which have a value of F6h and 28h respectively. The framer is an off-line framer
that updates the data path frame counters when an out of frame (OOF) condition has been detected. The use of an
off-line framer reduces the average time required to reframe, and reduces data loss caused by burst error. The
G.832 E3 framer checks each bit position for the frame alignment word (FA1 and FA2). The frame boundary is set
once the frame alignment word is identified. Since, the frame alignment word check is performed one bit at a time,
up to 4296 checks may be needed to find the frame boundary. The data path frame counters are updated if an
error free frame alignment word is received for two additional frames, and an OOF condition is present.
9.6.8.8 Receive G.832 E3 Performance Monitoring
Performance monitoring checks the E3 frame for alarm conditions and errors. The alarm conditions detected are
OOF, LOF, COFA, LOS, AIS, RUA1, and RDI. The errors accumulated are framing, parity, and Remote Error
Indication (REI) errors. An Out Of Frame (OOF) condition is declared when four consecutive frame alignment
words (FA1 and FA2) contain one or more errors, when 986 or more frames out of 1,000 frames has a BIP-8 block
error, or at the next framing word check when a manual reframe is requested. An OOF condition is terminated
when three consecutive frame alignment words (FA1 and FA2) are error free or the G.832 E3 framer updates the
data path frame counters.
A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active for a total of T
ms. The LOF integration counter is active (increments count) when an OOF condition is present, it is inactive (holds
count) when an OOF condition is absent, and it is reset when an OOF condition is absent for T continuous ms. T is
programmable (0, 1, 2, or 3). An LOF condition is terminated when an OOF condition is absent for T continuous
ms.
94 of 233
DS3170 DS3/E3 Single-Chip Transceiver
A Change Of Frame Alignment (COFA) is declared when the G.832 E3 framer updates the data path frame
counters with a frame alignment that is different from the current data path frame alignment.
A Loss Of Signal (LOS) condition is declared when the HDB3 encoder is active, and it declares an LOS condition.
An LOS condition is terminated when the HDB3 encoder is inactive, or it terminates an LOS condition.
An Alarm Indication Signal (AIS) condition is declared when 7 or less zeros are detected in each of two consecutive
frame periods that do not contain a frame alignment word. An AIS condition is terminated when 8 or more zeros are
detected in each of two consecutive frame periods.
A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less
zeros are detected and an OOF condition is continuously present. A RUA1 condition is terminated if in each of 4
consecutive 2047 bit windows, six or more zeros are detected or an OOF condition is continuously absent.
A Remote Defect Indication (RDI) condition is declared when four consecutive frames are received with the RDI bit
(first bit of MA byte) set to one. An RDI condition is terminated when four consecutive frames are received with the
RDI bit set to zero.
Three types of errors are accumulated, framing, parity, and Remote Error Indication (REI) errors. Framing errors
are determined by comparing FA1 and FA2 to their expected values. The type of framing errors accumulated is
programmable (OOFs, bit, byte, or word). An OOF error increments the count whenever an OOF condition is first
detected. A bit error increments the count once for each bit in FA1 and each bit in FA2 that does not match its
expected value (up to 16 per frame). A byte error increments the count once for each FA byte (FA1 or FA2) that
does not match its expected value (up to 2 per frame). A word error increments the count once for each FA word
(both FA1 and FA2) that does not match its expected value (up to 1 per frame).
Parity errors are determined by calculating the BIP-8 (8-Bit Interleaved Parity) of the current E3 frame (overhead
and payload bytes), and comparing the calculated BIP-8 to the EM byte in the next frame. The type of parity errors
accumulated is programmable (bit or block). A bit error increments the count once for each bit in the EM byte that
does not match the corresponding bit in the calculated BIP-8 (up to 8 per frame). A block error increments the
count if any bit in the EM byte does not match the corresponding bit in the calculated BIP-8 (up to 1 per frame).
REI errors are determined by the REI bit (second bit of MA byte). A one indicates an error and a zero indicates no
errors.
The receive alarm indication (RAI) signal is high when one or more of the indicated alarm conditions is present, and
low when all of the indicated alarm conditions are absent. Setting the receive alarm indication on LOS, OOF, LOF,
or AIS is individually programmable (on or off).
The receive error indication (REI) signal will transition from low to high once for each frame in which a parity error is
detected.
9.6.8.9 Receive G.832 E3 Overhead Extraction
Overhead extraction extracts all of the E3 overhead bytes from the G.832 E3 frame. All of the E3 overhead bytes
FA1, FA2, EM, TR, MA, NR, and GC are output on the receive overhead interface (ROH, ROHSOF, and
ROHCLK).
The EM byte is output as an error indication (modulo 2 addition of the calculated BIP-8 and the EM byte.
The TR byte is sent to the receive trail trace controller.
The payload type (third, fourth, and fifth bits of the MA byte) is integrated and stored in a register with change and
unstable indications. The integrated received payload type is also compared against an expected payload type. If
the received and expected payload types do not match (see Table 9-30
), a mismatch indication is set.
95 of 233
DS3170 DS3/E3 Single-Chip Transceiver
Table 9-30. Payload Label Match Status
EXPECTED RECEIVED STATUS
000 000 Match
000 001 Mismatch
000 XXX Mismatch
001 000 Mismatch
001 001 Match
001 XXX Match
XXX 000 Mismatch
XXX 001 Match
XXX XXX Match
XXX YYY Mismatch
XXX and YYY equal any value other than 000 or 001; XXX ¹ YYY.
The multiframe indicator and timing marker bits (sixth, seventh, and eighth bits of the MA byte) can be integrated
and stored in three register bits or extracted, integrated, and stored in four register bits. The bits (three or four) are
stored with a change indication. The multiframe indicator and timing marker storage type is programmable
(integrated or extracted). When the multiframe indicator and timing marker bits are integrated, the last three bits of
the MA byte are integrated and stored in three register bits. When the multiframe indicator and timing marker bits
are extracted, four timing source indicator bits are transferred in a four-frame multiframe, MSB first. The multiframe
indicator bits (sixth and seventh bits of the MA byte) identify the phase of the multiframe (00, 01, 10, or 11). The
timing marker bit (eighth bit of the MA byte) contains the timing source indicator bit indicated by the multiframe
indicator bits (first, second, third, or fourth bit respectively). The four timing source indicator bits are extracted from
the multiframe, integrated, and stored in four register bits with unstable and change indications.
The NR byte is integrated and stored in a register along with a change indication, it is sent to the receive FEAC
controller, and it can be sent to the receive HDLC controller. The byte sent to the receive HDLC controller is
programmable (NR or GC).
The GC byte is integrated and stored in a register along with a change indication, and can be sent to the receive
HDLC controller. The byte sent to the receive HDLC controller is programmable (NR or GC).
9.6.8.10 Receive G.832 Downstream AIS Generation
Downstream G.832 E3 AIS can be automatically generated on an OOF, LOS, or AIS condition or manually
inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS, OOF, or AIS
condition is declared. Automatic downstream AIS is programmable (on or off). If manual downstream AIS insertion
is enabled, downstream AIS is inserted. Manual downstream AIS insertion is programmable (on or off).
Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS
insertion is disabled. RPDT will be forced to all ones during downstream AIS.
9.7 HDLC Overhead Controller
9.7.1 General Description
The DS3170 device contains a built-in HDLC controller with 256 byte FIFOs for insertion/extraction of DS3 PMDL,
G.751 Sn bit and G.832 NR/GC bytes.
The HDLC Overhead Controller demaps HDLC overhead packets from the DS3/E3 data stream in the receive
direction and maps HDLC packets into the DS3/E3 data stream in the transmit direction.
The receive direction performs packet processing and stores the packet data in the FIFO. It removes packet data
from the FIFO and outputs the packet data to the microprocessor via the register interface.
The transmit direction inputs the packet data from the microprocessor via the register interface and stores the
packet data in the FIFO. It removes the packet data from the FIFO and performs packet processing.
96 of 233
DS3170 DS3/E3 Single-Chip Transceiver
The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB
last. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8 (LSB).
However, when a byte is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is
stored in the highest numbered bit (7). This is to differentiate between a byte in a register and the corresponding
byte in a signal.
See Figure 9-19
for the location of HDLC controllers within the DS3170 device.
Figure 9-19. HDLC Controller Block Diagram
TAIS
TUA1
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
DLB
9.7.2 Features
· Programmable inter-frame fill – The inter-frame fill between packets can be all 1’s or flags.
· Programmable FCS generation/monitoring – An FCS-16 can be generated and appended to the end of the
packet, and the FCS can be checked and removed from the end of the packet.
· Programmable bit reordering – The packet data can be can be output MSB first or LSB first from the FIFO.
· Programmable data inversion – The packet data can be inverted immediately after packet processing on the
transmit, and immediately before packet processing on the receive.
· Fully independent transmit and receive paths
· Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
DS3 / E3
Transmit
Formatter
FEAC
Trace
Buffer
DS3 / E3
Receive
Framer
IEEE P1149.1
JTAG Test
Access Port
Trail
HDLC
UA1
GEN
PLB
TX BERT
RX BERT
Microprocessor
Interface
9.7.3 Transmit FIFO
The Transmit FIFO block contains memory for 256 bytes of data with data status information and controller circuitry
for reading and writing the memory. The Transmit FIFO controller functions include filling the memory, tracking the
memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow
conditions. The Transmit FIFO receives data and status from the microprocessor interface, and stores the data
along with the data status information in memory. The Transmit Packet Processor reads the data and data status
information from the Transmit FIFO. The Transmit FIFO also outputs FIFO fill status (empty/data storage
available/full) via the microprocessor interface. All operations are byte based. The Transmit FIFO is considered
empty when its memory does not contain any data. The Transmit FIFO is considered to have data storage
available when its memory has a programmable number of bytes or more available for storage. The Transmit FIFO
is considered full when it does not have any space available for storage. The Transmit FIFO accepts data from the
register interface until full. If the Transmit FIFO is written to while the FIFO is full, the write is ignored, and a FIFO
overflow condition is declared. The Transmit Packet Processor reads the Transmit FIFO. If the Transmit Packet
Processor attempts to read the Transmit FIFO while it is empty, a FIFO underflow condition is declared.
97 of 233
DS3170 DS3/E3 Single-Chip Transceiver
9.7.4 Transmit HDLC Overhead Processor
The Transmit HDLC Overhead Processor accepts data from the Transmit FIFO, performs bit reordering, FCS
processing, stuffing, packet abort sequence insertion, and inter-frame padding.
A byte is read from the Transmit FIFO with a packet end status. When a byte is marked with a packet end
indication, the output data stream will be padded with FFh and marked with a FIFO empty indication if the Transmit
FIFO contains less than two bytes or transmit packet start is disabled. Transmit packet start is programmable (on
or off). When the Transmit Packet Processor reads the Transmit FIFO while it is empty, the output data stream is
marked with an abort indication. Once the Transmit FIFO is empty, the output data stream will be padded with
interframe fill until the Transmit FIFO contains two or more bytes of data and transmit packet start is enabled.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is input from the Transmit FIFO with the MSB in TFD[0]
and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. If bit reordering is enabled, the outgoing 8-bit data
stream DT[1:8] is input from the Transmit FIFO with the MSB in TFD[7] and the LSB in TFD[0] of the transmit FIFO
data TFD[7:0]. DT[1] is the first bit transmitted on the outgoing data stream.
FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 calculation over the
entire packet. The polynomial used for the CRC-16 is x
16
+ x12 + x5 + 1. The CRC-16 is inverted after calculation,
and appended to the packet. For diagnostic purposes, an FCS error can be inserted. This is accomplished by
appending the calculated CRC-16 without inverting it. FCS error insertion is programmable (on or off). When FCS
processing is disabled, the packet is output without appending an FCS. FCS processing is programmable (on or
off).
Stuffing inserts control data into the packet to prevent packet data from mimicking flags. Stuffing is halted during
FIFO empty periods. The 8-bit parallel data stream is multiplexed into a serial data stream, and bit stuffing is
performed. Bit stuffing consists of inserting a '0' directly following any five contiguous '1's. Stuffing is performed
from a packet start until a packet end.
Inter-frame padding inserts inter-frame fill between the packet start and end flags when the FIFO is empty. The
inter-frame fill can be flags or '1's. If the inter-frame fill is flags, flags (minimum two) are inserted until a packet start
is received. If the inter-frame fill is all '1's, an end flag is inserted, ‘1’s are inserted until a packet start is received,
and a start flag is inserted after the ‘1’s. The number of '1's between the end flag and start flag may not be an
integer number of bytes, however, the inter-frame fill will be at least 15 consecutive '1's. If the FIFO is not empty
between a packet end and a packet start, then two flags are inserted between the packet end and packet start. The
inter-frame padding type is programmable (flags or ‘1’s).
Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a
packet abort sequence is inserted and inter-frame padding is done until a packet start is detected. The abort
sequence is FFh.
Once all packet processing has been completed, the datastream is inserted into the DS3/E3 datastream at the
proper locations. If transmit data inversion is enabled, the outgoing data is inverted after packet processing is
performed. Transmit data inversion is programmable (on or off).
9.7.5 Receive HDLC Overhead Processor
The Receive HDLC Overhead Packet Processor accepts data from the DS3/E3 Framer and performs packet
delineation, inter-frame fill filtering, packet abort detection, destuffing, FCS processing, and bit reordering. If receive
data inversion is enabled, the incoming data is inverted before packet processing is performed. Receive data
inversion is programmable (on or off).
Packet delineation determines the packet boundary by identifying a packet start flag. Each time slot is checked for
a flag sequence (7Eh). Once a flag is found, if it is identified as a start or end flag, and the packet boundary is set.
There may be a single flag (both end and start) between packets, there may be an end flag and a start flag with a
shared zero (011111101111110) between packets, there may be an end flag and a start flag (two flags) between
packets, or there may be an end flag, inter-frame fill, and a start flag between packets. The flag check is performed
one bit at a time.
Inter-frame fill filtering removes the inter-frame fill between a start flag and an end flag. All inter-frame fill is
discarded. The inter-frame fill can be flags (01111110) or all '1's. When inter-frame fill is all ‘1’s, the number of '1's
between the end flag and the start flag may not be an integer number of bytes. When inter-frame fill is flags, the
98 of 233
DS3170 DS3/E3 Single-Chip Transceiver
number of bits between the end flag and the start flag will be an integer number of bytes (flags). Any time there is
less than 16 bits between two flags, the data will be discarded.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if
an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded
until a packet start flag is detected. The abort sequence is seven consecutive ones.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if
an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded
until a packet start flag is detected. The abort sequence is seven consecutive ones.
Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. After a start
flag is detected, destuffing is performed until an end flag is detected. Destuffing consists of discarding any '0' that
directly follows five contiguous '1's. After destuffing is completed, the serial bit stream is demultiplexed into an 8-bit
parallel data stream and passed on with packet start, packet end, and packet abort indications. If there is less than
eight bits in the last byte, an invalid packet status is set, and the packet is tagged with an abort indication. If a
packet ends with five contiguous '1's, the packet will be processed as a normal packet regardless of whether or not
the five contiguous '1's are followed by a '0'.
FCS processing checks the FCS, discards the FCS bytes, and marks FCS erred packets. The FCS is checked for
errors, and the last two bytes are removed from the end of the packet. If an FCS error is detected, the packet is
marked with an FCS error indication. The HDLC CONTROLLER performs FCS-16 checking. FCS processing is
programmable (on or off). If FCS processing is disabled, FCS checking is not performed, and all of the packet data
is passed on.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[0]
and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. If bit reordering is enabled, the incoming 8-bit data
stream DT[1:8] is output to the Receive FIFO with the MSB in RFD[7] and the LSB in RFD[0] of the receive FIFO
data RFD[7:0]. DT[1] is the first bit received from the incoming data stream.
Once all of the packet processing has been completed, The 8-bit parallel data stream is passed on to the Receive
FIFO with packet start, packet end, and packet error indications.
9.7.6 Receive FIFO
The Receive FIFO block contains memory for 256 bytes of data with data status information and controller circuitry
for reading and writing the memory. The Receive FIFO Controller controls filling the memory, tracking the memory
fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow
conditions. The Receive FIFO accepts data and data status from the Receive Packet Processor and stores the
data along with data status information in memory. The data is read from the receive FIFO via the microprocessor
interface. The Receive FIFO also outputs FIFO fill status (empty/data available/full) via the microprocessor
interface. All operations are byte based. The Receive FIFO is considered empty when it does not contain any data.
The Receive FIFO is considered to have data available when there is a programmable number of bytes or more
stored in the memory. The Receive FIFO is considered full when it does not have any space available for storage.
The Receive FIFO accepts data from the Receive Packet Processor until full. If a packet start is received while full,
the data is discarded and a FIFO overflow condition is declared. If any other packet data is received while full, the
current packet being transferred is marked with an abort indication, and a FIFO overflow condition is declared.
Once a FIFO overflow condition is declared, the Receive FIFO will discard incoming data until a packet start is
received while the Receive FIFO has sixteen or more bytes available for storage. If the Receive FIFO is read while
the FIFO is empty, the read is ignored, and an invalid data indication given.
9.8 Trail Trace Controller
9.8.1 General Description
The DS3170 has a dedicated Trail Trace Buffer for E3-G.832 link management
The Trail Trace Controller performs extraction and storage of the incoming G.832 trail access point identifier in a
16-byte receive register.
99 of 233
DS3170 DS3/E3 Single-Chip Transceiver
The Trail Trace Controller extracts/inserts E3-G.832 trail access point identifiers using a 16-byte register(one for
transmit, one for receive).
The Trail Trace Controller demaps a 16-byte trail trace identifier from the E3-G.832 datastream in the receive
direction and maps a trace identifier into the E3-G.832 datastream in the transmit direction.
The receive direction inputs the trace ID data stream, performs trace ID processing, and stores the trace identifier
data in the data storage using line timing. It removes trace identifier data from the data storage and outputs the
trace identifier data to the microprocessor via the microprocessor interface using register timing. The data is forced
to all ones during LOS, LOF and AIS detection to eliminate false messages
The transmit direction inputs the trace identifier data from the microprocessor via the microprocessor interface and
stores the trace identifier data in the data storage using register timing. It removes the trace identifier data from the
data storage, performs trace ID processing, and outputs the trace ID data stream. Refer to Figure 9-20
for the
location of the Trail Trace Controller with the DS3170 device.
Figure 9-20. Trail Trace Controller Block Diagram
TAIS
TUA1
DS3/E3
Transmit
LIU
ALB
DS3/E3
Receive
LIU
Clock Rate
Adapter
B3ZS/
HDB3
Encoder
LLB
B3ZS/
HDB3
Decoder
DLB
DS3 / E3
Transmit
Formatter
FEAC
Trace
Buffer
DS3 / E3
Receive
Framer
IEEE P1149.1
JTAG Test
Access Port
Trail
HDLC
UA1
GEN
TX BERT
PLB
RX BERT
Microprocessor
Interface
9.8.2 Features
· Programmable trail trace ID – The trail trace ID controller can be programmed to handle a 16-byte trail trace
identifier (trail trace mode).
· Programmable transmit trace ID – All sixteen bytes of the transmit trail trace identifier are programmable.
· Programmable receive expected trace ID – A 16-byte expected trail trace identifier can be programmed.
Both a mismatch and unstable indication are provided.
· Programmable trace ID multiframe alignment – The transmit side can be programmed to perform trail trace
multiframe alignment insertion. The receive side can be programmed to perform trail trace multiframe
synchronization.
· Programmable bit reordering – The trace identifier data can be output MSB first or LSB first from the data
storage.
· Programmable data inversion – The trace identifier data can be inverted immediately after trace ID
processing on the transmit side, and immediately before trail ID processing on the receive side.
· Fully independent transmit and receive sides
· Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
9.8.3 Functional Description
The bits in a byte are received most significant bit (MSB) first and least significant bit (LSB) last. When they are
output serially, they are output MSB first and LSB last. The bits in a byte in an incoming signal are numbered in the
100 of 233
Loading...