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DS3164
User Manual
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Rainbow Electronics DS3164 User Manual

Maxim/Dallas Semiconductor Confidential
Y
PRODUCT PREVIEW
DS3161,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3

FEATURES

• Universal PHYs map ATM cells and/or HDLC packets into DS3 or E3 data streams

• Single, dual, triple and quad-port devices

• UTOPIA 2 or 3 or POS-PHY 2 or 3 interface
with 8, 16, or 32 bit bus width up to 66 MHz

• Ports independently configurable for cell or packet traffic in POS-PHY bus modes

• Direct, PLCP and clear-channel cell mapping

• Direct and clear-channel packet mapping

• On-chip DS3 (M23 or C-bit) and E3 (G.751
or G.832) framers

• Ports independently configurable for DS3, E3 or arbitrary framing protocol up to 52 Mbps

• Programmable (externally controlled or internally hardware based engine) subrate DS3/E3 circuitry

• DS3/E3/PLCP alarm generation and detection

• Built-in HDLC controllers with 256 byte
FIFOs for DS3 PMDL, G.751 Sn bit or G.832 NR/GC bytes

• On-chip BERTs for PRBS and repetitive pattern generation, detection and analysis

• Full featured DS3/E3/PLCP alarms

• Large performance-monitoring counters for
accumulation intervals up to 1 second

• Flexible overhead insertion/extraction ports for DS3, E3 and PLCP framers

• Loopbacks include line, diagnostic, framer payload and system interface

• Ports can be disabled to reduce power

www.maxim-ic.com/telecom

• Integrates clock rate adapter to generate the required 44.736 MHz for DS3, 34.368 MHz for E3, and/or 52 MHz for arbitrary framing protocol up to 52 Mbps

• 8/16-bit generic microprocessor interface

• 3.3V supply with 5V tolerant I/O

• Small high-density Thermally Enhanced (TE)
Chip Scale BGA packaging

• IEEE 1149.1 JTAG test port

PRODUCT BRIEF
PRODUCT BRIEF
PRELIMINAR
Note: This Product Preview contains preliminary information and is subject to change without notice.
Rev 1.6 1 of 12 022604
.
Maxim/Dallas Semiconductor Confidential
r
PRODUCT PREVIEW
DS3161,2,3,4 Multi-Port ATM/Packet PHYs For DS3/E3

FUNCTIONAL DIAGRAM

Line
Interface
Serial
Clock/Data
Ports[1:n]
to LIUs or SONET/SDH mapper
DS3/E3
Overhead
Ports[1:n]
Frame
Interface
Ports[1:n]
PLCP Overhead Ports[1:n]
DS316x
Microprocessor
Interface
System
Interface
UTOPIA or POS-PHY bus
to ATM or Link layer

ORDERING INFORMATION

Commercial Temperature Range (0°C to 70°C) DS3161 Single 400-lead TE-CSBGA DS3162 Dual 400-lead TE-CSBGA DS3163 Triple 400-lead TE-CSBGA DS3164 Quad 400-lead TE-CSBGA
Industrial Temperature Range (-40°C to 85°C) DS3161N Single 400-lead TE-CSBGA DS3162N Dual 400-lead TE-CSBGA DS3163N Triple 400-lead TE-CSBGA DS3164N Quad 400-lead TE-CSBGA
www.maxim-ic.com/telecom
Note: This Product Preview contains preliminary information and is subject to change without notice.
Rev 1.6 2 of 12 022604
.
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
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DESCRIPTION

The DS316x Multi-port PHYs map ATM cells and/or packets into as many as four DS3/E3 data streams. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3 or G.832 E3 data streams. PLCP framers provide legacy ATM transmission-convergence support. With integrated hardware support for both cells and packets, the DS316x PHYs enable high-density universal line cards for unchannelized DS3/E3.
1 BLOCK DIAGRAM

Figure 1–1 Block Diagram

TPOSn / TNRZn DS3 / E3
TNEGn / TOHMn
TCLKn
RPOSn / RNRZn
RNEGn / RLCVn / ROHMn
RCLKn
2 APPLICATIONS
Clock
Rate
Adapter
CLKACLKB
REFCL
Encoder
Loopback
Framer Diagnostic
Line Facility Loopback
IEEE P1149.1
JTAG Test
Access Port
JTCL
JTRST*
TMEI
B3ZS/ HDB3
HDLC
B3ZS/ HDB3
Decoder
JTDI
JTMS
JTDO
TOHn
TOHGCLKn
TOHSOFn
Transmit
Formatter
FEAC
DS3 / E3
Receive
Framer
ROHn
RECU
ROHGCLKn
ROHSOFn
TDATn
Trail Trace Buffer
RDATn
TLCLKn
TSOFn / TIOHMn
TDENn / TGCLKn
RSOFn
RLCLKn
RDENn / RGCLKn
TPOHn
TPOHGCLKn
TPOHSOFn
8KREFI
Tx
PLCP/DSS/FRAC
Formatter
Loopback
Framer Payload
Rx
PLCP/DSS/FRAC
Framer
RPOHn
8KREFO
RPOHSOFn
RPOHGCLKn
BERT
Tx Cell
Processor
Tx Packet Processor
Rx Packet Processor
Rx Cell
Processor
Microprocessor
Interface
9:0
CS*
ALE
15:0
A
D
Tx
FIFO
PIOAn
System
Interface
n = port #
PIOBn
Loopback
System Interface
Rx
FIFO
INT*
MOT
RST*
RD*/DS*
WR*/ R/W*
TSCLK TADR[4:0
TDATA[31:0 TPRTY* TEN* TPX TDXA[4:1 TSOX TSP TEOP TSX TMOD[1:0 TERR
RSCLK RADR[4:0
RDATA[31:0 RPRTY* REN* RPX RDXA[4:1 RSOX REOP RSX RVAL RMOD[1:0 RERR

• Access Concentrators

• Multi-Service Access Platforms

• ATM and Frame Relay Equipment

• Routers and Switches

• SONET/SDH ADM

• Digital Cross Connect

• PDH Multiplexer/Demultiplexer

Rev 1.6 3 of 12 022604
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
R
n
R
R
n
R
Figure 2–1 Four-Port Unchannelized ATM over T3/E3 Card
Typical ATM Line Card
Utopia
POS PHY
2/3
-
-
x
DS3/E3
DS3/E3
Line
Line
DS3154 #1
DS315x #1
4-Chan
4-Chan
DS3/E
DS3/E3
LIU
LIU
Utopia
POS-
DS3164 #1
DS316x #1
4-Chan
4-Chan
DS3/E
DS3/E3
ATM
ATM
PH
PHY
POS-
PHY
2/3
AT
ATM
Switch
Switch
Card
Card
(S/W+
(S/W+
Igr/Egr Mgt)
Igr/Egr Mgt)
DS318
DS3164 #3
DS316x #3
4-Chan
4-Chan
DS3/E
DS3/E3
ATM
ATM
PH
PHY
X = 1, 2, 3, 4
x
DS3/E3
DS3/E3
Line
Line
DS3154 #3
DS315x #3
4-Chan
4-Chan
DS3/E
DS3/E3
LIU
LIU
Typical ATM Line Card

Figure 2-2 Four-Port Unchannelized HDLC over T3/E3 Line Card

OC -12
OC -
AT
ATM
SA
SA
Typical Packet Line Card
Utopia
POS-
POS­PHY
2/3
OC -12
OC -
AT
POS
SA
SA
x
DS3/E3
DS3/E3
Line
Line
DS3154 #1
DS315x #1
4-Chan
4-Chan
DS3/E
DS3/E3
LIU
LIU
Utopia
POS-
DS3164 #1
DS316x #1
4-Chan
4-Chan
DS3/E
DS3/E3
ATM
PKT
PH
PHY
POS­PHY
2/3
AT
IP/PKT
Switch
Switch
Card
Card
(S/W+
(S/W+
Igr/Egr Mgt)
Igr/Egr Mgt)
DS318
DS3164 #3
DS316x #3
4-Chan
4-Chan
DS3/E
DS3/E3
ATM
PH
PHY
X = 1, 2, 3, 4
x
DS3/E3
DS3/E3
Line
Line
DS3154 #3
DS315x #3
4-Chan
4-Chan
DS3/E
DS3/E3
LIU
LIU
Typical Packet Line Card
Rev 1.6 4 of 12 022604
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