Rainbow Electronics DS31256 User Manual

www.maxim-ic.com

GENERAL DESCRIPTION

The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The Envoy is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.

There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The Envoy also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps.

APPLICATIONS

Channelized and Clear-Channel

(Unchannelized) T1/E1 and T3/E3 Routers with Multilink PPP Support High-Density Frame-Relay Access xDSL Access Multiplexers (DSLAMs) Triple HSSI High-Density V.35 SONET/SDH EOC/ECC Termination

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS31256 0°C to +70°C

256 PBGA

DEMO KIT AVAILABLE

DS31256 Envoy

256-Channel, High-Throughput

HDLC Controlle

FEATURES

§ 256 Independent, Bidirectional HDLC channels

§ Up to 132Mbps Full-Duplex Throughput

§ Supports Up to 64 T1 or E1 Data Streams

§ 16 Physical Ports (16 Tx and 16 Rx) That

Can Be Independently Configured for Channelized or Unchannelized Operation

§ Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized)

§ Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines

§ Per-Channel DS0 Loopbacks in Both Directions

§ Over-Subscription at the Port Level

§ Transparent Mode Supported

§ On-Board Bit Error-Rate Tester (BERT)

with Automatic Error Insertion Capability

§ BERT function Can Be Assigned to Any HDLC Channel or Any Port

§ Large 16kB FIFO in Both Receive and Transmit Directions

§ Efficient Scatter/Gather DMA Maximizes Memory Efficiency

§ Receive Data Packets are Time-Stamped

§ Transmit Packet Priority Setting

§ V.54 Loopback Code Detector

§ Local Bus Allows for PCI Bridging or Local

Access

§ Intel or Motorola Bus Signals Supported

§ Backward Compatibility with DS3134

§ 33MHz 32-Bit PCI (V2.1) Interface

§ 3.3V Low-Power CMOS with 5V Tolerant

I/O

§ JTAG Support IEEE 1149.1

§ 256-Pin Plastic BGA (27mm x 27mm)

Features continued on page 6.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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TABLE OF CONTENTS

1. MAIN FEATURES........................................................................................................................ 6

2. DETAILED DESCRIPTION........................................................................................................ 7

3. SIGNAL DESCRIPTION ........................................................................................................... 13

3.1 OVERVIEW/SIGNAL LIST.............................................................................................................................. 13

3.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION ......................................................................................... 18

3.3 LOCAL BUS SIGNAL DESCRIPTION .............................................................................................................. 19

3.4 JTAG SIGNAL DESCRIPTION ....................................................................................................................... 21

3.5 PCI BUS SIGNAL DESCRIPTION ................................................................................................................... 22

3.6 PCI EXTENSION SIGNALS ............................................................................................................................ 25

3.7 SUPPLY AND TEST SIGNAL DESCRIPTION.................................................................................................... 25

4. MEMORY MAP .......................................................................................................................... 26

4.1 INTRODUCTION ............................................................................................................................................ 26

4.2 GENERAL CONFIGURATION REGISTERS (0XX) ............................................................................................ 26

4.3 RECEIVE PORT REGISTERS (1XX) ................................................................................................................ 27

4.4 TRANSMIT PORT REGISTERS (2XX).............................................................................................................. 27

4.5 CHANNELIZED PORT REGISTERS (3XX) ....................................................................................................... 28

4.6 HDLC REGISTERS (4XX) ............................................................................................................................. 29

4.7 BERT REGISTERS (5XX).............................................................................................................................. 29

4.8 RECEIVE DMA REGISTERS (7XX)................................................................................................................ 29

4.9 TRANSMIT DMA REGISTERS (8XX)............................................................................................................. 30

4.10 FIFO REGISTERS (9XX)....................................................................................................................... 30

4.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX).................................................. 31

4.12 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX) .................................................. 31

5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT ............................ 32

5.1 MASTER RESET AND ID REGISTER DESCRIPTION ....................................................................................... 32

5.2 MASTER CONFIGURATION REGISTER DESCRIPTION.................................................................................... 32

5.3 STATUS AND INTERRUPT ............................................................................................................................. 34

5.3.1 General Description of Operation...................................................................................................... 34

5.3.2 Status and Interrupt Register Description .......................................................................................... 37

5.4 TEST REGISTER DESCRIPTION ..................................................................................................................... 43

6. LAYER 1 ...................................................................................................................................... 44

6.1 GENERAL DESCRIPTION............................................................................................................................... 44

6.2 PORT REGISTER DESCRIPTIONS ................................................................................................................... 48

6.3 LAYER 1 CONFIGURATION REGISTER DESCRIPTION ................................................................................... 51

6.4 RECEIVE V.54 DETECTOR............................................................................................................................ 56

6.5 BERT........................................................................................................................................................... 60

6.6 BERT REGISTER DESCRIPTION ................................................................................................................... 61

7. HDLC............................................................................................................................................ 67

7.1 GENERAL DESCRIPTION............................................................................................................................... 67

7.2 HDLC REGISTER DESCRIPTION................................................................................................................... 69

8. FIFO.............................................................................................................................................. 74

8.1 GENERAL DESCRIPTION AND EXAMPLE ...................................................................................................... 74

8.1.1 Receive High Watermark.................................................................................................................... 76

8.1.2 Transmit Low Watermark ................................................................................................................... 76

8.2 FIFO REGISTER DESCRIPTION..................................................................................................................... 76

9. DMA.............................................................................................................................................. 83

9.1 INTRODUCTION ............................................................................................................................................ 83

9.2 RECEIVE SIDE .............................................................................................................................................. 85

9.2.1 Overview ............................................................................................................................................. 85

9.2.2 Packet Descriptors.............................................................................................................................. 90

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9.2.3 Free Queue ......................................................................................................................................... 92

9.2.4 Done Queue ........................................................................................................................................ 97

9.2.5 DMA Channel Configuration RAM .................................................................................................. 102

9.3 TRANSMIT SIDE.......................................................................................................................................... 105

9.3.1 Overview ........................................................................................................................................... 105

9.3.2 Packet Descriptors............................................................................................................................ 114

9.3.3 Pending Queue.................................................................................................................................. 116

9.3.4 Done Queue ...................................................................................................................................... 120

9.3.5 DMA Configuration RAM................................................................................................................. 125

10. PCI BUS...................................................................................................................................... 130

10.1 GENERAL DESCRIPTION OF OPERATION ........................................................................................... 130

10.1.1 PCI Read Cycle................................................................................................................................. 131

10.1.2 PCI Write Cycle................................................................................................................................ 132

10.1.3 PCI Bus Arbitration.......................................................................................................................... 133

10.1.4 PCI Initiator Abort............................................................................................................................ 133

10.1.5 PCI Target Retry............................................................................................................................... 134

10.1.6 PCI Target Disconnect ..................................................................................................................... 134

10.1.7 PCI Target Abort .............................................................................................................................. 135

10.1.8 PCI Fast Back-to-Back ..................................................................................................................... 136

10.2 PCI CONFIGURATION REGISTER DESCRIPTION ................................................................................ 137

10.2.1 Command Bits (PCMD0).................................................................................................................. 138

10.2.2 Status Bits (PCMD0)......................................................................................................................... 139

10.2.3 Command Bits (PCMD1).................................................................................................................. 143

10.2.4 Status Bits (PCMD1)......................................................................................................................... 144

11. LOCAL BUS .............................................................................................................................. 147

11.1 GENERAL DESCRIPTION .................................................................................................................... 147

11.1.1 PCI Bridge Mode.............................................................................................................................. 149

11.1.2 Configuration Mode.......................................................................................................................... 151

11.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION....................................................... 153

11.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION................................. 155

12. JTAG........................................................................................................................................... 163

12.1 JTAG DESCRIPTION .......................................................................................................................... 163

12.2 TAP CONTROLLER STATE MACHINE DESCRIPTION ......................................................................... 164

12.3 INSTRUCTION REGISTER AND INSTRUCTIONS ................................................................................... 166

12.4 TEST REGISTERS ............................................................................................................................... 167

13. AC CHARACTERISTICS........................................................................................................ 168

14. MECHANICAL DIMENSIONS .............................................................................................. 176

14.1 256 PBGA PACKAGE ........................................................................................................................ 176

15. APPLICATIONS ....................................................................................................................... 177

15.1 16 PORT T1 OR E1 WITH 256 HDLC CHANNEL SUPPORT ................................................................ 178

15.2 DUAL T3 WITH 256 HDLC CHANNEL SUPPORT............................................................................... 179

15.3 SINGLE T3 WITH 512 HDLC CHANNEL SUPPORT ............................................................................ 180

15.4 SINGLE T3 WITH 672 HDLC CHANNEL SUPPORT ............................................................................ 181

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LIST OF FIGURES

Figure 2-1. Block Diagram....................................................................................................................................... 10

Figure 5-1. Status Register Block Diagram for SM and SV54................................................................................. 36

Figure 6-1. Layer 1 Block Diagram.......................................................................................................................... 46

Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ............................................................... 47

Figure 6-3. Layer 1 Register Set............................................................................................................................... 51

Figure 6-4. Port RAM Indirect Access ..................................................................................................................... 53

Figure 6-5. Receive V.54 Host Algorithm................................................................................................................ 58

Figure 6-6. Receive V.54 State Machine.................................................................................................................. 59

Figure 6-7. BERT Mux Diagram.............................................................................................................................. 60

Figure 6-8. BERT Register Set................................................................................................................................. 61

Figure 8-1. FIFO Example........................................................................................................................................ 75

Figure 9-1. Receive DMA Operation ....................................................................................................................... 88

Figure 9-2. Receive DMA Memory Organization.................................................................................................... 89

Figure 9-3. Receive Descriptor Example.................................................................................................................. 90

Figure 9-4. Receive Packet Descriptors.................................................................................................................... 91

Figure 9-5. Receive Free-Queue Descriptor............................................................................................................. 92

Figure 9-6. Receive Free-Queue Structure ............................................................................................................... 94

Figure 9-7. Receive Done-Queue Descriptor ........................................................................................................... 97

Figure 9-8. Receive Done-Queue Structure.............................................................................................................. 99

Figure 9-9. Receive DMA Configuration RAM..................................................................................................... 102

Figure 9-10. Transmit DMA Operation.................................................................................................................. 108

Figure 9-11. Transmit DMA Memory Organization .............................................................................................. 109

Figure 9-12. Transmit DMA Packet Handling ....................................................................................................... 110

Figure 9-13. Transmit DMA Priority Packet Handling.......................................................................................... 111

Figure 9-14. Transmit DMA Error Recovery Algorithm ....................................................................................... 113

Figure 9-15. Transmit Descriptor Example............................................................................................................ 114

Figure 9-16. Transmit Packet Descriptors.............................................................................................................. 115

Figure 9-17. Transmit Pending-Queue Descriptor ................................................................................................. 116

Figure 9-18. Transmit Pending-Queue Structure.................................................................................................... 118

Figure 9-19. Transmit Done-Queue Descriptor...................................................................................................... 120

Figure 9-20. Transmit Done-Queue Structure........................................................................................................ 122

Figure 9-21. Transmit DMA Configuration RAM ................................................................................................. 125

Figure 10-1. PCI Configuration Memory Map....................................................................................................... 130

Figure 10-2. PCI Bus Read..................................................................................................................................... 131

Figure 10-3. PCI Bus Write.................................................................................................................................... 132

Figure 10-4. PCI Bus Arbitration Signaling Protocol............................................................................................. 133

Figure 10-5. PCI Initiator Abort............................................................................................................................. 133

Figure 10-6. PCI Target Retry................................................................................................................................ 134

Figure 10-7. PCI Target Disconnect....................................................................................................................... 134

Figure 10-8. PCI Target Abort................................................................................................................................ 135

Figure 10-9. PCI Fast Back-To-Back ..................................................................................................................... 136

Figure 11-1. Bridge Mode ...................................................................................................................................... 148

Figure 11-2. Bridge Mode With Arbitration Enabled............................................................................................. 148

Figure 11-3. Configuration Mode........................................................................................................................... 149

Figure 11-4. Local Bus Access Flowchart.............................................................................................................. 152

Figure 11-5. 8-Bit Read Cycle................................................................................................................................ 155

Figure 11-6. 16-Bit Write Cycle............................................................................................................................. 156

Figure 11-7. 8-Bit Read Cycle................................................................................................................................ 157

Figure 11-8. 16-Bit Write (Only Upper 8-Bits Active) Cycle................................................................................ 158

Figure 11-9. 8-Bit Read Cycle................................................................................................................................ 159

Figure 11-10. 8-Bit Write Cycle............................................................................................................................. 160

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Figure 11-11. 16-Bit Read Cycle............................................................................................................................ 161

Figure 11-12. 8-Bit Write Cycle............................................................................................................................. 162

Figure 12-1. Block Diagram................................................................................................................................... 163

Figure 12-2. TAP Controller State Machine........................................................................................................... 164

Figure 13-1. Layer 1 Port AC Timing Diagram ..................................................................................................... 169

Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram................................................................. 170

Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.................................................... 172

Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (Continued) ............................... 173

Figure 13-5. PCI Bus Interface AC Timing Diagram............................................................................................. 174

Figure 13-6. JTAG Test Port Interface AC Timing Diagram................................................................................. 175

Figure 15-1. Application Drawing Key .................................................................................................................. 177

Figure 15-2. Single T1/E1 Line Connection........................................................................................................... 177

Figure 15-3. Quad T1/E1 Connection .................................................................................................................... 178

Figure 15-4. 16-Port T1 Application ...................................................................................................................... 178

Figure 15-5. Dual T3 Application .......................................................................................................................... 179

Figure 15-6. T3 Application (512 HDLC Channels).............................................................................................. 180

Figure 15-7. T3 Application (672 HDLC Channels).............................................................................................. 181

LIST OF TABLES

Table 1-A. Data Sheet Definitions.............................................................................................................................. 7

Table 2-A. Restrictions for Rev B1/B2 Silicon ........................................................................................................ 11

Table 2-B. Initialization Steps .................................................................................................................................. 12

Table 2-C. Indirect Registers.................................................................................................................................... 12

Table 3-A. Signal Description.................................................................................................................................. 13

Table 3-B. RS Sampled Edge................................................................................................................................... 18

Table 3-C. TS Sampled Edge ................................................................................................................................... 19

Table 4-A. Memory Map Organization.................................................................................................................... 26

Table 6-A. Channelized Port Modes ........................................................................................................................ 44

Table 6-B. Receive V.54 Search Routine................................................................................................................. 57

Table 7-A. Receive HDLC Packet Processing Outcomes........................................................................................ 67

Table 7-B. Receive HDLC Functions....................................................................................................................... 68

Table 7-C. Transmit HDLC Functions..................................................................................................................... 68

Table 8-A. FIFO Priority Algorithm Select.............................................................................................................. 74

Table 9-A. DMA Registers to be Configured by the Host on Power-Up................................................................. 84

Table 9-B. Receive DMA Main Operational Areas ................................................................................................. 86

Table 9-C. Receive Descriptor Address Storage ...................................................................................................... 90

Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation............................................... 93

Table 9-E. Receive Free-Queue Internal Address Storage ....................................................................................... 93

Table 9-F. Receive Done-Queue Internal Address Storage...................................................................................... 98

Table 9-G. Transmit DMA Main Operational Areas.............................................................................................. 106

Table 9-H. Done-Queue Error-Status Conditions................................................................................................... 112

Table 9-I. Transmit Descriptor Address Storage.................................................................................................... 114

Table 9-J. Transmit Pending-Queue Internal Address Storage .............................................................................. 117

Table 9-K. Transmit Done-Queue Internal Address Storage ................................................................................. 121

Table 11-A. Local Bus Signals............................................................................................................................... 147

Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting ................................................................................. 150

Table 11-C. Local Bus 16-Bit Width Address, Ld, LBHE Setting......................................................................... 150

Table 12-A. Instruction Codes................................................................................................................................ 166

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1. MAIN FEATURES

§ Layer 1

Can simultaneously support up to 64 T1 or E1

data streams, or two T3 data streams

16 independent physical ports capable of speeds

up to 10MHz; three ports are also capable of speeds up to 52MHz

Each port can be independently configured for

either channelized or unchannelized operation

Each physical channelized port can handle one,

two, or four T1 or E1 data streams Supports N x 64kbps and N x 56kbps On-board V.54 loopback detector On-board BERT generation and detection Per DS0 channel loopback in both directions Unchannelized loopbacks in both directions

§ HDLC

256 independent channels Up to 132Mbps throughput in both the receive

and transmit directions Transparent mode Three fast HDLC controllers capable of

operating up to 52 MHz Automatic flag detection and generation Shared opening and closing flag Interfame fill Zero stuffing and destuffing CRC16/32 checking and generation Abort detection and generation CRC error and long/short frame error detection Invert clock Invert data

§ FIFO

Large 16kB receive and 16kB transmit buffers

maximize PCI bus efficiency Small block size of 16 Bytes allows maximum

flexibility Programmable low and high watermarks Programmable HDLC channel priority setting

Governing Specifications

The DS31256 fully meets the following specifications:

· ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995

· PCI Local Bus Specification V2.1 June 1, 1995

· ITU Q.921 March 1993

· ISO Standard 3309-1979 Data Communications–HDLC Procedures–Frame Structure

§ DMA

Efficient scatter-gather DMA minimizes PCI bus

accesses (same as the DS3134 CHATEAU)

Programmable small and large buffer sizes up to

8188 Bytes and algorithm select

Descriptor bursting to conserve PCI bus

bandwidth

Identical receive and transmit descriptors

minimize host processing in store-andforward

Automatic channel disabling and enabling on

transmit errors Receive packets are timestamped Transmit packet priority setting

§ PCI Bus

32-bit, 33MHz Version 2.1 Compliant; See t5 in the PCI Bus

AC Characteristics for a 1ns exception.

Note: This does not affect real-world

designs. DS31256 V

than the PCI specification, as detailed in the

first page of Section 13 Contains extension signals that allow adoption to

custom buses Can burst up to 256 32-bit words to maximize

bus efficiency

is also slightly higher

§ Local Bus

Can operate as a bridge from the PCI bus or a

configuration bus Can arbitrate for the bus when in bridge mode Configurable as 8 or 16 bits wide Supports a 1MB address space when in bridge

mode Supports Intel and Motorola bus timing

§ JTAG Test Access

§ 3.3V low-power CMOS with 5V tolerant I/Os

§ 256-pin plastic BGA package (27mm x 27mm)

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Table 1-A. Data Sheet Definitions

The following terms are used throughout this data sheet.

Note: The DS31256’s ports are numbered 0 to 39; the HDLC channels are numbered 1 to 40. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on.

TERM DEFINITION

BERT Bit Error-Rate Tester Descriptor A message passed back and forth between the DMA and the host Dword Double word; a 32-bit data entity DMA Direct Memory Access FIFO First In, First Out. A temporary memory storage scheme. HDLC High-Level Data-Link Control Host The main controller that resides on the PCI Bus n/a Not assigned

V.54 A pseudorandom pattern that controls loopbacks (see ANSI T1.403)

2. DETAILED DESCRIPTION

This data sheet is broken into sections detailing each of the DS31256 Envoy’s blocks. See Figure 2-1 for a block diagram.

The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The DS31256 is capable of handling up to 64 T1 or E1 data streams or two T3 data streams simultaneously. Each of the 16 physical ports can handle up to two or four T1 or E1 data streams. Section 15 details a few common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC block and grooms data from the HDLC block for transmission. The block can perform both channelized and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host assigns HDLC channgels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 6.3 detect both pseudorandom and repeating bit patterns and is used to test and stress data communication links.

The HDLC Block consists of two types of HDLC controllers. There are 16 Slow HDLC Engines (one for each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to 10 Mbps in unchannelized mode. There are also three Fast HDLC Engines, which only reside on Ports 0, 1 and 2 and they are capable of operating at speeds up to 52 Mbps. Via the RP[n]CR and TP[n]CR registers in the Layer One Block, the Host will configure Ports 0, 1, and 2 to use either the Slow or the Fast HDLC engine. The HDLC Engines perform all of the Layer 2 processing, including zero stuffing and destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.

. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and

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In the receive path, the following process occurs. The HDLC Engines collect the incoming data into 32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no bearing on the priority of this data transfer. This situation is of no real concern however since the DS31256 has been designed to handle up to 132 Mbps in both the receive and transmit directions without any potential loss of data due to priority conflicts in the transfer of data from the HDLC Engines to the FIFO and vice versa.

The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the application, the selection of this algorithm can be quite important. The DS31256 cannot control when it will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which HDLC channels get top priority access to the PCI Bus when it is granted to the DS31256.

When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO (even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is ready to be transferred from the FIFO to the PCI Bus by the DMA.

In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC (Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority decoded with Port 0 generally getting the highest priority. Hence, if multiple ports are requesting packet data, the FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports before moving on to the higher numbered ports. Again there is no potential loss of data as long as the transmit throughput maximum of 132 Mbps is not exceeded. When the FIFO detects that a HDLC Engine needs data, it then transfers the data from the FIFO to the HDLC Engines in 8-bit chunks. If the FIFO detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any data available for that HDLC Channel. The DMA will know if any data is available because the Host on the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 generally getting the highest priority).

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When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled it to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords to the HDLC Engine.

One of the unique attributes of the DS31256 is the structure of the DMA. The DMA has been optimized to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere within the 32-bit address space. The user has the option on the receive side of two different buffer sizes which are called “large” and “small” but that can be set to any size up to 8188 bytes. The user has the option to store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer first and then fill large buffers as needed. The varying buffer storage options allow the user to make the best use of the available memory and to be able to balance the tradeoff between latency and bus utilization.

The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are handed back and forth from the DMA to the Host. Since this descriptor transfer utilizes bus cycles, the DMA has been structured to minimize the number of transfers required. For example on the receive side, the DMA obtains descriptors from the Host to know where in the 32-bit address space to place the incoming packet data. These descriptors are known as Free Queue Descriptors. When the DMA reads these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS31256 DMA does not need to use any more bus cycles to determine where to place the data. Other DMA architectures tend to use pointers, which require them to go back onto the bus to obtain more information and hence use more bus cycles.

Another technique that the DMA uses to maximize bus utilization is the ability to burst read and write the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions which reduces the total number of bus cycles needed.

The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions that reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.

The Local Bus Block has two modes of operation. It can be used as either a Bridge from the PCI Bus in which case it is a bus master or it can be used as a Configuration Bus in which case it is a bus slave. The Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS31256 will map data from the PCI Bus to the local bus. In the configuration mode, the local bus is used only to control and monitor the DS31256 while the HDLC packet data will still be transferred to the Host via the PCI Bus.

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Figure 2-1. Block Diagram

PRST

PREQ

PGNT

PXAS

PXDS

LWR

LINT

LRDY

LCS

LBHE

DS31256

RECEIVE DIRECTION

TRANSMIT DIRECTION

RC0 RD0

RC1 RD1

RC2 RD2

RC39 RD39

TC39 TD39

TRS

JTDI JTMS JTCL JTDO

TC0 TD0

TC1 TD1

TC2 TD2

LAYER 1 BLOCK (SECT. 6)

JTAG TEST

ACCESS

(SECT. 12)

CONTROLLERS (SECT. 7)

40-BIT SYNCHRONOUS HDLC

BERT

(SECT. 6)

FIFO BLOCK (SECT. 8)

DMA BLOCK (SECT. 9)

INTERNAL CONTROL BUS

DS31256

PCI BLOCK (SECT. 10)

(SECT. 11)

LOCAL BUS BLOC

PIN NAMES IN ( )

THE DEVICE IS IN THE MOT MODE (i.e., LIM = 1).

PCL

PAD[31:0]

CBE[3:0]

PPAR

FRAM IRD TRD STO IDSE DEVSE

PER SER

XBLAS

LA[19:0] LD[15:0]

(LR/W)

RD(LDS)

LIM

LMS

LHOLD(LBR) LHLDA(LBG)

BGAC

LCL LBPXS

RE ACTIVE WHEN

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Restrictions

In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS31256. Table 2-A lists all of the upper-bound maximum restrictions.

Table 2-A. Restrictions for Rev B1/B2 Silicon

ITEM RESTRICTION

Port Maximum of 16 channelized and unchannelized physical ports

Unchannelized

Channelized

Throughput

HDLC

*The 256 HDLC channels within the device are numbered 1 to 256.

Internal Device Configuration Registers

All internal device configuration registers (with the exception of the PCI configuration registers, which are 32-bit registers) are 16 bits wide and are not byte addressable. When the host on the PCI bus accesses these registers, the particular combination of byte enables (i.e., PCBE signals) is not important, but at least one of the byte enables must be asserted for a transaction to occur. All registers are read/write, unless otherwise noted. Not assigned (n/a) bits should be set to 0 when written to allow for future upgrades. These bits should be treated as having no meaning and could be either 0 or 1 when read.

Initialization

On a system reset (which can be invoked by either hardware action through the PRST signal or software action through the RST control bit in the master reset and ID register), all of the internal device configuration registers are set to 0 (0000h). The local bus bridge mode control register (LBBMC) is not affected by a software-invoked system reset; it is forced to all zeros only by a hardware reset. The internal registers that are accessed indirectly (these are listed as “indirect registers” in the data sheet and consist of the channelized port registers in the Layer 1 block, the DMA configuration RAMs, the HDLC configuration registers, and the FIFO registers) are not affected by a system reset, so they must be configured on power-up by the host to a proper state. Table 2-B lists the steps required to initialize the DS31256.

Note: After device power-up and reset, it takes 0.625ms to get a port up and operating, therefore, the ports must wait a minimum of 0.625ms before packet data can be processed.

Ports 0 to 2: Maximum data rate of 52Mbps Ports 3 to 15: Maximum data rate of 10 Mbps Channelized and with frame interleave interfaces or a minimum of two/multiple of two consecutive DS0 time slots assigned to one HDLC channel: 64 T1/E1 channels Channelized and with byte interleave interfaces: 64 T1/E1 channels

Maximum receive: 132Mbps

Maximum transmit: 132Mbps

Maximum of 256 channels: If the fast HDLC engine on Port 0 is being used, then it must be HDLC Channel 1* If the fast HDLC engine on Port 1 is being used, then it must be HDLC Channel 2* If the fast HDLC engine on Port 2 is being used, then it must be HDLC Channel 3*

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Table 2-B. Initialization Steps

INITIALIZATION STEP COMMENTS

1) Initialize the PCI configuration registers

2) Initialize all indirect registers

3) Configure the device for operation

4) Enable the HDLC channels

5) Load the DMA descriptors

6) Enable the DMAs

7) Enable DMA for each HDLC channel

Achieved by asserting the PIDSEL signal. It is recommended that all of the indirect registers be set to

0000h (Table 2-C Program all necessary registers, which include the Layer 1, HDLC, FIFO, and DMA registers. Done through the RCHEN and TCHEN bits in the R[n]CFG[j] and T[n]CFG[j] registers. Indicate to the DMA where packet data can be written and where pending data (if any) resides. Done through the RDE and TDE control bits in the master configuration (MC) register. Done through the channel enable bit in the receive and transmit configuration RAM.

Table 2-C. Indirect Registers

Channelized Port CP0RD to CP15RD

Receive HDLC Channel Definition RHCD 256 (one for each HDLC Channel) Transmit HDLC Channel Definition THCD 256 (one for each HDLC Channel) Receive DMA Configuration RDMAC 1536 (one for each HDLC Channel) Transmit DMA Configuration TDMAC 3072 (one for each HDLC Channel) Receive FIFO Staring Block Pointer RFSBP 256 (one for each HDLC Channel) Receive FIFO Block Pointer RFBP 1024 (one for each FIFO Block) Receive FIFO High Watermark RFHWM 256 (one for each HDLC Channel) Transmit FIFO Staring Block Pointer TFSBP 256 (one for each HDLC Channel) Transmit FIFO Block Pointer TFBP 1024 (one for each FIFO Block) Transmit FIFO Low Watermark TFLWM 256 (one for each HDLC Channel)

6144 (16 Ports x 128 DS0 Channels x 3 Registers for each DS0 Channel)

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3. SIGNAL DESCRIPTION

3.1 Overview/Signal List

This section describes the input and output signals on the DS31256. Signal names follow a convention that is shown in the Signal Naming Convention table below. Table 3-A

lists all of the signals, their signal

type, description, and pin location.

Signal Naming Convention

FIRST LETTER SIGNAL CATEGORY SECTION

R Receive Serial Port 3.2 T Transmit Serial Port 3.2 L Local Bus 3.3

J JTAG Test Port 3.4

P PCI Bus 3.5

Table 3-A. Signal Description

PIN NAME TYPE FUNCTION

V19 JTCLK I JTAG IEEE 1149.1 Test Serial Clock U18 JTDI I JTAG IEEE 1149.1 Test Serial Data Input T17 JTDO O JTAG IEEE 1149.1 Test Serial Data Output

W20 JTMS I JTAG IEEE 1149.1 Test Mode Select

U19 G20 LA0 I/O Local Bus Address Bit 0, LSB G19 LA1 I/O Local Bus Address Bit 1

F20 LA2 I/O Local Bus Address Bit 2

G18 LA3 I/O Local Bus Address Bit 3

F19 LA4 I/O Local Bus Address Bit 4 E20 LA5 I/O Local Bus Address Bit 5 G17 LA6 I/O Local Bus Address Bit 6

F18 LA7 I/O Local Bus Address Bit 7 E19 LA8 I/O Local Bus Address Bit 8 D20 LA9 I/O Local Bus Address Bit 9 E18 LA10 I/O Local Bus Address Bit 10 D19 LA11 I/O Local Bus Address Bit 11 C20 LA12 I/O Local Bus Address Bit 12 E17 LA13 I/O Local Bus Address Bit 13 D18 LA14 I/O Local Bus Address Bit 14 C19 LA15 I/O Local Bus Address Bit 15 B20 LA16 I/O Local Bus Address Bit 16 C18 LA17 I/O Local Bus Address Bit 17 B19 LA18 I/O Local Bus Address Bit 18 A20 LA19 I/O Local Bus Address Bit 19, MSB L20 H20

J20 LCLK O Local Bus Clock K19 LCS* I Local Bus Chip Select V20 LD0 I/O Local Bus Data Bit 0, LSB U20 LD1 I/O Local Bus Data Bit 1 T18 LD2 I/O Local Bus Data Bit 2 T19 LD3 I/O Local Bus Data Bit 3

JTRST

LBGACK

LBHE

I JTAG IEEE 1149.1 Test Reset

O Local Bus Grant Acknowledge O Local Bus Byte High Enable

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PIN NAME TYPE FUNCTION

T20 LD4 I/O Local Bus Data Bit 4 R18 LD5 I/O Local Bus Data Bit 5

P17 LD6 I/O Local Bus Data Bit 6 R19 LD7 I/O Local Bus Data Bit 7 R20 LD8 I/O Local Bus Data Bit 8

P18 LD9 I/O Local Bus Data Bit 9

P19 LD10 I/O Local Bus Data Bit 10

P20 LD11 I/O Local Bus Data Bit 11 N18 LD12 I/O Local Bus Data Bit 12 N19 LD13 I/O Local Bus Data Bit 13 N20 LD14 I/O Local Bus Data Bit 14

M17 LD15 I/O Local Bus Data Bit 15, MSB

L18 L19

M18 LIM I Local Bus Intel/Motorola Bus Select

K20

M19 LMS I Local Bus Mode Select

H18 K18 H19

A2, A8, A11, A19,

B2, B18, J18, J19, K1, K2, K3, L1–L3, M20, U14, W2, W9,

Y1, Y19

V17 PAD0 I/O PCI Multiplexed Address and Data Bit 0 U16 PAD1 I/O PCI Multiplexed Address and Data Bit 1 Y18 PAD2 I/O PCI Multiplexed Address and Data Bit 2

W17 PAD3 I/O PCI Multiplexed Address and Data Bit 3

V16 PAD4 I/O PCI Multiplexed Address and Data Bit 4 Y17 PAD5 I/O PCI Multiplexed Address and Data Bit 5

W16 PAD6 I/O PCI Multiplexed Address and Data Bit 6

V15 PAD7 I/O PCI Multiplexed Address and Data Bit 7

W15 PAD8 I/O PCI Multiplexed Address and Data Bit 8

V14 PAD9 I/O PCI Multiplexed Address and Data Bit 9 Y15 PAD10 I/O PCI Multiplexed Address and Data Bit 10

W14 PAD11 I/O PCI Multiplexed Address and Data Bit 11

Y14 PAD12 I/O PCI Multiplexed Address and Data Bit 12 V13 PAD13 I/O PCI Multiplexed Address and Data Bit 13

W13 PAD14 I/O PCI Multiplexed Address and Data Bit 14

Y13 PAD15 I/O PCI Multiplexed Address and Data Bit 15

V9 PAD16 I/O PCI Multiplexed Address and Data Bit 16 U9 PAD17 I/O PCI Multiplexed Address and Data Bit 17 Y8 PAD18 I/O PCI Multiplexed Address and Data Bit 18

W8 PAD19 I/O PCI Multiplexed Address and Data Bit 19

V8 PAD20 I/O PCI Multiplexed Address and Data Bit 20 Y7 PAD21 I/O PCI Multiplexed Address and Data Bit 21

W7 PAD22 I/O PCI Multiplexed Address and Data Bit 22

V7 PAD23 I/O PCI Multiplexed Address and Data Bit 23 U7 PAD24 I/O PCI Multiplexed Address and Data Bit 24 V6 PAD25 I/O PCI Multiplexed Address and Data Bit 25 Y5 PAD26 I/O PCI Multiplexed Address and Data Bit 26

LHLDA( LHOLD(

LRD (LDS)

LWR (LR/W)

LBG) LBR)

LINT

LRDY

I Local Bus Hold Acknowledge (Local Bus Grant)

O Local Bus Hold (Local Bus Request)

I/O Local Bus Interrupt

I/O Local Bus Read Enable (Local Bus Data Strobe)

I Local Bus PCI Bridge Ready

I/O Local Bus Write Enable (Local Bus Read/Write Select)

N.C. — No Connect. Do not connect any signal to this pin.

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PIN NAME TYPE FUNCTION

W5 PAD27 I/O PCI Multiplexed Address and Data Bit 27

V5 PAD28 I/O PCI Multiplexed Address and Data Bit 28 Y4 PAD29 I/O PCI Multiplexed Address and Data Bit 29 Y3 PAD30 I/O PCI Multiplexed Address and Data Bit 30

U5 PAD31 I/O PCI Multiplexed Address and Data Bit 31 Y16 V12

PCBE0 PCBE1 PCBE2 PCBE3

Y2 PCLK I

Y11

W10

PDEVSEL

PFRAME

PGNT

I/O PCI Bus Command/Byte Enable Bit 0 I/O PCI Bus Command/Byte Enable Bit 1 I/O PCI Bus Command/Byte Enable Bit 2 I/O PCI Bus Command/Byte Enable Bit 3

PCI and System Clock. A 25MHz to 33 MHz clock is applied

here. I/O PCI Device Select I/O PCI Cycle Frame

I PCI Bus Grant

Y6 PIDSEL I PCI Initialization Device Select

W18

V10

PINT

PIRDY

O PCI Interrupt

I/O PCI Initiator Ready

W12 PPAR I/O PCI Bus Parity

V11

Y12

W11

Y10 V18 Y20

W19

PPERR

PREQ

PRST PSERR PSTOP PTRDY

PXAS

PXBLAST

PXDS

I/O PCI Parity Error

O PCI Bus Request

I PCI Reset

O PCI System Error I/O PCI Stop I/O PCI Target Ready

O PCI Extension Signal: Address Strobe

O PCI Extension Signal: Burst Last

O PCI Extension Signal: Data Strobe

B1 RC0 I Receive Serial Clock for Port 0 D1 RC1 I Receive Serial Clock for Port 1

F2 RC2 I Receive Serial Clock for Port 2

H2 RC3 I Receive Serial Clock for Port 3

M1 RC4 I Receive Serial Clock for Port 4

P1 RC5 I Receive Serial Clock for Port 5 P4 RC6 I Receive Serial Clock for Port 6

V1 RC7 I Receive Serial Clock for Port 7 B17 RC8 I Receive Serial Clock for Port 8 B16 RC9 I Receive Serial Clock for Port 9 C14 RC10 I Receive Serial Clock for Port 10 D12 RC11 I Receive Serial Clock for Port 11 A10 RC12 I Receive Serial Clock for Port 12

B8 RC13 I Receive Serial Clock for Port 13

B6 RC14 I Receive Serial Clock for Port 14

C5 RC15 I Receive Serial Clock for Port 15

D2 RD0 I Receive Serial Data for Port 0

E2 RD1 I Receive Serial Data for Port 1

G3 RD2 I Receive Serial Data for Port 2

J4 RD3 I Receive Serial Data for Port 3

M3 RD4 I Receive Serial Data for Port 4

R1 RD5 I Receive Serial Data for Port 5

T2 RD6 I Receive Serial Data for Port 6

U3 RD7 I Receive Serial Data for Port 7 D16 RD8 I Receive Serial Data for Port 8

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PIN NAME TYPE FUNCTION

C15 RD9 I Receive Serial Data for Port 9 A14 RD10 I Receive Serial Data for Port 10 B12 RD11 I Receive Serial Data for Port 11 C10 RD12 I Receive Serial Data for Port 12

A7 RD13 I Receive Serial Data for Port 13

D7 RD14 I Receive Serial Data for Port 14

A3 RD15 I Receive Serial Data for Port 15

C2 RS0 I Receive Serial Sync for Port 0

E3 RS1 I Receive Serial Sync for Port 1

F1 RS2 I Receive Serial Sync for Port 2

H1 RS3 I Receive Serial Sync for Port 3

M2 RS4 I Receive Serial Sync for Port 4

P2 RS5 I Receive Serial Sync for Port 5 R3 RS6 I Receive Serial Sync for Port 6 T4 RS7 I Receive Serial Sync for Port 7

C17 RS8 I Receive Serial Sync for Port 8 A16 RS9 I Receive Serial Sync for Port 9 B14 RS10 I Receive Serial Sync for Port 10 C12 RS11 I Receive Serial Sync for Port 11 B10 RS12 I Receive Serial Sync for Port 12

C8 RS13 I Receive Serial Sync for Port 13 A5 RS14 I Receive Serial Sync for Port 14 B4 RS15 I Receive Serial Sync for Port 15 D3 TC0 I Transmit Serial Clock for Port 0 E1 TC1 I Transmit Serial Clock for Port 1 G2 TC2 I Transmit Serial Clock for Port 2

J3 TC3 I Transmit Serial Clock for Port 3

N1 TC4 I Transmit Serial Clock for Port 4

P3 TC5 I Transmit Serial Clock for Port 5 U1 TC6 I Transmit Serial Clock for Port 6 V2 TC7 I Transmit Serial Clock for Port 7

A18 TC8 I Transmit Serial Clock for Port 8 D14 TC9 I Transmit Serial Clock for Port 9 C13 TC10 I Transmit Serial Clock for Port 10 A12 TC11 I Transmit Serial Clock for Port 11

A9 TC12 I Transmit Serial Clock for Port 12 B7 TC13 I Transmit Serial Clock for Port 13 C6 TC14 I Transmit Serial Clock for Port 14 D5 TC15 I Transmit Serial Clock for Port 15 C1 TD0 O Transmit Serial Data for Port 0 G4 TD1 O Transmit Serial Data for Port 1 H3 TD2 O Transmit Serial Data for Port 2

J1 TD3 O Transmit Serial Data for Port 3 N3 TD4 O Transmit Serial Data for Port 4 T1 TD5 O Transmit Serial Data for Port 5 U2 TD6 O Transmit Serial Data for Port 6 V3 TD7 O Transmit Serial Data for Port 7

C16 TD8 O Transmit Serial Data for Port 8 A15 TD9 O Transmit Serial Data for Port 9 A13 TD10 O Transmit Serial Data for Port 10 C11 TD11 O Transmit Serial Data for Port 11

C9 TD12 O Transmit Serial Data for Port 12

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PIN NAME TYPE FUNCTION

C7 TD13 O Transmit Serial Data for Port 13 A4 TD14 O Transmit Serial Data for Port 14 B3 TD15 O Transmit Serial Data for Port 15 C3 TEST I Test. Factory tests signal; leave open circuited E4 TS0 I Transmit Serial Sync for Port 0

F3 TS1 I Transmit Serial Sync for Port 1

G1 TS2 I Transmit Serial Sync for Port 2

J2 TS3 I Transmit Serial Sync for Port 3 N2 TS4 I Transmit Serial Sync for Port 4 R2 TS5 I Transmit Serial Sync for Port 5 T3 TS6 I Transmit Serial Sync for Port 6

W1 TS7 I Transmit Serial Sync for Port 7 A17 TS8 I Transmit Serial Sync for Port 8 B15 TS9 I Transmit Serial Sync for Port 9 B13 TS10 I Transmit Serial Sync for Port 10 B11 TS11 I Transmit Serial Sync for Port 11

B9 TS12 I Transmit Serial Sync for Port 12 A6 TS13 I Transmit Serial Sync for Port 13 B5 TS14 I Transmit Serial Sync for Port 14 C4 TS15 I Transmit Serial Sync for Port 15

D6, D10, D11, D15,

F4, F17, K4, K17, L4, L17, R4, R17,

U6, U10, U11, U15

A1, D4, D8, D9,

D13, D17, H4, H17,

J17, M4, N4, N17, U4, U8, U13, U13,

U17

DS31256

VDD — Positive Supply. 3.3V (±10%)

VSS — Ground Reference

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3.2 Serial Port Interface Signal Description

Signal Name: RC0 to RC15 Signal Description: Receive Serial Clock Signal Type: Input Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz. RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name: RD0 to RD15 Signal Description: Receive Serial Data Signal Type: Input Can be sampled either on the rising edge of RC (normal clock mode) or the falling edge of RC (inverted clock mode). Unused signals should be wired low.

Signal Name: RS0 to RS15 Signal Description: Receive Serial Data Synchronization Pulse Signal Type: Input This is a one-RC clock-wide synchronization pulse that can be applied to the Envoy to force byte/frame alignment alignment. The applied sync-signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC (Table 3-B applied sync pulse can be during the first RC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks. It is acceptable to pulse the RS signal once to establish byte boundaries and allow the Envoy to track the byte/frame boundaries by counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low.

). The

Table 3-B. RS Sampled Edge

SIGNAL NORMAL RC CLOCK MODE INVERTED RC CLOCK MODE

0 RC Clock Early Mode Falling Edge Rising Edge 1/2 RC Clock Early Mode Rising Edge Falling Edge 1 RC Clock Early Mode Falling Edge Rising Edge 2 RC Clock Early Mode Falling Edge Rising Edge

Signal Name: TC0 to TC15 Signal Description: Transmit Serial Clock Signal Type: Input Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of TC. This is programmable on a per port basis. TC0 and TC1 can operate at speeds up to 52MHz. TC2– TC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name: TD0 to TD15 Signal Description: Transmit Serial Data Signal Type: Output This can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted clock mode). Data can be forced high.

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Signal Name: TS0 to TS15 Signal Description: Transmit Serial Data Synchronization Pulse Signal Type: Input This is a one-TC clock-wide synchronization pulse that can be applied to the Envoy to force byte/frame alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC (Table 3-C pulse can be during the first TC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 TC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) TC clocks. It is acceptable to pulse the TS signal once to establish byte boundaries and allow the Envoy to track the byte/frame boundaries by counting TC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low.

). The applied sync

Table 3-C. TS Sampled Edge

SIGNAL NORMAL TC CLOCK MODE INVERTED TC CLOCK MODE

0 TC Clock Early Mode Falling Edge Rising Edge 1/2 TC Clock Early Mode Rising Edge Falling Edge 1 TC Clock Early Mode Falling Edge Rising Edge 2 TC Clock Early Mode Falling Edge Rising Edge

3.3 Local Bus Signal Description

Signal Name: LMS Signal Description: Local Bus Mode Select Signal Type: Input This signal should be connected low when the device operates with no local bus access or if the local bus is used as a bridge from the PCI bus. This signal should be connected high if the local bus is to be used by an external host to configure the device. 0 = local bus is in the PCI bridge mode (master) 1 = local bus is in the configuration mode (slave)

Signal Name: LIM Signal Description: Local Bus Intel/Motorola Bus Select Signal Type: Input The signal determines whether the local bus operates in the Intel mode (LIM = 0) or the Motorola mode (LIM = 1). The signal names in parenthesis are operational when the device is in the Motorola mode. 0 = local bus is in the Intel mode 1 = local bus is in the Motorola mode

Signal Name: LD0 to LD15 Signal Description: Local Bus Nonmultiplexed Data Bus Signal Type: Input/Output (three-state capable) In PCI bridge mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When writing data to the local bus, these signals are outputs and updated on the rising edge of LCLK. When reading data from the local bus, these signals are inputs, which are sampled on the rising edge of LCLK. Depending on the assertion of the PCI byte enables (PCBE0 to PCBE3) and the local bus-width (LBW) control bit in the local bus bridge mode control register (LBBMC), this data bus uses all 16 bits (LD[15:0]) or just the lower 8 bits (LD[7:0]) or the upper 8 bits (LD[15:8]). If the upper LD bits (LD[15:8]) are used, then the local bus high-enable signal (LBHE) is asserted during the bus transaction. If the local bus is not currently involved in a bus transaction, all 16 signals are three-stated. When reading data from the local bus, these signals are outputs that are updated on the rising edge of LCLK. When writing data to the local bus, these signals become inputs, which are sampled on the rising edge of LCLK. In configuration mode (LMS = 1), the external host configures the device and obtains real-time status

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information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is not available).

Signal Name: LA0 to LA19 Signal Description: Local Bus Nonmultiplexed Address Bus Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to indicate which address to be written to or read from. These signals are three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. In configuration mode (LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active. The upper four (LA[19:16]) are ignored and should be connected low. These signals are sampled on the rising edge of LCLK to determine the internal device configuration register that the external host wishes to access.

Signal Name: LWR (LR/W) Signal Description: Local Bus Write Enable (Local Bus Read/Write Select) Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In configuration mode (LMS = 1), this signal is sampled on the rising edge of LCLK. In Intel mode (LIM = 0), it determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur.

Signal Name: LRD (LDS) Signal Description: Local Bus Read Enable (Local Bus Data Strobe) Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In configuration mode (LMS = 1), this signal is an active-low input that is sampled on the rising edge of LCLK. In Intel mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the rising edge writes data into the device.

Signal Name: LINT Signal Description: Local Bus Interrupt Signal Type: Input/Output (open drain) In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK. If asserted and unmasked, this signal causes an interrupt at the PCI bus through the PINTA signal. If not used in PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an opendrain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal remains low until either the interrupt is serviced or masked.

Signal Name: LRDY Signal Description: Local Bus PCI Bridge Ready (PCI Bridge Mode Only) Signal Type: Input This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete. This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in configuration mode (LMS = 1) and should be connected high.

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Signal Name: LHLDA (LBG) Signal Description: Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only) Signal Type: Input This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low signal. This signal is ignored and should be connected high when the local bus is in configuration mode (LMS = 1). Also, in PCI bridge mode (LMS = 0), this signal should be wired deasserted when the local bus arbitration is disabled through the LBBMC register.

Signal Name: LHOLD (LBR) Signal Description: Local Bus Hold (Local Bus Request) (PCI Bridge Mode Only) Signal Type: Output This signal is asserted when the DS31256 is attempting to control the local bus. In Intel mode (LIM = 0), this signal is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal. It is deasserted concurrently with LBGACK. This signal is three-stated when the local bus is in configuration mode (LMS = 1) and also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register.

Signal Name: LBGACK Signal Description: Local Bus Grant Acknowledge (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This active-low signal is asserted when the local bus hold-acknowledge/bus grant signal (LHLDA/LBG) has been detected and continues its assertion for a programmable (32 to 1,048,576) number of LCLKs, based on the local bus arbitration timer setting in the LBBMC register. This signal is three-stated when the local bus is in configuration mode (LMS = 1).

Signal Name: LBHE Signal Description: Local Bus Byte-High Enable (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal remains in three-state when the local bus is not involved in a bus transaction and is in configuration mode (LMS = 1).

Signal Name: LCLK Signal Description: Local Bus Clock (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated and sampled from this clock. This output is three-stated when the local bus is in configuration mode (LMS = 1). It can be disabled in the PCI bridge mode through the LBBMC register.

Signal Name: LCS Signal Description: Local Bus Chip Select (Configuration Mode Only) Signal Type: Input This active-low signal must be asserted for the device to accept a read or write command from an external host. This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high.

3.4 JTAG Signal Description

Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If unused, this signal should be pulled high.

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Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input Signal Type: Input (with internal 10kΩ pullup) Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be pulled high. This signal has an internal pullup.

Signal Name: JTDO Signal Description: JTAG IEEE 1149.1 Test Serial-Data Output Signal Type: Output Test instructions are clocked out of this signal on the falling edge of JTCLK. If unused, this signal should be left open circuited.

Signal Name: JTRST Signal Description: JTAG IEEE 1149.1 Test Reset Signal Type: Input (with internal 10kΩ pullup) This signal is used to synchronously reset the test access port controller. At power-up, JTRST must be set low and then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If boundary scan is not used, this signal should be held low. This signal has an internal pullup.

Signal Name: JTMS Signal Description: JTAG IEEE 1149.1 Test Mode Select Signal Type: Input (with internal 10kΩ pullup) This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE

1149.1 states. If unused, this signal should be pulled high. This signal has an internal pullup.

3.5 PCI Bus Signal Description

Signal Name: PCLK Signal Description: PCI and System Clock Signal Type: Input (Schmitt triggered) This clock input provides timing for the PCI bus and the device’s internal logic. A 25MHz to 33MHz clock with a nominal 50% duty cycle should be applied here.

Signal Name: PRST Signal Description: PCI Reset Signal Type: Input This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic. When forced low, this input forces all the internal logic of the device into its default state, forces the PCI outputs into three-state, and forces the TD[15:0] output port-data signals high.

Signal Name: PAD0 to PAD31 Signal Description: PCI Address and Data Multiplexed Bus Signal Type: Input/Output (three-state capable) Both address and data information are multiplexed onto these signals. Each bus transaction consists of an address phase followed by one or more data phases. Data can be either read or written in bursts. The address is transferred during the first clock cycle of a bus transaction. When the Little Endian format is selected, PAD[31:24] is the MSB of the DWORD; when Big Endian is selected, PAD[7:0] contains the MSB. When the device is an initiator, these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a write transaction. When the device is not involved in a bus transaction, these signals remain three-stated. These signals are always updated and sampled on the rising edge of PCLK.

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Signal Name: PCBE0/PCBE1/PCBE2/PCBE3 Signal Description: PCI Bus Command and Byte Enable Signal Type: Input/Output (three-state capable) Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals define the bus command. During the data phase, these signals are used as bus enables. During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is invalid; when low, the associated byte is valid. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, these signals are three-stated.

Signal Name: PPAR Signal Description: PCI Bus Parity Signal Type: Input/Output (three-state capable) This signal provides information on even parity across both the PAD address/data bus and the PCBE bus command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads. It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PPAR is three-stated.

Signal Name: PFRAME Signal Description: PCI Cycle Frame Signal Type: Input/Output (three-state capable) This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus transaction. PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is three-stated.

Signal Name: PIRDY Signal Description: PCI Initiator Ready Signal Type: Input/Output (three-state capable) The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PTRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PIRDY is deasserted when the initiator cannot temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PIRDY is three-stated.

Signal Name: PTRDY Signal Description: PCI Target Ready Signal Type: Input/Output (three-state capable) The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PIRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PTRDY is deasserted when the target cannot temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY is three-stated.

Signal Name: PSTOP Signal Description: PCI Stop Signal Type: Input/Output (three-state capable) The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this

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signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PSTOP is three-stated.

Signal Name: PIDSEL Signal Description: PCI Initialization Device Select Signal Type: Input This input signal is used as a chip select during configuration read and write transactions. This signal is disabled when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle. PIDSEL is sampled on the rising edge of PCLK.

Signal Name: PDEVSEL Signal Description: PCI Device Select Signal Type: Input/Output (three-state capable) The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is three- stated.

Signal Name: PREQ Signal Description: PCI Bus Request Signal Type: Output (three-state capable) The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is updated on the rising edge of PCLK.

Signal Name: PGNT Signal Description: PCI Bus Grant Signal Type: Input The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus transaction when it has sensed that the PFRAME signal has been deasserted.

Signal Name: PPERR Signal Description: PCI Parity Error Signal Type: Input/Output (three-state capable) This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.

Signal Name: PSERR Signal Description: PCI System Error Signal Type: Output (open drain) This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.

Signal Name: PINTA Signal Description: PCI Interrupt Signal Type: Output (open drain) This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This signal is updated on the rising edge of PCLK.

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3.6 PCI Extension Signals

These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the Envoy is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-PCI environment like an Intel i960-type bus.

Signal Name: PXAS Signal Description: PCI Extension Address Strobe Signal Type: Output This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

Signal Name: PXDS Signal Description: PCI Extension Data Strobe Signal Type: Output This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

Signal Name: PXBLAST Signal Description: PCI Extension Burst Last Signal Type: Output This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

3.7 Supply and Test Signal Description

Signal Name: TEST Signal Description: Factory Test Input Signal Type: Input (with internal 10kΩ pullup) This input should be left open-circuited by the user.

Signal Name: VDD Signal Description: Positive Supply Signal Type: n/a

3.3V (±10%). All VDD signals should be connected together.

Signal Name: VSS Signal Description: Ground Reference Signal Type: n/a All VSS signals should be connected to the local ground plane.

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4. MEMORY MAP

4.1 Introduction

All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kb (12 bits). When the PCI bus is the host (i.e., the local bus is in bridge mode), the actual 32-bit PCI bus addresses of the internal device configuration registers are obtained by adding the DC base address value in the PCI device-configuration memory-base address register (Section 10.2) to the offset listed in Sections 4.1 to 4.10. When an external host is configuring the device through the local bus (i.e., the local bus is in the configuration mode), the offset is 0h and the host on the local bus uses the 16-bit addresses listed in Sections 4.2 to 4.10.

Table 4-A. Memory Map Organization

General Configuration Registers (0x000) (00xx) 4.2 Receive Port Registers (0x1xx) (01xx) 4.3 Transmit Port Registers (0x2xx) (02xx) 4.4 Channelized Port Registers (0x3xx) (03xx) 4.6 HDLC Registers (0x4xx) (04xx) 4.6 BERT Registers (0x5xx) (05xx) 4.7 Receive DMA Registers (0x7xx) (07xx) 4.8 Transmit DMA Registers (0x8xx) (08xx) 4.9 FIFO Registers (0x9xx) (09xx) 4.10 PCI Configuration Registers for Function 0 (PIDSEL) (0Axx) 4.11 PCI Configuration Registers for Function 1 (PIDSEL) (0Bxx) 4.12

PCI HOST [OFFSET

FROM DC BASE]

LOCAL BUS HOST

(16-BIT ADDRESS)

SECTION

4.2 General Configuration Registers (0xx)

OFFSET/

ADDRESS

0000 MRID Master Reset and ID Register 5.1 0010 MC Master Configuration 5.2 0020 SM Master Status Register 5.3.2 0024 ISM Interrupt Mask Register for SM 5.3.2 0028 SDMA Status Register for DMA 5.3.2

002C ISDMA Interrupt Mask Register for SDMA 5.3.2

0030 SV54 Status Register for V.54 Loopback Detector 5.3.2 0034 ISV54 Interrupt Mask Register for SV.54 5.3.2 0040 LBBMC Local Bus Bridge Mode Control Register 11.2 0050 TEST Test Register 5.4

NAME REGISTER SECTION

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4.3 Receive Port Registers (1xx)

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OFFSET/

ADDRESS

NAME REGISTER SECTION

0100 RP0CR Receive Port 0 Control Register 6.2 0104 RP1CR Receive Port 1 Control Register 6.2 0108 RP2CR Receive Port 2 Control Register 6.2 010C RP3CR Receive Port 3 Control Register 6.2 0110 RP4CR Receive Port 4 Control Register 6.2 0114 RP5CR Receive Port 5 Control Register 6.2 0118 RP6CR Receive Port 6 Control Register 6.2 011C RP7CR Receive Port 7 Control Register 6.2 0120 RP8CR Receive Port 8 Control Register 6.2 0124 RP9CR Receive Port 9 Control Register 6.2 0128 RP10CR Receive Port 10 Control Register 6.2 012C RP11CR Receive Port 11 Control Register 6.2 0130 RP12CR Receive Port 12 Control Register 6.2 0134 RP13CR Receive Port 13 Control Register 6.2 0138 RP14CR Receive Port 14 Control Register 6.2 013C RP15CR Receive Port 15 Control Register 6.2

4.4 Transmit Port Registers (2xx)

OFFSET/

ADDRESS

0200 TP0CR Transmit Port 0 Control Register 6.2 0204 TP1CR Transmit Port 1 Control Register 6.2 0208 TP2CR Transmit Port 2 Control Register 6.2

020C TP3CR Transmit Port 3 Control Register 6.2

0210 TP4CR Transmit Port 4 Control Register 6.2 0214 TP5CR Transmit Port 5 Control Register 6.2 0218 TP6CR Transmit Port 6 Control Register 6.2

021C TP7CR Transmit Port 7 Control Register 6.2

0220 TP8CR Transmit Port 8 Control Register 6.2 0224 TP9CR Transmit Port 9 Control Register 6.2 0228 TP10CR Transmit Port 10 Control Register 6.2

022C TP11CR Transmit Port 11 Control Register 6.2

0230 TP12CR Transmit Port 12 Control Register 6.2 0234 TP13CR Transmit Port 13 Control Register 6.2 0238 TP14CR Transmit Port 14 Control Register 6.2

023C TP15CR Transmit Port 15 Control Register 6.2

NAME REGISTER SECTION

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4.5 Channelized Port Registers (3xx)

OFFSET/

ADDRESS

0300 CP0RDIS Channelized Port 0 Register Data Indirect Select 6.3 0304 CP0RD Channelized Port 0 Register Data 6.3 0308 CP1RDIS Channelized Port 1 Register Data Indirect Select 6.3 030C CP1RD Channelized Port 1 Register Data 6.3 0310 CP2RDIS Channelized Port 2 Register Data Indirect Select 6.3 0314 CP2RD Channelized Port 2 Register Data 6.3 0318 CP3RDIS Channelized Port 3 Register Data Indirect Select 6.3 031C CP3RD Channelized Port 3 Register Data 6.3 0320 CP4RDIS Channelized Port 4 Register Data Indirect Select 6.3 0324 CP4RD Channelized Port 4 Register Data 6.3 0328 CP5RDIS Channelized Port 5 Register Data Indirect Select 6.3 032C CP5RD Channelized Port 5 Register Data 6.3 0330 CP6RDIS Channelized Port 6 Register Data Indirect Select 6.3 0334 CP6RD Channelized Port 6 Register Data 6.3 0338 CP7RDIS Channelized Port 7 Register Data Indirect Select 6.3 033C CP7RD Channelized Port 7 Register Data 6.3 0340 CP8RDIS Channelized Port 8 Register Data Indirect Select 6.3 0344 CP8RD Channelized Port 8 Register Data 6.3 0348 CP9RDIS Channelized Port 9 Register Data Indirect Select 6.3 034C CP9RD Channelized Port 9 Register Data. 6.3 0350 CP10RDIS Channelized Port 10 Register Data Indirect Select. 6.3 0354 CP10RD Channelized Port 10 Register Data. 6.3 0358 CP11RDIS Channelized Port 11 Register Data Indirect Select. 6.3 035C CP11RD Channelized Port 11 Register Data 6.3 0360 CP12RDIS Channelized Port 12 Register Data Indirect Select 6.3 0364 CP12RD Channelized Port 12 Register Data 6.3 0368 CP13RDIS Channelized Port 13 Register Data Indirect Select 6.3 036C CP13RD Channelized Port 13 Register Data 6.3 0370 CP14RDIS Channelized Port 14 Register Data Indirect Select 6.3 0374 CP14RD Channelized Port 14 Register Data 6.3 0378 CP15RDIS Channelized Port 15 Register Data Indirect Select 6.3 037C CP15RD Channelized Port 15 Register Data 6.3

NAME REGISTER SECTION

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4.6 HDLC Registers (4xx)

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OFFSET/

ADDRESS

0400 RHCDIS Receive HDLC Channel Definition Indirect Select 7.2 0404 RHCD Receive HDLC Channel Definition 7.2 0410 RHPL Receive HDLC maximum Packet Length. One per device. 7.2 0480 THCDIS Transmit HDLC Channel Definition Indirect Select 7.2 0484 THCD Transmit HDLC Channel Definition 7.2

NAME REGISTER SECTION

4.7 BERT Registers (5xx)

OFFSET/

ADDRESS

0500 BERTC0 BERT Control 0 6.6 0504 BERTC1 BERT Control 1 6.6 0508 BERTRP0 BERT Repetitive Pattern Set 0 (lower word) 6.6

050C BERTRP1 BERT Repetitive Pattern Set 1 (upper word) 6.6

0510 BERTBC0 BERT Bit Counter 0 (lower word) 6.6 0514 BERTBC1 BERT Bit Counter 1 (upper word) 6.6 0518 BERTEC0 BERT Error Counter 0 (lower word) 6.6

051C BERTEC1 BERT Error Counter 1 (upper word) 6.6

NAME REGISTER SECTION

4.8 Receive DMA Registers (7xx)

OFFSET/

ADDRESS

NAME REGISTER SECTION

0700 RFQBA0 Receive Free-Queue Base Address 0 (lower word) 9.2.3 0704 RFQBA1 Receive Free-Queue Base Address 1 (upper word) 9.2.3 0708 RFQEA Receive Free-Queue End Address 9.2.3

070C RFQSBSA Receive Free-Queue Small Buffer Start Address 9.2.3

0710 RFQLBWP Receive Free-Queue Large Buffer Host Write Pointer 9.2.3 0714 RFQSBWP Receive Free-Queue Small Buffer Host Write Pointer 9.2.3 0718 RFQLBRP Receive Free-Queue Large Buffer DMA Read Pointer 9.2.3

071C RFQSBRP Receive Free-Queue Small Buffer DMA Read Pointer 9.2.3

0730 RDQBA0 Receive Done-Queue Base Address 0 (lower word) 9.2.4 0734 RDQBA1 Receive Done-Queue Base Address 1 (upper word) 9.2.4 0738 RDQEA Receive Done-Queue End Address 9.2.4

073C RDQRP Receive Done-Queue Host Read Pointer 9.2.4

0740 RDQWP Receive Done-Queue DMA Write Pointer 9.2.4 0744 RDQFFT Receive Done-Queue FIFO Flush Timer 9.2.4 0750 RDBA0 Receive Descriptor Base Address 0 (lower word) 9.2.2 0754 RDBA1 Receive Descriptor Base Address 1 (upper word) 9.2.2 0770 RDMACIS Receive DMA Configuration Indirect Select 9.3.5 0774 RDMAC Receive DMA Configuration 9.3.5 0780 RDMAQ Receive DMA Queues Control 9.2.3/9.2.4 0790 RLBS Receive Large Buffer Size 9.2.1 0794 RSBS Receive Small Buffer Size 9.2.1

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4.9 Transmit DMA Registers (8xx)

OFFSET/

ADDRESS

0800 TPQBA0 Transmit Pending-Queue Base Address 0 (lower word) 9.3.3 0804 TPQBA1 Transmit Pending-Queue Base Address 1 (upper word) 9.3.3 0808 TPQEA Transmit Pending-Queue End Address 9.3.3

080C TPQWP Transmit Pending-Queue Host Write Pointer 9.3.3

0810 TPQRP Transmit Pending-Queue DMA Read Pointer 9.3.3 0830 TDQBA0 Transmit Done-Queue Base Address 0 (lower word) 9.3.4 0834 TDQBA1 Transmit Done-Queue Base Address 1 (upper word) 9.3.4 0838 TDQEA Transmit Done-Queue End Address 9.3.4

083C TDQRP Transmit Done-Queue Host Read Pointer 9.3.4

0840 TDQWP Transmit Done-Queue DMA Write Pointer 9.3.4 0844 TDQFFT Transmit Done-Queue FIFO Flush Timer 9.3.4 0850 TDBA0 Transmit Descriptor Base Address 0 (lower word) 9.3.2 0854 TDBA1 Transmit Descriptor Base Address 1 (upper word) 9.3.2 0870 TDMACIS Transmit DMA Configuration Indirect Select 9.3.5 0874 TDMAC Transmit DMA Configuration 9.3.5 0880 TDMAQ Transmit DMA Queues Control 9.3.3/9.3.4

4.10 FIFO Registers (9xx)

OFFSET/

ADDRESS

0900 RFSBPIS Receive FIFO Starting Block Pointer Indirect Select 8.2 0904 RFSBP Receive FIFO Starting Block Pointer 8.2 0910 RFBPIS Receive FIFO Block Pointer Indirect Select 8.2 0914 RFBP Receive FIFO Block Pointer 8.2 0920 RFHWMIS Receive FIFO High-Watermark Indirect Select 8.2 0924 RFHWM Receive FIFO High Watermark 8.2 0980 TFSBPIS Transmit FIFO Starting Block Pointer Indirect Select 8.2 0984 TFSBP Transmit FIFO Starting Block Pointer 8.2 0990 TFBPIS Transmit FIFO Block Pointer Indirect Select 8.2

0994 TFBP Transmit FIFO Block Pointer 8.2 09A0 TFLWMIS Transmit FIFO Low-Watermark Indirect Select 8.2 09A4 TFLWM Transmit FIFO Low Watermark 8.2

NAME REGISTER SECTION

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