Rainbow Electronics DS31256 User Manual

www.maxim-ic.com

GENERAL DESCRIPTION

The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The Envoy is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.

There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The Envoy also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps.

APPLICATIONS

Channelized and Clear-Channel

(Unchannelized) T1/E1 and T3/E3 Routers with Multilink PPP Support High-Density Frame-Relay Access xDSL Access Multiplexers (DSLAMs) Triple HSSI High-Density V.35 SONET/SDH EOC/ECC Termination

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS31256 0°C to +70°C

256 PBGA

DEMO KIT AVAILABLE

DS31256 Envoy

256-Channel, High-Throughput

HDLC Controlle

FEATURES

§ 256 Independent, Bidirectional HDLC channels

§ Up to 132Mbps Full-Duplex Throughput

§ Supports Up to 64 T1 or E1 Data Streams

§ 16 Physical Ports (16 Tx and 16 Rx) That

Can Be Independently Configured for Channelized or Unchannelized Operation

§ Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized)

§ Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines

§ Per-Channel DS0 Loopbacks in Both Directions

§ Over-Subscription at the Port Level

§ Transparent Mode Supported

§ On-Board Bit Error-Rate Tester (BERT)

with Automatic Error Insertion Capability

§ BERT function Can Be Assigned to Any HDLC Channel or Any Port

§ Large 16kB FIFO in Both Receive and Transmit Directions

§ Efficient Scatter/Gather DMA Maximizes Memory Efficiency

§ Receive Data Packets are Time-Stamped

§ Transmit Packet Priority Setting

§ V.54 Loopback Code Detector

§ Local Bus Allows for PCI Bridging or Local

Access

§ Intel or Motorola Bus Signals Supported

§ Backward Compatibility with DS3134

§ 33MHz 32-Bit PCI (V2.1) Interface

§ 3.3V Low-Power CMOS with 5V Tolerant

I/O

§ JTAG Support IEEE 1149.1

§ 256-Pin Plastic BGA (27mm x 27mm)

Features continued on page 6.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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TABLE OF CONTENTS

1. MAIN FEATURES........................................................................................................................ 6

2. DETAILED DESCRIPTION........................................................................................................ 7

3. SIGNAL DESCRIPTION ........................................................................................................... 13

3.1 OVERVIEW/SIGNAL LIST.............................................................................................................................. 13

3.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION ......................................................................................... 18

3.3 LOCAL BUS SIGNAL DESCRIPTION .............................................................................................................. 19

3.4 JTAG SIGNAL DESCRIPTION ....................................................................................................................... 21

3.5 PCI BUS SIGNAL DESCRIPTION ................................................................................................................... 22

3.6 PCI EXTENSION SIGNALS ............................................................................................................................ 25

3.7 SUPPLY AND TEST SIGNAL DESCRIPTION.................................................................................................... 25

4. MEMORY MAP .......................................................................................................................... 26

4.1 INTRODUCTION ............................................................................................................................................ 26

4.2 GENERAL CONFIGURATION REGISTERS (0XX) ............................................................................................ 26

4.3 RECEIVE PORT REGISTERS (1XX) ................................................................................................................ 27

4.4 TRANSMIT PORT REGISTERS (2XX).............................................................................................................. 27

4.5 CHANNELIZED PORT REGISTERS (3XX) ....................................................................................................... 28

4.6 HDLC REGISTERS (4XX) ............................................................................................................................. 29

4.7 BERT REGISTERS (5XX).............................................................................................................................. 29

4.8 RECEIVE DMA REGISTERS (7XX)................................................................................................................ 29

4.9 TRANSMIT DMA REGISTERS (8XX)............................................................................................................. 30

4.10 FIFO REGISTERS (9XX)....................................................................................................................... 30

4.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX).................................................. 31

4.12 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX) .................................................. 31

5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT ............................ 32

5.1 MASTER RESET AND ID REGISTER DESCRIPTION ....................................................................................... 32

5.2 MASTER CONFIGURATION REGISTER DESCRIPTION.................................................................................... 32

5.3 STATUS AND INTERRUPT ............................................................................................................................. 34

5.3.1 General Description of Operation...................................................................................................... 34

5.3.2 Status and Interrupt Register Description .......................................................................................... 37

5.4 TEST REGISTER DESCRIPTION ..................................................................................................................... 43

6. LAYER 1 ...................................................................................................................................... 44

6.1 GENERAL DESCRIPTION............................................................................................................................... 44

6.2 PORT REGISTER DESCRIPTIONS ................................................................................................................... 48

6.3 LAYER 1 CONFIGURATION REGISTER DESCRIPTION ................................................................................... 51

6.4 RECEIVE V.54 DETECTOR............................................................................................................................ 56

6.5 BERT........................................................................................................................................................... 60

6.6 BERT REGISTER DESCRIPTION ................................................................................................................... 61

7. HDLC............................................................................................................................................ 67

7.1 GENERAL DESCRIPTION............................................................................................................................... 67

7.2 HDLC REGISTER DESCRIPTION................................................................................................................... 69

8. FIFO.............................................................................................................................................. 74

8.1 GENERAL DESCRIPTION AND EXAMPLE ...................................................................................................... 74

8.1.1 Receive High Watermark.................................................................................................................... 76

8.1.2 Transmit Low Watermark ................................................................................................................... 76

8.2 FIFO REGISTER DESCRIPTION..................................................................................................................... 76

9. DMA.............................................................................................................................................. 83

9.1 INTRODUCTION ............................................................................................................................................ 83

9.2 RECEIVE SIDE .............................................................................................................................................. 85

9.2.1 Overview ............................................................................................................................................. 85

9.2.2 Packet Descriptors.............................................................................................................................. 90

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9.2.3 Free Queue ......................................................................................................................................... 92

9.2.4 Done Queue ........................................................................................................................................ 97

9.2.5 DMA Channel Configuration RAM .................................................................................................. 102

9.3 TRANSMIT SIDE.......................................................................................................................................... 105

9.3.1 Overview ........................................................................................................................................... 105

9.3.2 Packet Descriptors............................................................................................................................ 114

9.3.3 Pending Queue.................................................................................................................................. 116

9.3.4 Done Queue ...................................................................................................................................... 120

9.3.5 DMA Configuration RAM................................................................................................................. 125

10. PCI BUS...................................................................................................................................... 130

10.1 GENERAL DESCRIPTION OF OPERATION ........................................................................................... 130

10.1.1 PCI Read Cycle................................................................................................................................. 131

10.1.2 PCI Write Cycle................................................................................................................................ 132

10.1.3 PCI Bus Arbitration.......................................................................................................................... 133

10.1.4 PCI Initiator Abort............................................................................................................................ 133

10.1.5 PCI Target Retry............................................................................................................................... 134

10.1.6 PCI Target Disconnect ..................................................................................................................... 134

10.1.7 PCI Target Abort .............................................................................................................................. 135

10.1.8 PCI Fast Back-to-Back ..................................................................................................................... 136

10.2 PCI CONFIGURATION REGISTER DESCRIPTION ................................................................................ 137

10.2.1 Command Bits (PCMD0).................................................................................................................. 138

10.2.2 Status Bits (PCMD0)......................................................................................................................... 139

10.2.3 Command Bits (PCMD1).................................................................................................................. 143

10.2.4 Status Bits (PCMD1)......................................................................................................................... 144

11. LOCAL BUS .............................................................................................................................. 147

11.1 GENERAL DESCRIPTION .................................................................................................................... 147

11.1.1 PCI Bridge Mode.............................................................................................................................. 149

11.1.2 Configuration Mode.......................................................................................................................... 151

11.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION....................................................... 153

11.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION................................. 155

12. JTAG........................................................................................................................................... 163

12.1 JTAG DESCRIPTION .......................................................................................................................... 163

12.2 TAP CONTROLLER STATE MACHINE DESCRIPTION ......................................................................... 164

12.3 INSTRUCTION REGISTER AND INSTRUCTIONS ................................................................................... 166

12.4 TEST REGISTERS ............................................................................................................................... 167

13. AC CHARACTERISTICS........................................................................................................ 168

14. MECHANICAL DIMENSIONS .............................................................................................. 176

14.1 256 PBGA PACKAGE ........................................................................................................................ 176

15. APPLICATIONS ....................................................................................................................... 177

15.1 16 PORT T1 OR E1 WITH 256 HDLC CHANNEL SUPPORT ................................................................ 178

15.2 DUAL T3 WITH 256 HDLC CHANNEL SUPPORT............................................................................... 179

15.3 SINGLE T3 WITH 512 HDLC CHANNEL SUPPORT ............................................................................ 180

15.4 SINGLE T3 WITH 672 HDLC CHANNEL SUPPORT ............................................................................ 181

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LIST OF FIGURES

Figure 2-1. Block Diagram....................................................................................................................................... 10

Figure 5-1. Status Register Block Diagram for SM and SV54................................................................................. 36

Figure 6-1. Layer 1 Block Diagram.......................................................................................................................... 46

Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ............................................................... 47

Figure 6-3. Layer 1 Register Set............................................................................................................................... 51

Figure 6-4. Port RAM Indirect Access ..................................................................................................................... 53

Figure 6-5. Receive V.54 Host Algorithm................................................................................................................ 58

Figure 6-6. Receive V.54 State Machine.................................................................................................................. 59

Figure 6-7. BERT Mux Diagram.............................................................................................................................. 60

Figure 6-8. BERT Register Set................................................................................................................................. 61

Figure 8-1. FIFO Example........................................................................................................................................ 75

Figure 9-1. Receive DMA Operation ....................................................................................................................... 88

Figure 9-2. Receive DMA Memory Organization.................................................................................................... 89

Figure 9-3. Receive Descriptor Example.................................................................................................................. 90

Figure 9-4. Receive Packet Descriptors.................................................................................................................... 91

Figure 9-5. Receive Free-Queue Descriptor............................................................................................................. 92

Figure 9-6. Receive Free-Queue Structure ............................................................................................................... 94

Figure 9-7. Receive Done-Queue Descriptor ........................................................................................................... 97

Figure 9-8. Receive Done-Queue Structure.............................................................................................................. 99

Figure 9-9. Receive DMA Configuration RAM..................................................................................................... 102

Figure 9-10. Transmit DMA Operation.................................................................................................................. 108

Figure 9-11. Transmit DMA Memory Organization .............................................................................................. 109

Figure 9-12. Transmit DMA Packet Handling ....................................................................................................... 110

Figure 9-13. Transmit DMA Priority Packet Handling.......................................................................................... 111

Figure 9-14. Transmit DMA Error Recovery Algorithm ....................................................................................... 113

Figure 9-15. Transmit Descriptor Example............................................................................................................ 114

Figure 9-16. Transmit Packet Descriptors.............................................................................................................. 115

Figure 9-17. Transmit Pending-Queue Descriptor ................................................................................................. 116

Figure 9-18. Transmit Pending-Queue Structure.................................................................................................... 118

Figure 9-19. Transmit Done-Queue Descriptor...................................................................................................... 120

Figure 9-20. Transmit Done-Queue Structure........................................................................................................ 122

Figure 9-21. Transmit DMA Configuration RAM ................................................................................................. 125

Figure 10-1. PCI Configuration Memory Map....................................................................................................... 130

Figure 10-2. PCI Bus Read..................................................................................................................................... 131

Figure 10-3. PCI Bus Write.................................................................................................................................... 132

Figure 10-4. PCI Bus Arbitration Signaling Protocol............................................................................................. 133

Figure 10-5. PCI Initiator Abort............................................................................................................................. 133

Figure 10-6. PCI Target Retry................................................................................................................................ 134

Figure 10-7. PCI Target Disconnect....................................................................................................................... 134

Figure 10-8. PCI Target Abort................................................................................................................................ 135

Figure 10-9. PCI Fast Back-To-Back ..................................................................................................................... 136

Figure 11-1. Bridge Mode ...................................................................................................................................... 148

Figure 11-2. Bridge Mode With Arbitration Enabled............................................................................................. 148

Figure 11-3. Configuration Mode........................................................................................................................... 149

Figure 11-4. Local Bus Access Flowchart.............................................................................................................. 152

Figure 11-5. 8-Bit Read Cycle................................................................................................................................ 155

Figure 11-6. 16-Bit Write Cycle............................................................................................................................. 156

Figure 11-7. 8-Bit Read Cycle................................................................................................................................ 157

Figure 11-8. 16-Bit Write (Only Upper 8-Bits Active) Cycle................................................................................ 158

Figure 11-9. 8-Bit Read Cycle................................................................................................................................ 159

Figure 11-10. 8-Bit Write Cycle............................................................................................................................. 160

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Figure 11-11. 16-Bit Read Cycle............................................................................................................................ 161

Figure 11-12. 8-Bit Write Cycle............................................................................................................................. 162

Figure 12-1. Block Diagram................................................................................................................................... 163

Figure 12-2. TAP Controller State Machine........................................................................................................... 164

Figure 13-1. Layer 1 Port AC Timing Diagram ..................................................................................................... 169

Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram................................................................. 170

Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.................................................... 172

Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (Continued) ............................... 173

Figure 13-5. PCI Bus Interface AC Timing Diagram............................................................................................. 174

Figure 13-6. JTAG Test Port Interface AC Timing Diagram................................................................................. 175

Figure 15-1. Application Drawing Key .................................................................................................................. 177

Figure 15-2. Single T1/E1 Line Connection........................................................................................................... 177

Figure 15-3. Quad T1/E1 Connection .................................................................................................................... 178

Figure 15-4. 16-Port T1 Application ...................................................................................................................... 178

Figure 15-5. Dual T3 Application .......................................................................................................................... 179

Figure 15-6. T3 Application (512 HDLC Channels).............................................................................................. 180

Figure 15-7. T3 Application (672 HDLC Channels).............................................................................................. 181

LIST OF TABLES

Table 1-A. Data Sheet Definitions.............................................................................................................................. 7

Table 2-A. Restrictions for Rev B1/B2 Silicon ........................................................................................................ 11

Table 2-B. Initialization Steps .................................................................................................................................. 12

Table 2-C. Indirect Registers.................................................................................................................................... 12

Table 3-A. Signal Description.................................................................................................................................. 13

Table 3-B. RS Sampled Edge................................................................................................................................... 18

Table 3-C. TS Sampled Edge ................................................................................................................................... 19

Table 4-A. Memory Map Organization.................................................................................................................... 26

Table 6-A. Channelized Port Modes ........................................................................................................................ 44

Table 6-B. Receive V.54 Search Routine................................................................................................................. 57

Table 7-A. Receive HDLC Packet Processing Outcomes........................................................................................ 67

Table 7-B. Receive HDLC Functions....................................................................................................................... 68

Table 7-C. Transmit HDLC Functions..................................................................................................................... 68

Table 8-A. FIFO Priority Algorithm Select.............................................................................................................. 74

Table 9-A. DMA Registers to be Configured by the Host on Power-Up................................................................. 84

Table 9-B. Receive DMA Main Operational Areas ................................................................................................. 86

Table 9-C. Receive Descriptor Address Storage ...................................................................................................... 90

Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation............................................... 93

Table 9-E. Receive Free-Queue Internal Address Storage ....................................................................................... 93

Table 9-F. Receive Done-Queue Internal Address Storage...................................................................................... 98

Table 9-G. Transmit DMA Main Operational Areas.............................................................................................. 106

Table 9-H. Done-Queue Error-Status Conditions................................................................................................... 112

Table 9-I. Transmit Descriptor Address Storage.................................................................................................... 114

Table 9-J. Transmit Pending-Queue Internal Address Storage .............................................................................. 117

Table 9-K. Transmit Done-Queue Internal Address Storage ................................................................................. 121

Table 11-A. Local Bus Signals............................................................................................................................... 147

Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting ................................................................................. 150

Table 11-C. Local Bus 16-Bit Width Address, Ld, LBHE Setting......................................................................... 150

Table 12-A. Instruction Codes................................................................................................................................ 166

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1. MAIN FEATURES

§ Layer 1

Can simultaneously support up to 64 T1 or E1

data streams, or two T3 data streams

16 independent physical ports capable of speeds

up to 10MHz; three ports are also capable of speeds up to 52MHz

Each port can be independently configured for

either channelized or unchannelized operation

Each physical channelized port can handle one,

two, or four T1 or E1 data streams Supports N x 64kbps and N x 56kbps On-board V.54 loopback detector On-board BERT generation and detection Per DS0 channel loopback in both directions Unchannelized loopbacks in both directions

§ HDLC

256 independent channels Up to 132Mbps throughput in both the receive

and transmit directions Transparent mode Three fast HDLC controllers capable of

operating up to 52 MHz Automatic flag detection and generation Shared opening and closing flag Interfame fill Zero stuffing and destuffing CRC16/32 checking and generation Abort detection and generation CRC error and long/short frame error detection Invert clock Invert data

§ FIFO

Large 16kB receive and 16kB transmit buffers

maximize PCI bus efficiency Small block size of 16 Bytes allows maximum

flexibility Programmable low and high watermarks Programmable HDLC channel priority setting

Governing Specifications

The DS31256 fully meets the following specifications:

· ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995

· PCI Local Bus Specification V2.1 June 1, 1995

· ITU Q.921 March 1993

· ISO Standard 3309-1979 Data Communications–HDLC Procedures–Frame Structure

§ DMA

Efficient scatter-gather DMA minimizes PCI bus

accesses (same as the DS3134 CHATEAU)

Programmable small and large buffer sizes up to

8188 Bytes and algorithm select

Descriptor bursting to conserve PCI bus

bandwidth

Identical receive and transmit descriptors

minimize host processing in store-andforward

Automatic channel disabling and enabling on

transmit errors Receive packets are timestamped Transmit packet priority setting

§ PCI Bus

32-bit, 33MHz Version 2.1 Compliant; See t5 in the PCI Bus

AC Characteristics for a 1ns exception.

Note: This does not affect real-world

designs. DS31256 V

than the PCI specification, as detailed in the

first page of Section 13 Contains extension signals that allow adoption to

custom buses Can burst up to 256 32-bit words to maximize

bus efficiency

is also slightly higher

§ Local Bus

Can operate as a bridge from the PCI bus or a

configuration bus Can arbitrate for the bus when in bridge mode Configurable as 8 or 16 bits wide Supports a 1MB address space when in bridge

mode Supports Intel and Motorola bus timing

§ JTAG Test Access

§ 3.3V low-power CMOS with 5V tolerant I/Os

§ 256-pin plastic BGA package (27mm x 27mm)

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Table 1-A. Data Sheet Definitions

The following terms are used throughout this data sheet.

Note: The DS31256’s ports are numbered 0 to 39; the HDLC channels are numbered 1 to 40. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on.

TERM DEFINITION

BERT Bit Error-Rate Tester Descriptor A message passed back and forth between the DMA and the host Dword Double word; a 32-bit data entity DMA Direct Memory Access FIFO First In, First Out. A temporary memory storage scheme. HDLC High-Level Data-Link Control Host The main controller that resides on the PCI Bus n/a Not assigned

V.54 A pseudorandom pattern that controls loopbacks (see ANSI T1.403)

2. DETAILED DESCRIPTION

This data sheet is broken into sections detailing each of the DS31256 Envoy’s blocks. See Figure 2-1 for a block diagram.

The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The DS31256 is capable of handling up to 64 T1 or E1 data streams or two T3 data streams simultaneously. Each of the 16 physical ports can handle up to two or four T1 or E1 data streams. Section 15 details a few common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC block and grooms data from the HDLC block for transmission. The block can perform both channelized and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host assigns HDLC channgels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 6.3 detect both pseudorandom and repeating bit patterns and is used to test and stress data communication links.

The HDLC Block consists of two types of HDLC controllers. There are 16 Slow HDLC Engines (one for each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to 10 Mbps in unchannelized mode. There are also three Fast HDLC Engines, which only reside on Ports 0, 1 and 2 and they are capable of operating at speeds up to 52 Mbps. Via the RP[n]CR and TP[n]CR registers in the Layer One Block, the Host will configure Ports 0, 1, and 2 to use either the Slow or the Fast HDLC engine. The HDLC Engines perform all of the Layer 2 processing, including zero stuffing and destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.

. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and

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In the receive path, the following process occurs. The HDLC Engines collect the incoming data into 32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no bearing on the priority of this data transfer. This situation is of no real concern however since the DS31256 has been designed to handle up to 132 Mbps in both the receive and transmit directions without any potential loss of data due to priority conflicts in the transfer of data from the HDLC Engines to the FIFO and vice versa.

The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the application, the selection of this algorithm can be quite important. The DS31256 cannot control when it will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which HDLC channels get top priority access to the PCI Bus when it is granted to the DS31256.

When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO (even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is ready to be transferred from the FIFO to the PCI Bus by the DMA.

In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC (Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority decoded with Port 0 generally getting the highest priority. Hence, if multiple ports are requesting packet data, the FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports before moving on to the higher numbered ports. Again there is no potential loss of data as long as the transmit throughput maximum of 132 Mbps is not exceeded. When the FIFO detects that a HDLC Engine needs data, it then transfers the data from the FIFO to the HDLC Engines in 8-bit chunks. If the FIFO detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any data available for that HDLC Channel. The DMA will know if any data is available because the Host on the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the DMA will handle next via a Host configurable algorithm, which allows the selection to be either round robin or priority, decoded (with HDLC Channel 1 generally getting the highest priority).

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When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled it to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords to the HDLC Engine.

One of the unique attributes of the DS31256 is the structure of the DMA. The DMA has been optimized to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere within the 32-bit address space. The user has the option on the receive side of two different buffer sizes which are called “large” and “small” but that can be set to any size up to 8188 bytes. The user has the option to store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer first and then fill large buffers as needed. The varying buffer storage options allow the user to make the best use of the available memory and to be able to balance the tradeoff between latency and bus utilization.

The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are handed back and forth from the DMA to the Host. Since this descriptor transfer utilizes bus cycles, the DMA has been structured to minimize the number of transfers required. For example on the receive side, the DMA obtains descriptors from the Host to know where in the 32-bit address space to place the incoming packet data. These descriptors are known as Free Queue Descriptors. When the DMA reads these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS31256 DMA does not need to use any more bus cycles to determine where to place the data. Other DMA architectures tend to use pointers, which require them to go back onto the bus to obtain more information and hence use more bus cycles.

Another technique that the DMA uses to maximize bus utilization is the ability to burst read and write the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions which reduces the total number of bus cycles needed.

The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions that reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.

The Local Bus Block has two modes of operation. It can be used as either a Bridge from the PCI Bus in which case it is a bus master or it can be used as a Configuration Bus in which case it is a bus slave. The Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS31256 will map data from the PCI Bus to the local bus. In the configuration mode, the local bus is used only to control and monitor the DS31256 while the HDLC packet data will still be transferred to the Host via the PCI Bus.

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Figure 2-1. Block Diagram

PRST

PREQ

PGNT

PXAS

PXDS

LWR

LINT

LRDY

LCS

LBHE

DS31256

RECEIVE DIRECTION

TRANSMIT DIRECTION

RC0 RD0

RC1 RD1

RC2 RD2

RC39 RD39

TC39 TD39

TRS

JTDI JTMS JTCL JTDO

TC0 TD0

TC1 TD1

TC2 TD2

LAYER 1 BLOCK (SECT. 6)

JTAG TEST

ACCESS

(SECT. 12)

CONTROLLERS (SECT. 7)

40-BIT SYNCHRONOUS HDLC

BERT

(SECT. 6)

FIFO BLOCK (SECT. 8)

DMA BLOCK (SECT. 9)

INTERNAL CONTROL BUS

DS31256

PCI BLOCK (SECT. 10)

(SECT. 11)

LOCAL BUS BLOC

PIN NAMES IN ( )

THE DEVICE IS IN THE MOT MODE (i.e., LIM = 1).

PCL

PAD[31:0]

CBE[3:0]

PPAR

FRAM IRD TRD STO IDSE DEVSE

PER SER

XBLAS

LA[19:0] LD[15:0]

(LR/W)

RD(LDS)

LIM

LMS

LHOLD(LBR) LHLDA(LBG)

BGAC

LCL LBPXS

RE ACTIVE WHEN

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Restrictions

In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS31256. Table 2-A lists all of the upper-bound maximum restrictions.

Table 2-A. Restrictions for Rev B1/B2 Silicon

ITEM RESTRICTION

Port Maximum of 16 channelized and unchannelized physical ports

Unchannelized

Channelized

Throughput

HDLC

*The 256 HDLC channels within the device are numbered 1 to 256.

Internal Device Configuration Registers

All internal device configuration registers (with the exception of the PCI configuration registers, which are 32-bit registers) are 16 bits wide and are not byte addressable. When the host on the PCI bus accesses these registers, the particular combination of byte enables (i.e., PCBE signals) is not important, but at least one of the byte enables must be asserted for a transaction to occur. All registers are read/write, unless otherwise noted. Not assigned (n/a) bits should be set to 0 when written to allow for future upgrades. These bits should be treated as having no meaning and could be either 0 or 1 when read.

Initialization

On a system reset (which can be invoked by either hardware action through the PRST signal or software action through the RST control bit in the master reset and ID register), all of the internal device configuration registers are set to 0 (0000h). The local bus bridge mode control register (LBBMC) is not affected by a software-invoked system reset; it is forced to all zeros only by a hardware reset. The internal registers that are accessed indirectly (these are listed as “indirect registers” in the data sheet and consist of the channelized port registers in the Layer 1 block, the DMA configuration RAMs, the HDLC configuration registers, and the FIFO registers) are not affected by a system reset, so they must be configured on power-up by the host to a proper state. Table 2-B lists the steps required to initialize the DS31256.

Note: After device power-up and reset, it takes 0.625ms to get a port up and operating, therefore, the ports must wait a minimum of 0.625ms before packet data can be processed.

Ports 0 to 2: Maximum data rate of 52Mbps Ports 3 to 15: Maximum data rate of 10 Mbps Channelized and with frame interleave interfaces or a minimum of two/multiple of two consecutive DS0 time slots assigned to one HDLC channel: 64 T1/E1 channels Channelized and with byte interleave interfaces: 64 T1/E1 channels

Maximum receive: 132Mbps

Maximum transmit: 132Mbps

Maximum of 256 channels: If the fast HDLC engine on Port 0 is being used, then it must be HDLC Channel 1* If the fast HDLC engine on Port 1 is being used, then it must be HDLC Channel 2* If the fast HDLC engine on Port 2 is being used, then it must be HDLC Channel 3*

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Table 2-B. Initialization Steps

INITIALIZATION STEP COMMENTS

1) Initialize the PCI configuration registers

2) Initialize all indirect registers

3) Configure the device for operation

4) Enable the HDLC channels

5) Load the DMA descriptors

6) Enable the DMAs

7) Enable DMA for each HDLC channel

Achieved by asserting the PIDSEL signal. It is recommended that all of the indirect registers be set to

0000h (Table 2-C Program all necessary registers, which include the Layer 1, HDLC, FIFO, and DMA registers. Done through the RCHEN and TCHEN bits in the R[n]CFG[j] and T[n]CFG[j] registers. Indicate to the DMA where packet data can be written and where pending data (if any) resides. Done through the RDE and TDE control bits in the master configuration (MC) register. Done through the channel enable bit in the receive and transmit configuration RAM.

Table 2-C. Indirect Registers

Channelized Port CP0RD to CP15RD

Receive HDLC Channel Definition RHCD 256 (one for each HDLC Channel) Transmit HDLC Channel Definition THCD 256 (one for each HDLC Channel) Receive DMA Configuration RDMAC 1536 (one for each HDLC Channel) Transmit DMA Configuration TDMAC 3072 (one for each HDLC Channel) Receive FIFO Staring Block Pointer RFSBP 256 (one for each HDLC Channel) Receive FIFO Block Pointer RFBP 1024 (one for each FIFO Block) Receive FIFO High Watermark RFHWM 256 (one for each HDLC Channel) Transmit FIFO Staring Block Pointer TFSBP 256 (one for each HDLC Channel) Transmit FIFO Block Pointer TFBP 1024 (one for each FIFO Block) Transmit FIFO Low Watermark TFLWM 256 (one for each HDLC Channel)

6144 (16 Ports x 128 DS0 Channels x 3 Registers for each DS0 Channel)

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3. SIGNAL DESCRIPTION

3.1 Overview/Signal List

This section describes the input and output signals on the DS31256. Signal names follow a convention that is shown in the Signal Naming Convention table below. Table 3-A

lists all of the signals, their signal

type, description, and pin location.

Signal Naming Convention

FIRST LETTER SIGNAL CATEGORY SECTION

R Receive Serial Port 3.2 T Transmit Serial Port 3.2 L Local Bus 3.3

J JTAG Test Port 3.4

P PCI Bus 3.5

Table 3-A. Signal Description

PIN NAME TYPE FUNCTION

V19 JTCLK I JTAG IEEE 1149.1 Test Serial Clock U18 JTDI I JTAG IEEE 1149.1 Test Serial Data Input T17 JTDO O JTAG IEEE 1149.1 Test Serial Data Output

W20 JTMS I JTAG IEEE 1149.1 Test Mode Select

U19 G20 LA0 I/O Local Bus Address Bit 0, LSB G19 LA1 I/O Local Bus Address Bit 1

F20 LA2 I/O Local Bus Address Bit 2

G18 LA3 I/O Local Bus Address Bit 3

F19 LA4 I/O Local Bus Address Bit 4 E20 LA5 I/O Local Bus Address Bit 5 G17 LA6 I/O Local Bus Address Bit 6

F18 LA7 I/O Local Bus Address Bit 7 E19 LA8 I/O Local Bus Address Bit 8 D20 LA9 I/O Local Bus Address Bit 9 E18 LA10 I/O Local Bus Address Bit 10 D19 LA11 I/O Local Bus Address Bit 11 C20 LA12 I/O Local Bus Address Bit 12 E17 LA13 I/O Local Bus Address Bit 13 D18 LA14 I/O Local Bus Address Bit 14 C19 LA15 I/O Local Bus Address Bit 15 B20 LA16 I/O Local Bus Address Bit 16 C18 LA17 I/O Local Bus Address Bit 17 B19 LA18 I/O Local Bus Address Bit 18 A20 LA19 I/O Local Bus Address Bit 19, MSB L20 H20

J20 LCLK O Local Bus Clock K19 LCS* I Local Bus Chip Select V20 LD0 I/O Local Bus Data Bit 0, LSB U20 LD1 I/O Local Bus Data Bit 1 T18 LD2 I/O Local Bus Data Bit 2 T19 LD3 I/O Local Bus Data Bit 3

JTRST

LBGACK

LBHE

I JTAG IEEE 1149.1 Test Reset

O Local Bus Grant Acknowledge O Local Bus Byte High Enable

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PIN NAME TYPE FUNCTION

T20 LD4 I/O Local Bus Data Bit 4 R18 LD5 I/O Local Bus Data Bit 5

P17 LD6 I/O Local Bus Data Bit 6 R19 LD7 I/O Local Bus Data Bit 7 R20 LD8 I/O Local Bus Data Bit 8

P18 LD9 I/O Local Bus Data Bit 9

P19 LD10 I/O Local Bus Data Bit 10

P20 LD11 I/O Local Bus Data Bit 11 N18 LD12 I/O Local Bus Data Bit 12 N19 LD13 I/O Local Bus Data Bit 13 N20 LD14 I/O Local Bus Data Bit 14

M17 LD15 I/O Local Bus Data Bit 15, MSB

L18 L19

M18 LIM I Local Bus Intel/Motorola Bus Select

K20

M19 LMS I Local Bus Mode Select

H18 K18 H19

A2, A8, A11, A19,

B2, B18, J18, J19, K1, K2, K3, L1–L3, M20, U14, W2, W9,

Y1, Y19

V17 PAD0 I/O PCI Multiplexed Address and Data Bit 0 U16 PAD1 I/O PCI Multiplexed Address and Data Bit 1 Y18 PAD2 I/O PCI Multiplexed Address and Data Bit 2

W17 PAD3 I/O PCI Multiplexed Address and Data Bit 3

V16 PAD4 I/O PCI Multiplexed Address and Data Bit 4 Y17 PAD5 I/O PCI Multiplexed Address and Data Bit 5

W16 PAD6 I/O PCI Multiplexed Address and Data Bit 6

V15 PAD7 I/O PCI Multiplexed Address and Data Bit 7

W15 PAD8 I/O PCI Multiplexed Address and Data Bit 8

V14 PAD9 I/O PCI Multiplexed Address and Data Bit 9 Y15 PAD10 I/O PCI Multiplexed Address and Data Bit 10

W14 PAD11 I/O PCI Multiplexed Address and Data Bit 11

Y14 PAD12 I/O PCI Multiplexed Address and Data Bit 12 V13 PAD13 I/O PCI Multiplexed Address and Data Bit 13

W13 PAD14 I/O PCI Multiplexed Address and Data Bit 14

Y13 PAD15 I/O PCI Multiplexed Address and Data Bit 15

V9 PAD16 I/O PCI Multiplexed Address and Data Bit 16 U9 PAD17 I/O PCI Multiplexed Address and Data Bit 17 Y8 PAD18 I/O PCI Multiplexed Address and Data Bit 18

W8 PAD19 I/O PCI Multiplexed Address and Data Bit 19

V8 PAD20 I/O PCI Multiplexed Address and Data Bit 20 Y7 PAD21 I/O PCI Multiplexed Address and Data Bit 21

W7 PAD22 I/O PCI Multiplexed Address and Data Bit 22

V7 PAD23 I/O PCI Multiplexed Address and Data Bit 23 U7 PAD24 I/O PCI Multiplexed Address and Data Bit 24 V6 PAD25 I/O PCI Multiplexed Address and Data Bit 25 Y5 PAD26 I/O PCI Multiplexed Address and Data Bit 26

LHLDA( LHOLD(

LRD (LDS)

LWR (LR/W)

LBG) LBR)

LINT

LRDY

I Local Bus Hold Acknowledge (Local Bus Grant)

O Local Bus Hold (Local Bus Request)

I/O Local Bus Interrupt

I/O Local Bus Read Enable (Local Bus Data Strobe)

I Local Bus PCI Bridge Ready

I/O Local Bus Write Enable (Local Bus Read/Write Select)

N.C. — No Connect. Do not connect any signal to this pin.

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PIN NAME TYPE FUNCTION

W5 PAD27 I/O PCI Multiplexed Address and Data Bit 27

V5 PAD28 I/O PCI Multiplexed Address and Data Bit 28 Y4 PAD29 I/O PCI Multiplexed Address and Data Bit 29 Y3 PAD30 I/O PCI Multiplexed Address and Data Bit 30

U5 PAD31 I/O PCI Multiplexed Address and Data Bit 31 Y16 V12

PCBE0 PCBE1 PCBE2 PCBE3

Y2 PCLK I

Y11

W10

PDEVSEL

PFRAME

PGNT

I/O PCI Bus Command/Byte Enable Bit 0 I/O PCI Bus Command/Byte Enable Bit 1 I/O PCI Bus Command/Byte Enable Bit 2 I/O PCI Bus Command/Byte Enable Bit 3

PCI and System Clock. A 25MHz to 33 MHz clock is applied

here. I/O PCI Device Select I/O PCI Cycle Frame

I PCI Bus Grant

Y6 PIDSEL I PCI Initialization Device Select

W18

V10

PINT

PIRDY

O PCI Interrupt

I/O PCI Initiator Ready

W12 PPAR I/O PCI Bus Parity

V11

Y12

W11

Y10 V18 Y20

W19

PPERR

PREQ

PRST PSERR PSTOP PTRDY

PXAS

PXBLAST

PXDS

I/O PCI Parity Error

O PCI Bus Request

I PCI Reset

O PCI System Error I/O PCI Stop I/O PCI Target Ready

O PCI Extension Signal: Address Strobe

O PCI Extension Signal: Burst Last

O PCI Extension Signal: Data Strobe

B1 RC0 I Receive Serial Clock for Port 0 D1 RC1 I Receive Serial Clock for Port 1

F2 RC2 I Receive Serial Clock for Port 2

H2 RC3 I Receive Serial Clock for Port 3

M1 RC4 I Receive Serial Clock for Port 4

P1 RC5 I Receive Serial Clock for Port 5 P4 RC6 I Receive Serial Clock for Port 6

V1 RC7 I Receive Serial Clock for Port 7 B17 RC8 I Receive Serial Clock for Port 8 B16 RC9 I Receive Serial Clock for Port 9 C14 RC10 I Receive Serial Clock for Port 10 D12 RC11 I Receive Serial Clock for Port 11 A10 RC12 I Receive Serial Clock for Port 12

B8 RC13 I Receive Serial Clock for Port 13

B6 RC14 I Receive Serial Clock for Port 14

C5 RC15 I Receive Serial Clock for Port 15

D2 RD0 I Receive Serial Data for Port 0

E2 RD1 I Receive Serial Data for Port 1

G3 RD2 I Receive Serial Data for Port 2

J4 RD3 I Receive Serial Data for Port 3

M3 RD4 I Receive Serial Data for Port 4

R1 RD5 I Receive Serial Data for Port 5

T2 RD6 I Receive Serial Data for Port 6

U3 RD7 I Receive Serial Data for Port 7 D16 RD8 I Receive Serial Data for Port 8

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PIN NAME TYPE FUNCTION

C15 RD9 I Receive Serial Data for Port 9 A14 RD10 I Receive Serial Data for Port 10 B12 RD11 I Receive Serial Data for Port 11 C10 RD12 I Receive Serial Data for Port 12

A7 RD13 I Receive Serial Data for Port 13

D7 RD14 I Receive Serial Data for Port 14

A3 RD15 I Receive Serial Data for Port 15

C2 RS0 I Receive Serial Sync for Port 0

E3 RS1 I Receive Serial Sync for Port 1

F1 RS2 I Receive Serial Sync for Port 2

H1 RS3 I Receive Serial Sync for Port 3

M2 RS4 I Receive Serial Sync for Port 4

P2 RS5 I Receive Serial Sync for Port 5 R3 RS6 I Receive Serial Sync for Port 6 T4 RS7 I Receive Serial Sync for Port 7

C17 RS8 I Receive Serial Sync for Port 8 A16 RS9 I Receive Serial Sync for Port 9 B14 RS10 I Receive Serial Sync for Port 10 C12 RS11 I Receive Serial Sync for Port 11 B10 RS12 I Receive Serial Sync for Port 12

C8 RS13 I Receive Serial Sync for Port 13 A5 RS14 I Receive Serial Sync for Port 14 B4 RS15 I Receive Serial Sync for Port 15 D3 TC0 I Transmit Serial Clock for Port 0 E1 TC1 I Transmit Serial Clock for Port 1 G2 TC2 I Transmit Serial Clock for Port 2

J3 TC3 I Transmit Serial Clock for Port 3

N1 TC4 I Transmit Serial Clock for Port 4

P3 TC5 I Transmit Serial Clock for Port 5 U1 TC6 I Transmit Serial Clock for Port 6 V2 TC7 I Transmit Serial Clock for Port 7

A18 TC8 I Transmit Serial Clock for Port 8 D14 TC9 I Transmit Serial Clock for Port 9 C13 TC10 I Transmit Serial Clock for Port 10 A12 TC11 I Transmit Serial Clock for Port 11

A9 TC12 I Transmit Serial Clock for Port 12 B7 TC13 I Transmit Serial Clock for Port 13 C6 TC14 I Transmit Serial Clock for Port 14 D5 TC15 I Transmit Serial Clock for Port 15 C1 TD0 O Transmit Serial Data for Port 0 G4 TD1 O Transmit Serial Data for Port 1 H3 TD2 O Transmit Serial Data for Port 2

J1 TD3 O Transmit Serial Data for Port 3 N3 TD4 O Transmit Serial Data for Port 4 T1 TD5 O Transmit Serial Data for Port 5 U2 TD6 O Transmit Serial Data for Port 6 V3 TD7 O Transmit Serial Data for Port 7

C16 TD8 O Transmit Serial Data for Port 8 A15 TD9 O Transmit Serial Data for Port 9 A13 TD10 O Transmit Serial Data for Port 10 C11 TD11 O Transmit Serial Data for Port 11

C9 TD12 O Transmit Serial Data for Port 12

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PIN NAME TYPE FUNCTION

C7 TD13 O Transmit Serial Data for Port 13 A4 TD14 O Transmit Serial Data for Port 14 B3 TD15 O Transmit Serial Data for Port 15 C3 TEST I Test. Factory tests signal; leave open circuited E4 TS0 I Transmit Serial Sync for Port 0

F3 TS1 I Transmit Serial Sync for Port 1

G1 TS2 I Transmit Serial Sync for Port 2

J2 TS3 I Transmit Serial Sync for Port 3 N2 TS4 I Transmit Serial Sync for Port 4 R2 TS5 I Transmit Serial Sync for Port 5 T3 TS6 I Transmit Serial Sync for Port 6

W1 TS7 I Transmit Serial Sync for Port 7 A17 TS8 I Transmit Serial Sync for Port 8 B15 TS9 I Transmit Serial Sync for Port 9 B13 TS10 I Transmit Serial Sync for Port 10 B11 TS11 I Transmit Serial Sync for Port 11

B9 TS12 I Transmit Serial Sync for Port 12 A6 TS13 I Transmit Serial Sync for Port 13 B5 TS14 I Transmit Serial Sync for Port 14 C4 TS15 I Transmit Serial Sync for Port 15

D6, D10, D11, D15,

F4, F17, K4, K17, L4, L17, R4, R17,

U6, U10, U11, U15

A1, D4, D8, D9,

D13, D17, H4, H17,

J17, M4, N4, N17, U4, U8, U13, U13,

U17

DS31256

VDD — Positive Supply. 3.3V (±10%)

VSS — Ground Reference

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3.2 Serial Port Interface Signal Description

Signal Name: RC0 to RC15 Signal Description: Receive Serial Clock Signal Type: Input Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz. RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name: RD0 to RD15 Signal Description: Receive Serial Data Signal Type: Input Can be sampled either on the rising edge of RC (normal clock mode) or the falling edge of RC (inverted clock mode). Unused signals should be wired low.

Signal Name: RS0 to RS15 Signal Description: Receive Serial Data Synchronization Pulse Signal Type: Input This is a one-RC clock-wide synchronization pulse that can be applied to the Envoy to force byte/frame alignment alignment. The applied sync-signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC (Table 3-B applied sync pulse can be during the first RC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks. It is acceptable to pulse the RS signal once to establish byte boundaries and allow the Envoy to track the byte/frame boundaries by counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low.

). The

Table 3-B. RS Sampled Edge

SIGNAL NORMAL RC CLOCK MODE INVERTED RC CLOCK MODE

0 RC Clock Early Mode Falling Edge Rising Edge 1/2 RC Clock Early Mode Rising Edge Falling Edge 1 RC Clock Early Mode Falling Edge Rising Edge 2 RC Clock Early Mode Falling Edge Rising Edge

Signal Name: TC0 to TC15 Signal Description: Transmit Serial Clock Signal Type: Input Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of TC. This is programmable on a per port basis. TC0 and TC1 can operate at speeds up to 52MHz. TC2– TC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name: TD0 to TD15 Signal Description: Transmit Serial Data Signal Type: Output This can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted clock mode). Data can be forced high.

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Signal Name: TS0 to TS15 Signal Description: Transmit Serial Data Synchronization Pulse Signal Type: Input This is a one-TC clock-wide synchronization pulse that can be applied to the Envoy to force byte/frame alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low (inverted sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC (Table 3-C pulse can be during the first TC clock period of a 193/256/512/1024-bit frame or it can be applied 1/2, 1, or 2 TC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) TC clocks. It is acceptable to pulse the TS signal once to establish byte boundaries and allow the Envoy to track the byte/frame boundaries by counting TC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low.

). The applied sync

Table 3-C. TS Sampled Edge

SIGNAL NORMAL TC CLOCK MODE INVERTED TC CLOCK MODE

0 TC Clock Early Mode Falling Edge Rising Edge 1/2 TC Clock Early Mode Rising Edge Falling Edge 1 TC Clock Early Mode Falling Edge Rising Edge 2 TC Clock Early Mode Falling Edge Rising Edge

3.3 Local Bus Signal Description

Signal Name: LMS Signal Description: Local Bus Mode Select Signal Type: Input This signal should be connected low when the device operates with no local bus access or if the local bus is used as a bridge from the PCI bus. This signal should be connected high if the local bus is to be used by an external host to configure the device. 0 = local bus is in the PCI bridge mode (master) 1 = local bus is in the configuration mode (slave)

Signal Name: LIM Signal Description: Local Bus Intel/Motorola Bus Select Signal Type: Input The signal determines whether the local bus operates in the Intel mode (LIM = 0) or the Motorola mode (LIM = 1). The signal names in parenthesis are operational when the device is in the Motorola mode. 0 = local bus is in the Intel mode 1 = local bus is in the Motorola mode

Signal Name: LD0 to LD15 Signal Description: Local Bus Nonmultiplexed Data Bus Signal Type: Input/Output (three-state capable) In PCI bridge mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When writing data to the local bus, these signals are outputs and updated on the rising edge of LCLK. When reading data from the local bus, these signals are inputs, which are sampled on the rising edge of LCLK. Depending on the assertion of the PCI byte enables (PCBE0 to PCBE3) and the local bus-width (LBW) control bit in the local bus bridge mode control register (LBBMC), this data bus uses all 16 bits (LD[15:0]) or just the lower 8 bits (LD[7:0]) or the upper 8 bits (LD[15:8]). If the upper LD bits (LD[15:8]) are used, then the local bus high-enable signal (LBHE) is asserted during the bus transaction. If the local bus is not currently involved in a bus transaction, all 16 signals are three-stated. When reading data from the local bus, these signals are outputs that are updated on the rising edge of LCLK. When writing data to the local bus, these signals become inputs, which are sampled on the rising edge of LCLK. In configuration mode (LMS = 1), the external host configures the device and obtains real-time status

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information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is not available).

Signal Name: LA0 to LA19 Signal Description: Local Bus Nonmultiplexed Address Bus Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to indicate which address to be written to or read from. These signals are three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. In configuration mode (LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active. The upper four (LA[19:16]) are ignored and should be connected low. These signals are sampled on the rising edge of LCLK to determine the internal device configuration register that the external host wishes to access.

Signal Name: LWR (LR/W) Signal Description: Local Bus Write Enable (Local Bus Read/Write Select) Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In configuration mode (LMS = 1), this signal is sampled on the rising edge of LCLK. In Intel mode (LIM = 0), it determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal determines whether a read or write is to occur.

Signal Name: LRD (LDS) Signal Description: Local Bus Read Enable (Local Bus Data Strobe) Signal Type: Input/Output (three-state capable) In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In configuration mode (LMS = 1), this signal is an active-low input that is sampled on the rising edge of LCLK. In Intel mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the rising edge writes data into the device.

Signal Name: LINT Signal Description: Local Bus Interrupt Signal Type: Input/Output (open drain) In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK. If asserted and unmasked, this signal causes an interrupt at the PCI bus through the PINTA signal. If not used in PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an opendrain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal remains low until either the interrupt is serviced or masked.

Signal Name: LRDY Signal Description: Local Bus PCI Bridge Ready (PCI Bridge Mode Only) Signal Type: Input This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete. This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in configuration mode (LMS = 1) and should be connected high.

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Signal Name: LHLDA (LBG) Signal Description: Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only) Signal Type: Input This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low signal. This signal is ignored and should be connected high when the local bus is in configuration mode (LMS = 1). Also, in PCI bridge mode (LMS = 0), this signal should be wired deasserted when the local bus arbitration is disabled through the LBBMC register.

Signal Name: LHOLD (LBR) Signal Description: Local Bus Hold (Local Bus Request) (PCI Bridge Mode Only) Signal Type: Output This signal is asserted when the DS31256 is attempting to control the local bus. In Intel mode (LIM = 0), this signal is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal. It is deasserted concurrently with LBGACK. This signal is three-stated when the local bus is in configuration mode (LMS = 1) and also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register.

Signal Name: LBGACK Signal Description: Local Bus Grant Acknowledge (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This active-low signal is asserted when the local bus hold-acknowledge/bus grant signal (LHLDA/LBG) has been detected and continues its assertion for a programmable (32 to 1,048,576) number of LCLKs, based on the local bus arbitration timer setting in the LBBMC register. This signal is three-stated when the local bus is in configuration mode (LMS = 1).

Signal Name: LBHE Signal Description: Local Bus Byte-High Enable (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal remains in three-state when the local bus is not involved in a bus transaction and is in configuration mode (LMS = 1).

Signal Name: LCLK Signal Description: Local Bus Clock (PCI Bridge Mode Only) Signal Type: Output (three-state capable) This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated and sampled from this clock. This output is three-stated when the local bus is in configuration mode (LMS = 1). It can be disabled in the PCI bridge mode through the LBBMC register.

Signal Name: LCS Signal Description: Local Bus Chip Select (Configuration Mode Only) Signal Type: Input This active-low signal must be asserted for the device to accept a read or write command from an external host. This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high.

3.4 JTAG Signal Description

Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If unused, this signal should be pulled high.

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Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input Signal Type: Input (with internal 10kΩ pullup) Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be pulled high. This signal has an internal pullup.

Signal Name: JTDO Signal Description: JTAG IEEE 1149.1 Test Serial-Data Output Signal Type: Output Test instructions are clocked out of this signal on the falling edge of JTCLK. If unused, this signal should be left open circuited.

Signal Name: JTRST Signal Description: JTAG IEEE 1149.1 Test Reset Signal Type: Input (with internal 10kΩ pullup) This signal is used to synchronously reset the test access port controller. At power-up, JTRST must be set low and then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If boundary scan is not used, this signal should be held low. This signal has an internal pullup.

Signal Name: JTMS Signal Description: JTAG IEEE 1149.1 Test Mode Select Signal Type: Input (with internal 10kΩ pullup) This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE

1149.1 states. If unused, this signal should be pulled high. This signal has an internal pullup.

3.5 PCI Bus Signal Description

Signal Name: PCLK Signal Description: PCI and System Clock Signal Type: Input (Schmitt triggered) This clock input provides timing for the PCI bus and the device’s internal logic. A 25MHz to 33MHz clock with a nominal 50% duty cycle should be applied here.

Signal Name: PRST Signal Description: PCI Reset Signal Type: Input This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic. When forced low, this input forces all the internal logic of the device into its default state, forces the PCI outputs into three-state, and forces the TD[15:0] output port-data signals high.

Signal Name: PAD0 to PAD31 Signal Description: PCI Address and Data Multiplexed Bus Signal Type: Input/Output (three-state capable) Both address and data information are multiplexed onto these signals. Each bus transaction consists of an address phase followed by one or more data phases. Data can be either read or written in bursts. The address is transferred during the first clock cycle of a bus transaction. When the Little Endian format is selected, PAD[31:24] is the MSB of the DWORD; when Big Endian is selected, PAD[7:0] contains the MSB. When the device is an initiator, these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a write transaction. When the device is not involved in a bus transaction, these signals remain three-stated. These signals are always updated and sampled on the rising edge of PCLK.

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Signal Name: PCBE0/PCBE1/PCBE2/PCBE3 Signal Description: PCI Bus Command and Byte Enable Signal Type: Input/Output (three-state capable) Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals define the bus command. During the data phase, these signals are used as bus enables. During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is invalid; when low, the associated byte is valid. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, these signals are three-stated.

Signal Name: PPAR Signal Description: PCI Bus Parity Signal Type: Input/Output (three-state capable) This signal provides information on even parity across both the PAD address/data bus and the PCBE bus command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads. It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PPAR is three-stated.

Signal Name: PFRAME Signal Description: PCI Cycle Frame Signal Type: Input/Output (three-state capable) This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus transaction. PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is three-stated.

Signal Name: PIRDY Signal Description: PCI Initiator Ready Signal Type: Input/Output (three-state capable) The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PTRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PIRDY is deasserted when the initiator cannot temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PIRDY is three-stated.

Signal Name: PTRDY Signal Description: PCI Target Ready Signal Type: Input/Output (three-state capable) The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue sending/accepting data. This signal handshakes with the PIRDY signal during a bus transaction to control the rate at which data transfers across the bus. During a bus transaction, PTRDY is deasserted when the target cannot temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY is three-stated.

Signal Name: PSTOP Signal Description: PCI Stop Signal Type: Input/Output (three-state capable) The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this

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signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PSTOP is three-stated.

Signal Name: PIDSEL Signal Description: PCI Initialization Device Select Signal Type: Input This input signal is used as a chip select during configuration read and write transactions. This signal is disabled when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle. PIDSEL is sampled on the rising edge of PCLK.

Signal Name: PDEVSEL Signal Description: PCI Device Select Signal Type: Input/Output (three-state capable) The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is three- stated.

Signal Name: PREQ Signal Description: PCI Bus Request Signal Type: Output (three-state capable) The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is updated on the rising edge of PCLK.

Signal Name: PGNT Signal Description: PCI Bus Grant Signal Type: Input The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus transaction when it has sensed that the PFRAME signal has been deasserted.

Signal Name: PPERR Signal Description: PCI Parity Error Signal Type: Input/Output (three-state capable) This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.

Signal Name: PSERR Signal Description: PCI System Error Signal Type: Output (open drain) This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.

Signal Name: PINTA Signal Description: PCI Interrupt Signal Type: Output (open drain) This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This signal is updated on the rising edge of PCLK.

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3.6 PCI Extension Signals

These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the Envoy is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-PCI environment like an Intel i960-type bus.

Signal Name: PXAS Signal Description: PCI Extension Address Strobe Signal Type: Output This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

Signal Name: PXDS Signal Description: PCI Extension Data Strobe Signal Type: Output This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

Signal Name: PXBLAST Signal Description: PCI Extension Burst Last Signal Type: Output This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK.

3.7 Supply and Test Signal Description

Signal Name: TEST Signal Description: Factory Test Input Signal Type: Input (with internal 10kΩ pullup) This input should be left open-circuited by the user.

Signal Name: VDD Signal Description: Positive Supply Signal Type: n/a

3.3V (±10%). All VDD signals should be connected together.

Signal Name: VSS Signal Description: Ground Reference Signal Type: n/a All VSS signals should be connected to the local ground plane.

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4. MEMORY MAP

4.1 Introduction

All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kb (12 bits). When the PCI bus is the host (i.e., the local bus is in bridge mode), the actual 32-bit PCI bus addresses of the internal device configuration registers are obtained by adding the DC base address value in the PCI device-configuration memory-base address register (Section 10.2) to the offset listed in Sections 4.1 to 4.10. When an external host is configuring the device through the local bus (i.e., the local bus is in the configuration mode), the offset is 0h and the host on the local bus uses the 16-bit addresses listed in Sections 4.2 to 4.10.

Table 4-A. Memory Map Organization

General Configuration Registers (0x000) (00xx) 4.2 Receive Port Registers (0x1xx) (01xx) 4.3 Transmit Port Registers (0x2xx) (02xx) 4.4 Channelized Port Registers (0x3xx) (03xx) 4.6 HDLC Registers (0x4xx) (04xx) 4.6 BERT Registers (0x5xx) (05xx) 4.7 Receive DMA Registers (0x7xx) (07xx) 4.8 Transmit DMA Registers (0x8xx) (08xx) 4.9 FIFO Registers (0x9xx) (09xx) 4.10 PCI Configuration Registers for Function 0 (PIDSEL) (0Axx) 4.11 PCI Configuration Registers for Function 1 (PIDSEL) (0Bxx) 4.12

PCI HOST [OFFSET

FROM DC BASE]

LOCAL BUS HOST

(16-BIT ADDRESS)

SECTION

4.2 General Configuration Registers (0xx)

OFFSET/

ADDRESS

0000 MRID Master Reset and ID Register 5.1 0010 MC Master Configuration 5.2 0020 SM Master Status Register 5.3.2 0024 ISM Interrupt Mask Register for SM 5.3.2 0028 SDMA Status Register for DMA 5.3.2

002C ISDMA Interrupt Mask Register for SDMA 5.3.2

0030 SV54 Status Register for V.54 Loopback Detector 5.3.2 0034 ISV54 Interrupt Mask Register for SV.54 5.3.2 0040 LBBMC Local Bus Bridge Mode Control Register 11.2 0050 TEST Test Register 5.4

NAME REGISTER SECTION

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4.3 Receive Port Registers (1xx)

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OFFSET/

ADDRESS

NAME REGISTER SECTION

0100 RP0CR Receive Port 0 Control Register 6.2 0104 RP1CR Receive Port 1 Control Register 6.2 0108 RP2CR Receive Port 2 Control Register 6.2 010C RP3CR Receive Port 3 Control Register 6.2 0110 RP4CR Receive Port 4 Control Register 6.2 0114 RP5CR Receive Port 5 Control Register 6.2 0118 RP6CR Receive Port 6 Control Register 6.2 011C RP7CR Receive Port 7 Control Register 6.2 0120 RP8CR Receive Port 8 Control Register 6.2 0124 RP9CR Receive Port 9 Control Register 6.2 0128 RP10CR Receive Port 10 Control Register 6.2 012C RP11CR Receive Port 11 Control Register 6.2 0130 RP12CR Receive Port 12 Control Register 6.2 0134 RP13CR Receive Port 13 Control Register 6.2 0138 RP14CR Receive Port 14 Control Register 6.2 013C RP15CR Receive Port 15 Control Register 6.2

4.4 Transmit Port Registers (2xx)

OFFSET/

ADDRESS

0200 TP0CR Transmit Port 0 Control Register 6.2 0204 TP1CR Transmit Port 1 Control Register 6.2 0208 TP2CR Transmit Port 2 Control Register 6.2

020C TP3CR Transmit Port 3 Control Register 6.2

0210 TP4CR Transmit Port 4 Control Register 6.2 0214 TP5CR Transmit Port 5 Control Register 6.2 0218 TP6CR Transmit Port 6 Control Register 6.2

021C TP7CR Transmit Port 7 Control Register 6.2

0220 TP8CR Transmit Port 8 Control Register 6.2 0224 TP9CR Transmit Port 9 Control Register 6.2 0228 TP10CR Transmit Port 10 Control Register 6.2

022C TP11CR Transmit Port 11 Control Register 6.2

0230 TP12CR Transmit Port 12 Control Register 6.2 0234 TP13CR Transmit Port 13 Control Register 6.2 0238 TP14CR Transmit Port 14 Control Register 6.2

023C TP15CR Transmit Port 15 Control Register 6.2

NAME REGISTER SECTION

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4.5 Channelized Port Registers (3xx)

OFFSET/

ADDRESS

0300 CP0RDIS Channelized Port 0 Register Data Indirect Select 6.3 0304 CP0RD Channelized Port 0 Register Data 6.3 0308 CP1RDIS Channelized Port 1 Register Data Indirect Select 6.3 030C CP1RD Channelized Port 1 Register Data 6.3 0310 CP2RDIS Channelized Port 2 Register Data Indirect Select 6.3 0314 CP2RD Channelized Port 2 Register Data 6.3 0318 CP3RDIS Channelized Port 3 Register Data Indirect Select 6.3 031C CP3RD Channelized Port 3 Register Data 6.3 0320 CP4RDIS Channelized Port 4 Register Data Indirect Select 6.3 0324 CP4RD Channelized Port 4 Register Data 6.3 0328 CP5RDIS Channelized Port 5 Register Data Indirect Select 6.3 032C CP5RD Channelized Port 5 Register Data 6.3 0330 CP6RDIS Channelized Port 6 Register Data Indirect Select 6.3 0334 CP6RD Channelized Port 6 Register Data 6.3 0338 CP7RDIS Channelized Port 7 Register Data Indirect Select 6.3 033C CP7RD Channelized Port 7 Register Data 6.3 0340 CP8RDIS Channelized Port 8 Register Data Indirect Select 6.3 0344 CP8RD Channelized Port 8 Register Data 6.3 0348 CP9RDIS Channelized Port 9 Register Data Indirect Select 6.3 034C CP9RD Channelized Port 9 Register Data. 6.3 0350 CP10RDIS Channelized Port 10 Register Data Indirect Select. 6.3 0354 CP10RD Channelized Port 10 Register Data. 6.3 0358 CP11RDIS Channelized Port 11 Register Data Indirect Select. 6.3 035C CP11RD Channelized Port 11 Register Data 6.3 0360 CP12RDIS Channelized Port 12 Register Data Indirect Select 6.3 0364 CP12RD Channelized Port 12 Register Data 6.3 0368 CP13RDIS Channelized Port 13 Register Data Indirect Select 6.3 036C CP13RD Channelized Port 13 Register Data 6.3 0370 CP14RDIS Channelized Port 14 Register Data Indirect Select 6.3 0374 CP14RD Channelized Port 14 Register Data 6.3 0378 CP15RDIS Channelized Port 15 Register Data Indirect Select 6.3 037C CP15RD Channelized Port 15 Register Data 6.3

NAME REGISTER SECTION

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4.6 HDLC Registers (4xx)

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OFFSET/

ADDRESS

0400 RHCDIS Receive HDLC Channel Definition Indirect Select 7.2 0404 RHCD Receive HDLC Channel Definition 7.2 0410 RHPL Receive HDLC maximum Packet Length. One per device. 7.2 0480 THCDIS Transmit HDLC Channel Definition Indirect Select 7.2 0484 THCD Transmit HDLC Channel Definition 7.2

NAME REGISTER SECTION

4.7 BERT Registers (5xx)

OFFSET/

ADDRESS

0500 BERTC0 BERT Control 0 6.6 0504 BERTC1 BERT Control 1 6.6 0508 BERTRP0 BERT Repetitive Pattern Set 0 (lower word) 6.6

050C BERTRP1 BERT Repetitive Pattern Set 1 (upper word) 6.6

0510 BERTBC0 BERT Bit Counter 0 (lower word) 6.6 0514 BERTBC1 BERT Bit Counter 1 (upper word) 6.6 0518 BERTEC0 BERT Error Counter 0 (lower word) 6.6

051C BERTEC1 BERT Error Counter 1 (upper word) 6.6

NAME REGISTER SECTION

4.8 Receive DMA Registers (7xx)

OFFSET/

ADDRESS

NAME REGISTER SECTION

0700 RFQBA0 Receive Free-Queue Base Address 0 (lower word) 9.2.3 0704 RFQBA1 Receive Free-Queue Base Address 1 (upper word) 9.2.3 0708 RFQEA Receive Free-Queue End Address 9.2.3

070C RFQSBSA Receive Free-Queue Small Buffer Start Address 9.2.3

0710 RFQLBWP Receive Free-Queue Large Buffer Host Write Pointer 9.2.3 0714 RFQSBWP Receive Free-Queue Small Buffer Host Write Pointer 9.2.3 0718 RFQLBRP Receive Free-Queue Large Buffer DMA Read Pointer 9.2.3

071C RFQSBRP Receive Free-Queue Small Buffer DMA Read Pointer 9.2.3

0730 RDQBA0 Receive Done-Queue Base Address 0 (lower word) 9.2.4 0734 RDQBA1 Receive Done-Queue Base Address 1 (upper word) 9.2.4 0738 RDQEA Receive Done-Queue End Address 9.2.4

073C RDQRP Receive Done-Queue Host Read Pointer 9.2.4

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4.9 Transmit DMA Registers (8xx)

OFFSET/

ADDRESS

0800 TPQBA0 Transmit Pending-Queue Base Address 0 (lower word) 9.3.3 0804 TPQBA1 Transmit Pending-Queue Base Address 1 (upper word) 9.3.3 0808 TPQEA Transmit Pending-Queue End Address 9.3.3

080C TPQWP Transmit Pending-Queue Host Write Pointer 9.3.3

0810 TPQRP Transmit Pending-Queue DMA Read Pointer 9.3.3 0830 TDQBA0 Transmit Done-Queue Base Address 0 (lower word) 9.3.4 0834 TDQBA1 Transmit Done-Queue Base Address 1 (upper word) 9.3.4 0838 TDQEA Transmit Done-Queue End Address 9.3.4

083C TDQRP Transmit Done-Queue Host Read Pointer 9.3.4

0840 TDQWP Transmit Done-Queue DMA Write Pointer 9.3.4 0844 TDQFFT Transmit Done-Queue FIFO Flush Timer 9.3.4 0850 TDBA0 Transmit Descriptor Base Address 0 (lower word) 9.3.2 0854 TDBA1 Transmit Descriptor Base Address 1 (upper word) 9.3.2 0870 TDMACIS Transmit DMA Configuration Indirect Select 9.3.5 0874 TDMAC Transmit DMA Configuration 9.3.5 0880 TDMAQ Transmit DMA Queues Control 9.3.3/9.3.4

4.10 FIFO Registers (9xx)

OFFSET/

ADDRESS

0900 RFSBPIS Receive FIFO Starting Block Pointer Indirect Select 8.2 0904 RFSBP Receive FIFO Starting Block Pointer 8.2 0910 RFBPIS Receive FIFO Block Pointer Indirect Select 8.2 0914 RFBP Receive FIFO Block Pointer 8.2 0920 RFHWMIS Receive FIFO High-Watermark Indirect Select 8.2 0924 RFHWM Receive FIFO High Watermark 8.2 0980 TFSBPIS Transmit FIFO Starting Block Pointer Indirect Select 8.2 0984 TFSBP Transmit FIFO Starting Block Pointer 8.2 0990 TFBPIS Transmit FIFO Block Pointer Indirect Select 8.2

0994 TFBP Transmit FIFO Block Pointer 8.2 09A0 TFLWMIS Transmit FIFO Low-Watermark Indirect Select 8.2 09A4 TFLWM Transmit FIFO Low Watermark 8.2

NAME REGISTER SECTION

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4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx)

OFFSET/

ADDRESS

0x000/0A00 PVID0 PCI Vendor ID/Device ID 0 10.2 0x004/0A04 PCMD0 PCI Command Status 0 10.2 0x008/0A08 PRCC0 PCI Revision ID/Class Code 0 10.2

0x00C/0A0C PLTH0 PCI Cache Line Size/Latency Timer/Header Type 0 10.2

0x010/0A10 PDCM PCI Device Configuration Memory Base Address 10.2

0x03C/0A3C PINTL0 PCI Interrupt Line and Pin /Min Grant/Max Latency 0 10.2

NAME REGISTER SECTION

4.12 PCI Configuration Registers for Function 1 (PIDSEL/Bxx)

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OFFSET/

ADDRESS

NAME REGISTER SECTION

0x100/0B00 PVID1 PCI Vendor ID/Device ID 1 10.2 0x104/0B04 PCMD1 PCI Command Status 1 10.2 0x108/0B08 PRCC1 PCI Revision ID/Class Code 1 10.2

0x10C/0B0C PLTH1 PCI Cache Line Size/Latency Timer/Header Type 1 10.2

0x110/0B10 PLBM PCI Device Local Base Memory Base Address 10.2

0x13C/0B3C PINTL1 PCI Interrupt Line and Pin/Min Grant/Max Latency 1 10.2

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5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT

5.1 Master Reset and ID Register Description

The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all of the internal registers (except the PCI configuration registers) are placed into their default state, which is 0000h. The host must set the RST bit back to 0 before the device can be programmed for normal operation. The RST bit does not force the PCI outputs to three-state as does the hardware reset which is invoked by the PRST pin. A reset invoked by the PRST pin forces the RST bit to 0 as well as the rest of the internal configuration registers. See Section 2 for more details about device initialization.

The upper byte of the MRID register is read-only and it can be read by the host to determine the chip revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.

Bit # 7 6 5 4 3 2 1 0 Name n/a n/a

n/a n/a n/a n/a n/a RST

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name ID7 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

ID6 ID5 ID4 ID3 ID2 ID1 ID0

Bit 0/Master Software Reset (RST)

0 = normal operation 1 = force all internal registers (except LBBMC) to their default value of 0000h

Bits 8 to 15/Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the meaning of the ID bits.

5.2 Master Configuration Register Description

The master configuration (MC) register is used by the host to enable the receive and transmit DMAs as well as to control their PCI bus bursting attributes and select which port the BERT is dedicated to.

Bit # 7 6 5 4 3 2 1 0 Name BPS0 PBO TDT1 TDT0 TDE RDT1 DT0 RDE Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name TFPC1 TFPC0 RFPC1 RFPC0 BPS4 BPS3 BPS2 BPS1 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

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Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this bit. 0 = receive DMA is disabled 1 = receive DMA is enabled

Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1). These two bits select the maximum burst length that the receive DMA is allowed on the PCI bus. The DMA can be restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus efficiency. 00 = burst length maximum is 32 dwords 01 = burst length maximum is 64 dwords 10 = burst length maximum is 128 dwords 11 = burst length maximum is 256 dwords

Bit 3/Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to 0, the transmit DMA does not pass any data from the PCI bus to the transmit FIFO, even if one or more HDLC channels is enabled. On device initialization, the host should fully configure the transmit DMA before enabling it through this bit. 0 = transmit DMA is disabled 1 = transmit DMA is enabled

Bit 4/Transmit DMA Throttle Select Bit 0 (TDT0); Bit 5/Transmit DMA Throttle Select Bit 1 (TDT1). These These two bits select the maximum burst length the transmit DMA is allowed on the PCI bus. The DMA can be restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment for the PCI bus, the number of HDLC channels being used, and the trade off between channel latency and bus efficiency. 00 = burst length maximum is 32 dwords 01 = burst length maximum is 64 dwords 10 = burst length maximum is 128 dwords 11 = burst length maximum is 256 dwords

Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address while Big Endian places the least significant byte at the highest address. This bit setting only affects HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI configuration registers, and local bus are always in Little Endian format. 0 = HDLC packet data on the PCI bus is in Little Endian format 1 = HDLC packet data on the PCI bus is in Big Endian format

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Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated resources of the BERT.

00000 = Port 0 01000 = Port 8 10000 = Port 0 (high speed) 11000 = n/a 00001 = Port 1 01001 = Port 9 10001 = Port 1 (high speed) 11001 = n/a 00010 = Port 2 01010 = Port 10 10010 = Port 2 (high speed) 11010 = n/a 00011 = Port 3 01011 = Port 11 10011 = n/a 11011 = n/a 00100 = Port 4 01100 = Port 12 10100 = n/a 11100 = n/a 00101 = Port 5 01101 = Port 13 10101 = n/a 11101 = n/a 00110 = Port 6 01110 = Port 14 10110 = n/a 11110 = n/a 00111 = Port 7 01111 = Port 15 10111 = n/a 11111 = n/a

Bit 12/Receive FIFO Priority Control Bit 0 (RFPC0); Bit 13/Receive FIFO Priority Control Bit 1 (RFPC1).

These bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest priority to the DMA to transfer data from the FIFO to the PCI bus. In the priority decoded scheme, the lower the HDLC channel numbers, generally the higher the priority. In schemes ’10 and ’11, the upper priority decode channels have priority over the lower priority decode channels. 00 = all HDLC channels are serviced round robin 01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin 10 = HDLC channels 16 to 1 are priority decoded; HDLC channels 17-up are round robin 11 = HDLC channels 64 to 1 are priority decoded; HDLC channels 65-up are round robin

Bit 14/Transmit FIFO Priority Control Bit 0 (TFPC0); Bit 15/Transmit FIFO Priority Control Bit 1 (TFPC1). These two bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest

priority to the DMA to transfer data from the PCI bus to the FIFO. In the priority-decoded scheme, the lower the HDLC channel numbers, the higher the priority. 00 = all HDLC channels are serviced round robin 01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin 10 = HDLC channels 16 to 1 are priority decoded; other HDLC channels 17-up re round robin 11 = HDLC channels 64 to 1 are priority decoded; other HDLC channels 65-up are round robin

5.3 Status and Interrupt

5.3.1 General Description of Operation

There are three status registers in the device: status master (SM), status for the receive V.54 loopback detector (SV54), and status for DMA (SDMA). These registers report events in real-time by setting a bit within the register to 1. All bits that have been set within the register are cleared when the register is read, and the bit is not set again until the event has occurred again. Each bit can generate an interrupt at the PCI bus through the PINTA output signal pin, and, if the local bus is in the configuration mode, then an interrupt also be created at the LINT output signal pin. Each status register has an associated interrupt mask register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status registers remain active even if the associated interrupt is disabled.

SM Register

The status master (SM) register reports events that occur at the port interface, at the BERT receiver, at the PCI bus, and at the local bus. See Figure 5-1

The port interface reports change-of-frame alignment (COFA) events. If the software detects that one of these bits is set, the software must begin polling the RP[n]CR or TP[n]CR registers of each active port (a maximum of 16 reads) to determine which port or ports has incurred a COFA. Also, the host can allow/deny the COFA indications to be passed to the SRCOFA and STCOFA status bits through the

for details.

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interrupt enable for the receive COFA (IERC) and interrupt enable for the transmit COFA (IETC) control bits in the RP[n]CR and TP[n]CR registers, respectively.

The BERT receiver reports three events: a change in the receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. Each of these events can be masked within the BERT function through the BERT control register (BERTC0). If the software detects that the BERT has reported an event, the software must read the BERT status register (BERTEC0) to determine which event(s) has occurred.

The SM register also reports events as they occur in the PCI bus and the local bus. There are no control bits to stop these events from being reported in the SM register. When the local bus is operated in the PCI bridge mode, SM reports any interrupts detected through the local bus LINT input signal pin and if any timing errors occur because the external timing signal LRDY. When the local bus is operated in the configuration mode, the LBINT and LBE bits are meaningless and should be ignored.

SV54 Register

The status for receive V.54 detector (SV54) register reports if the V.54 loopback detector has either timed out in its search for the V.54 loop-up pattern or if the detector has found and verified the loopup/down pattern. There is a separate status bit (SLBP) for each port. When set, the host must read the VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the V.54 detector. When the V.54 detector experiences a time out in its search for the loop-up code (VTO = 1), then the SLBP status bit is continuously set until the V.54 detector is reset by the host, toggling the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in the SV54 register. See Figure 5-1 for details on the status bits and Section 6 for details on the operation of the V.54 loopback detector.

SDMA Register

The status DMA (SDMA) register reports events pertaining to the receive and transmit DMA blocks as well as the receive HDLC controller and FIFO. The SDMA reports when the DMA reads from either the receive free queue or transmit pending queue or writes to the receive or transmit done queues. Also reported are error conditions that might occur in the access of one of these queues. The SDMA reports if any of the HDLC channels experiences an FIFO overflow/underflow condition and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels. The host can determine which specific HDLC channel incurred an FIFO overflow/underflow, CRC error, octet length error, or abort by reading the status bits as reported in done queues, which are created by the DMA. There are no control bits to stop these events from being reported in the SDMA register.

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Figure 5-1. Status Register Block Diagram for SM and SV54

BERTEC0 Bit 1 (BECO) BERTEC0 Bit 2 (BBCO) BERTC0 Bit 13 (IEOF) Change in BERTEC0 Bit 0 (SYNC) BERTC0 Bit 15 (IESYNC) BERTEC0 Bit 3 (BED) BERTC0 Bit 14 (IEBED)

BERT

Transmit

Port I/F # 0

TCOFA

TP0CR Bit #14

Receive

Port I/F # 0

RCOFA

RP0CR Bit #14

DS31256

int_bd

SM: Status Master Register

LBINT LBE

SV54: Status for V54 Detector

SLBP15

SLBP14

SLBP13

#13

#14

#15

OR OR

n/an/a

PSERRPPERR

SBERT

ST COFA

#13

#14

#15

SR COFA

SLBP0SLBP1SLBP2SLBP3SLBP4SLBP5

Change in V.54 Detector (SLBP)

Port #15

Change in V.54 Detector (SLBP)

Port #14

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Change in V.54 Detector (SLBP)

Port #1

Change in V.54 Detector (SLBP)

Port #0

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5.3.2 Status and Interrupt Register Description

Bit # 7 6 5 4 3 2 1 0 Name n/a n/a Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name LBINT Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

LBE n/a n/a n/a n/a n/a n/a

Bit 0/Status Bit for Change-of-Frame Alignment (SRCOFA). This status bit is set to 1 if one or more of the receive ports has experienced a COFA event. The host must read the RCOFA bit in the receive port control registers (RP[n]CR) of each active port to determine which port or ports has seen the COFA. The SRCOFA bit is cleared when read and is not set again until the one or more receive ports has experienced another COFA. If enabled through the SRCOFA bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA). This status bit is set to 1 if one or more of the transmit ports has experienced a COFA event. The host must read the TCOFA bit in the transmit port control registers (TP[n]CR) of each active port to determine which port or ports has seen the COFA. The STCOFA bit is cleared when read and is not set again until one or more transmit ports has experienced another COFA. If enabled through the STCOFA bit in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 2/Status Bit for Change of State in BERT (SBERT). This status bit is set to 1 if there is a major change of state in the BERT receiver. A major change of state is defined as either a change in the receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. The host must read the status bits of the BERT in the BERT status register (BERTEC0) to determine the change of state. The SBERT bit is cleared when read and is not set again until the BERT has experienced another change of state. If enabled through the SBERT bit in the ISM, the setting of this bit causees a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 3/Status Bit for PCI System Error (PSERR). This status bit is a software version of the PCI bus hardware pin PSERR. It is set to 1 if the PCI bus detects an address parity error or other PCI bus error. The PSERR bit is cleared when read and is not set again until another PCI bus error has occurred. If enabled through the PSERR bit in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. This status bit is also reported in the control/status register in the PCI configuration registers (Section 10

Bit 4/Status Bit for PCI System Error (PPERR). This status bit is a software version of the PCI bus hardware pin PPERR. It is set to 1 if the PCI bus detects parity errors on the PAD and PCBE buses as experienced or reported by a target. The PPERR bit is cleared when read and is not set again until another parity error has been detected. If enabled through the PPERR bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. This status bit is also reported in the control/status register in the PCI configuration registers (Section 10

n/a PPERR PSERR SBERT STCOFA SRCOFA

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Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI bridge mode. It is set to 1 when the local bus LRDY signal is not detected within nine LCLK periods. This indicates to the host that an aborted local bus access has occurred. If enabled through the LBE bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. The LBE bit is meaningless when the local bus is operated in the configuration mode and should be ignored.

Bit 15/Status Bit for Local Bus Interrupt (LBINT). This status bit is set to 1 if the local bus LINT signal has been detected as asserted. This status bit is only valid when the local bus is operated in PCI bridge mode. The LBINT bit is cleared when read and is not set again until the LINT signal pin once again has been detected as asserted. If enabled through the LBINT bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin. The LBINT bit is meaningless when the local bus is operated in the configuration mode and should be ignored.

Bit # 7 6 5 4 3 2 1 0 Name n/a n/a

n/a PPERR PSERR SBERT STCOFA SRCOFA

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name LBINT LBE n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a

Bit 0/Status Bit for Receive Change-of-Frame Alignment (SRCOFA) 0 = interrupt masked 1 = interrupt unmasked

Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA) 0 = interrupt masked 1 = interrupt unmasked

Bit 2/Status Bit for Change of State in BERT (SBERT)

0 = interrupt masked 1 = interrupt unmasked

Bit 3/Status Bit for PCI System Error (PSERR)

0 = interrupt masked 1 = interrupt unmasked

Bit 4/Status Bit for PCI System Error (PPERR)

0 = interrupt masked 1 = interrupt unmasked

Bit 14/Status Bit for Local Bus Error (LBE) 0 = interrupt masked 1 = interrupt unmasked

Bit 15/Status Bit for Local Bus Interrupt (LBINT) 0 = interrupt masked 1 = interrupt unmasked

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Bit # 7 6 5 4 3 2 1 0 Name SLBP7

SLBP6 SLBP5 SLBP4 SLBP3 SLBP2 SLBP1 SLBP0

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name SLBP15

SLBP14 SLBP13 SLBP12 SLBP11 SLBP10 SLBP9 SLBP8

Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 15/Status Bits for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15). These status bits are set to 1 when the V.54 loopback detector within the port has either timed out in its search for the loop-up pattern or it has detected and validated the loop-up or loop-down pattern. There is one status bit per port. The host must read the VTO and VLB status bits in RP[n]CR register of the corresponding port to determine the exact status of the V.54 detector. If the V.54 detector has timed out in its search for the loop-up code (VTO = 1), then SLBP is continuously set until the host resets the V.54 detector by toggling the VRST bit in RP[n]CR. If enabled through the SLBP[n] bit in the interrupt mask for SV54 (ISV54), the setting of these bits causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. See Section 6 for specific details about the operation of the V.54 loopback detector.

Bit # 7 6 5 4 3 2 1 0 Name SLBP7 SLBP6 SLBP5 SLBP4 SLBP3 SLBP2 SLBP1 SLBP0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name SLBP15 SLBP14 SLBP13 SLBP12 SLBP11 SLBP10 SLBP9 SLBP8 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 15/Status Bit for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15)

0 = interrupt masked 1 = interrupt unmasked

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Bit # 7 6 5 4 3 2 1 0 Name RLBRE

RLBR ROVFL RLENC RABRT RCRCE n/a n/a

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name TDQWE TDQW TPQR TUDFL RDQWE RDQW RSBRE RSBR Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE). This status bit is set to 1 if any of the receive HDLC channels experiences a CRC checksum error. The RCRCE bit is cleared when read and is not set again until another CRC checksum error has occurred. If enabled through the RCRCE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 4/Status Bit for Receive HDLC Length Check (RLENC). This status bit is set to 1 if any of the HDLC channels:

· exceeds the octet length count (if so enabled to check for octet length)

· receives an HDLC packet that does not meet the minimum length criteria

· experiences a nonintegral number of octets in between opening and closing flags

The RLENC bit is cleared when read and is not set again until another length violation has occurred. If enabled through the RLENC bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 5/Status Bit for Receive FIFO Overflow (ROVFL). This status bit is set to 1 if any of the HDLC channels experiences an overflow in the receive FIFO. The ROVFL bit is cleared when read and is not set again until another overflow has occurred. If enabled through the ROVFL bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the large buffer free queue. The RLBR bit is cleared when read and is not be set again, until another read of the large buffer free queue has occurred. If enabled through the RLBR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt

at the PCI bus

through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit is set to 1 each time the receive DMA tries to read the large buffer free queue and it is empty. The RLBRE bit is cleared when read and is not set again, until another read of the large buffer free queue detects that it is empty. If enabled through the RLBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

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Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is cleared when read and is not set again, until another read of the small buffer free queue has occurred. If enabled through the RSBR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit is set to 1 each time the receive DMA tries to read the small buffer free queue and it is empty. The RSBRE bit is cleared when read and is not set again, until another read of the small buffer free queue detects that it is empty. If enabled through the RSBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW). This status bit is set to 1 when the receive DMA writes to the done queue. Based of the setting of the receive done-queue threshold setting (RDQT0 to RDQT2) bits in the receive DMA queues-control (RDMAQ) register, this bit is set either after each write or after a programmable number of writes from 2 to 128 (Section 9.2.4

). The RDQW bit is cleared when read and is not set

again until another write to the done queue has occurred. If enabled through the RDQW bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE). This status bit is set to 1 each time the receive DMA tries to write to the done queue and it is full. The RDQWE bit is cleared when read and is not set again until another write to the done queue detects that it is full. If enabled through the RDQWE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL). This status bit is set to 1 if any of the HDLC channels experiences an underflow in the transmit FIFO. The TUDFL bit is cleared when read and is not set again until another underflow has occurred. If enabled through the TUDFL bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR). This status bit is set to 1 each time the transmit DMA reads the pending queue. The TPQR bit is cleared when read and is not set again until another read of the pending queue has occurred. If enabled through the TPQR bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW). This status bit is set to 1 when the transmit DMA writes to the done queue. Based on the setting of the transmit done-queue threshold setting (TDQT0 to TDQT2) bits in the transmit DMA queues-control (TDMAQ) register, this bit is set either after each write or after a programmable number of writes from 2 to 128 (Section 9.2.4

). The TDQW bit is cleared when read and is not set

again until another write to the done queue has occurred. If enabled through the TDQW bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE). This status bit is set to 1 each time the transmit DMA tries to write to the done queue and it is full. The TDQWE bit is cleared when read and is not set again until another write to the done queue detects that it is full. If enabled through the TDQWE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.

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Bit # 7 6 5 4 3 2 1 0 Name RLBRE RLBR ROVFL RLENC RABRT RCRCE n/a n/a Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name TDQWE TDQW TPQR TUDFL RDQWE RDQW RSBRE RSBR Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE) 0 = interrupt masked 1 = interrupt unmasked

Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT) 0 = interrupt masked 1 = interrupt unmasked

Bit 4/Status Bit for Receive HDLC Length Check (RLENC) 0 = interrupt masked 1 = interrupt unmasked

Bit 5/Status Bit for Receive FIFO Overflow (ROVFL) 0 = interrupt masked 1 = interrupt unmasked

Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR) 0 = interrupt masked 1 = interrupt unmasked

Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE) 0 = interrupt masked 1 = interrupt unmasked

Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR) 0 = interrupt masked 1 = interrupt unmasked

Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE) 0 = interrupt masked 1 = interrupt unmasked

Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW) 0 = interrupt masked 1 = interrupt unmasked

Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE)

0 = interrupt masked

1 = interrupt unmasked

Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL) 0 = interrupt masked 1 = interrupt unmasked

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Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR) 0 = interrupt masked 1 = interrupt unmasked

Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW) 0 = interrupt masked 1 = interrupt unmasked

Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE) 0 = interrupt masked 1 = interrupt unmasked

5.4 Test Register Description

Bit # 7 6 5 4 3 2 1 0 Name n/a n/a Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a n/a n/a

Bit 0/Factory Test (FT). This bit is used by the factory to place the DS31256 into the test mode. For normal device operation, this bit should be set to 0 whenever this register is written to. Setting this bit places the RAMs into a low-power standby mode.

Bit 1 to 15/Device Internal Test Bits. Bits 1 to 15 are for internal (Dallas Semiconductor) test use only, not user test-mode controls. Values of these bits should always be 0. If any of these bits are set to 1 the device does not function properly.

n/a n/a n/a n/a n/a FT

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6. LAYER 1

6.1 General Description

Figure 6-1 shows the Layer 1 block. Each of the DS31256’s 16 Layer 1 ports can be configured to

support either a channelized application or an unchannelized application. Users can mix the applications on the ports as needed. Some or all of the ports can be channelized, while the others can be configured as unchannelized. A channelized application is defined as one that requires an 8kHz synchronization pulse to subdivide the serial data stream into a set of 8-bit DS0 channels (also called time slots), which are time division multiplexed (TDM) one after another. Ports running a channelized application require an 8kHz pulse at the RS and TS signals. An unchannelized application is defined as a synchronous clock and data interface. No synchronization pulse is required and the RS and TS signals are forced low in this application. Section 15 contains examples of some various configurations.

In channelized applications, the Layer 1 ports can be configured to operate in one of four modes, as shown in Table 6-A. Each port is capable of handling one, two, or four T1/E1 data streams. When more than one T1/E1 data stream is applied to the port, the individual T1/E1 data streams must be TDM into a single data stream at either a 4.096MHz or 8.192MHz data rate. Since the DS31256 can map any HDLC channel to any DS0 channel, it can support any form (byte interleaved, frame interleaved, etc.) of TDM that the application may require. On a DS0-by-DS0 basis, the DS31256 can be configured to process all 8 bits (64kbps), the seven most significant bits (56kbps), or no data.

Table 6-A. Channelized Port Modes

MODE FUNCTION

T1 (1.544MHz) N x 64kbps or N x 56kbps; where N = 1 to 24 (one T1 data stream) E1 (2.048MHz) N x 64kbps or N x 56kbps; where N = 1 to 32 (one T1 or E1 data stream)

4.096MHz N x 64kbps or N x 56kbps; where N = 1 to 64 (two T1 or E1 data streams)

8.192MHz N x 64kbps or N x 56kbps; where N = 1 to 128 (four T1 or E1 data streams)

Each port in the Layer 1 block is connected to a slow HDLC engine. The slow HDLC engine can handle channelized applications at speeds up to 8.192Mbps and unchannelized applications at speeds of up to 10Mbps. Ports 0 and 1 have the added capability of fast HDLC engines that can only handle unchannelized applications but at speeds of up to 52MHz.

Each port has an associated receive port control register (RP[n]CR, where n = 0 to 15) and a transmit port control register (TP[n]CR where n = 0 to 15). These control registers are defined in detail in Section 6.2. They control all the circuitry in the Layer 1 block with the exception of the Layer 1 state machine, which is shown in the center of the block diagram (Figure 6-1).

Each port contains a Layer 1 state machine that connects directly to the slow HDLC engine. It prepares the raw incoming data for the slow HDLC engine and grooms the outgoing data. The Layer 1 state machine performs a number of tasks that include the following:

§ Assigning the HDLC channel number to the incoming and outgoing data

§ Channelized local and network loopbacks

§ Channelized selection of 64kbps, 56kbps, or no data

§ Channelized transmits DS0 channel fill of all ones

§ Routing data to and from the BERT function

§ Routing data to the V.54 loop pattern detector

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The DS31256 has a set of three registers per DS0 channel for each port that determine how each DS0 channel is configured. These three registers are defined in Section 6.3. If the fast (52Mbps) HDLC engine is enabled on port 0, then HDLC channel 1 is assigned to it. Likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 1 if it is enabled, and HDLC channel 2 is assigned to the fast HDLC engine on port 2 if it is enabled.

The Layer 1 block also contains a V.54 detector. Each of the 16 ports contains a V.54 loop pattern detector on the receive side. The device can search for the V.54 loop-up and loop-down patterns in both channelized and unchannelized applications at speeds up to 10MHz. In channelized applications, the device can be configured to search for the patterns in any combination of DS0 channels. Section 6.4 describes all of the details on the V.54 detector.

The DS31256 contains an on-board full-featured BERT capable of generating and detecting both pseudorandom and repeating serial bit patterns. The BERT function is a shared resource among the 16 ports on the DS31256 and can only be assigned to one port at a time. It can be used in both channelized and unchannelized applications and at speeds up to 52MHz. In channelized applications, data can be routed to and from any combination of DS0 channels that are being used on the port. The details on the BERT function are covered in Section 6.5.

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Figure 6-1. Layer 1 Block Diagram

RC RS RD

TC TS

1 of 16

Local LoopBack (LLB)

LLB UNLB

Force All Ones

Port 0 & 1 Only

Invert Clock / Data / Sync

BERT/ Fast HDLC Mux

OverSample with PCLK

BERT Mux

(see Figure 5.5A)

UnChannelized Network Loopback (UNLB)

V.54 Detector

PORT RAM (see Sec.

5.3)

Layer One State Machine

Receive

Channelized Local LoopBack (CLLB)

Transmit

Channelized Network LoopBack (CNLB)

SLOW HDLC

(One per Port)

Ports 0 & 1 Only

FAST HDLC

l1_bd

DS31256

To /

From

FIFO

Block

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Figure 6-2. Port Timing (Channelized and Unchannelized Applications)

RC[n] / TC[n] Normal Mode

RC[n] / TC[n] Inverted Mode

RD[n] TD[n]

RS[n] / TS[n] 0 Clock Early & Not Inverted

RS[n] / TS[n] 1/2 Clock Early & Inverted

RS[n] / TS[n] 1 Clock Early & Not Inverted

RS[n] / TS[n] 2 Clocks Early & Not Inverted

Bit 191 or 254 or 510 or 1022

Bit 192 or 255 or 511 or 1023

Last Bit of the Frame

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Bit 0

First Bit of the Frame

Bit 1

tdm_tim

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6.2 Port Register Descriptions

Receive Side Control Bits (one each for all 16 ports)

Register Name: RP[n]CR, where n = 0 to 15 for each port Register Description: Receive Port [n] Control Register Register Address: See the Register Map in Section 4.

Bit # 7 6 5 4 3 2 1 0 Name RSS1 RSS0 RSD1 RSD0 VRST RISE RIDE RICE Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name RCOFA IERC VLB VTO n/a LLB RUEN RP[i]HS Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Invert Receive Clock Enable (RICE)

0 = do not invert clock (normal mode) 1 = invert clock (inverted clock mode)

Bit 1/Invert Receive Data Enable (RIDE)

0 = do not invert data (normal mode) 1 = invert data (inverted data mode)

Bit 2/Invert Sync Enable (RISE) 0 = do not invert sync pulse (normal mode) 1 = invert sync pulse (inverted sync pulse mode)

Bit 3/V.54 Detector Reset (VRST). Toggling this bit from 0 to 1 and then back to 0 causes the internal V.54 detector to be reset and begin searching for the V.54 loop-up pattern. See Section 6.4

Bit 4/Sync Delay Bit 0 (RSD0); Bit 5/Sync Delay Bit 1 (RSD1). These two bits define the format of the sync signal that is applied to the RS[n] input. These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1). 00 = sync pulse is 0 clocks early 01 = sync pulse is 1/2 clock early 10 = sync pulse is 1 clock early 11 = sync pulse is 2 clocks early

Bit 6/Sync Select Bit 0 (RSS0); Bit 7/Sync Select Bit 1 (RSS1). These two bits select the mode in which each port is to be operated. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate. These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1). 00 = T1 Mode (24 DS0 channels and 193 RC clocks between RS sync signals) 01 = E1 Mode (32 DS0 channels and 256 RC clocks between RS sync signals) 10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between RS sync signals) 11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between RS sync signals)

for more details.

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Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port 0 (1, or 2) Layer 1 state machine logic is defeated, and RC0 (1, 2) and RD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only present in RP0CR, RP1CR and RP2CR. Bit 8 is not assigned in ports 3 through 15. 0 = disabled 1 = enabled

Bit 9/Unchannelized Enable (RUEN). When enabled, this bit forces the port to operate in an unchannelized fashion. When disabled, the port operates in a channelized mode. 0 = channelized mode 1 = unchannelized mode

Bit 10/Local Loopback Enable (LLB). This loopback routes transmit data back to the receive port. It can be used in both channelized and unchannelized port operating modes, even on ports 0, 1, and 2 operating at speeds up to 52MHz (Figure 6-1 local loopback (CLLB) function. See Section 6.3

). In channelized applications, a per-channel loopback can be realized by using the channelized

for details on CLLB. 0 = loopback disabled 1 = loopback enabled

Bit 12/V.54 Time Out (VTO). This read-only bit reports the real-time status of the V.54 detector. It is set to 1 when the V.54 detector has finished searching for the V.54 loop-up pattern and has not detected it. This indicates to the host that the V.54 detector can now be used to search for the V.54 loop-up pattern on other HDLC channels, and the host can initiate this by configuring the RV54 bits in the RP[n]CR register and then toggling the VRST control bit. See Section 6.4

for more details about how the V.54 detector operates.

Bit 13/V.54 Loopback (VLB). This read-only bit reports the real-time status of the V.54 detector. It is set to 1 when the V.54 detector has verified that a V.54 loop-up pattern has been seen. When set, it remains set until either the V.54 loop-down pattern is seen or the V.54 detector is reset by the host (i.e., by toggling VRST). See Section 6.4

for more details on how the V.54 detector operates.

Bit 14/Interrupt Enable for RCOFA (IERC)

0 = interrupt masked 1 = interrupt enabled

Bit 15/COFA Status Bit (RCOFA). This latched read-only status bit sets if a COFA is detected. The COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024-bit frame. This bit resets when read and does not set again until another COFA has occurred.

Transmit Side Control Bits (one each for all 16 ports)

Register Name: TP[n]CR, where n = 0 to 15 for each port Register Description: Transmit Port [n] Control Register Register Address: See the Register Map in Section 4

Bit # 7 6 5 4 3 2 1 0 Name

TSS1 TSS0 TSD1 TSD0

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name TCOFA IETC n/a n/a TUBS UNLB TUEN TP[i]HS Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

TFDA1

TISE TIDE TICE

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Bit 0/Invert Clock Enable (TICE)

0 = do not invert clock (normal mode) 1 = invert clock (inverted mode)

Bit 1/Invert Data Enable (TIDE) 0 = do not invert data (normal mode) 1 = invert data (inverted mode)

Bit 2/Invert Sync Enable (TISE) 0 = do not invert sync (normal mode) 1 = invert sync pulse (inverted mode)

Bit 3/Force Data All Ones (TFDA1) 0 = force all data at TD to be 1 1 = allow data to be transmitted normally

Bit 4/Sync Delay Bit 0 (TSD0); Bit 5/Sync Delay Bit 1 (TSD1). These bits define the format of the sync signal that is applied to the TS[n] input. These bits are ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1). 00 = sync pulse is 0 clocks early 01 = sync pulse is 1/2 clock early 10 = sync pulse is 1 clock early 11 = sync pulse is 2 clocks early

Bit 6/Sync Select Bit 0 (TSS0); Bit 7/Sync Select Bit 1 (TSS1). These bits select the mode in which each port operates. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate. These bits are ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1). 00 = T1 Mode (24 DS0 channels and 193 RC clocks between TS sync signals) 01 = E1 Mode (32 DS0 channels and 256 RC clocks between TS sync signals) 10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between TS sync signals) 11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between TS sync signals)

Bit 8/Port 0 High-Speed Mode (TP0 (1, 2) HS). If enabled, the port 0 (1 or 2) Layer 1 state machine logic is defeated and TC0 (1, 2) and TD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only present in TP0CR, TP1CR, and TP2CR. Bit 8 is not assigned in ports 3 through 15. 0 = disabled 1 = enabled

Bit 9/Unchannelized Enable (TUEN). When enabled, this bit forces the port to operate in an unchannelized fashion. When disabled, the port operates in a channelized mode. This bit overrides the transmit channel enable (TCHEN) bit in the transmit layer 1 configuration (T[n]CFG[j]) registers, which are described in Section 6.3

. 0 = channelized mode 1 = unchannelized mode

Bit 10/Unchannelized Network Loopback Enable (UNLB). See Figure 6-1

for details. This loopback cannot be used for ports 0 and 1 when they are operating at speeds greater than 10MHz. 0 = loopback disabled 1 = loopback enabled

Bit 11/Unchannelized BERT Select (TUBS). This bit is ignored if TUEN = 0. This bit overrides the transmit BERT (TBERT) bit in the transmit layer 1 configuration (T[n]CFG[j]) registers, which are described in Section 6.3

. 0 = source transmit data from the HDLC controller 1 = source transmit data from the BERT block

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Bit 14/Interrupt Enable for TCOFA (IETC)

0 = interrupt masked 1 = interrupt enabled

Bit 15/COFA Status Bit (TCOFA). This latched read-only status bit is set if a COFA is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024-bit frame. This bit is reset when read and is not set again until another COFA has occurred.

6.3 Layer 1 Configuration Register Description

There are three configuration registers for each DS0 channel on each port (Figure 6-3). As shown in

Figure 6-1, each of the 16 ports contains a PORT RAM, which controls the Layer 1 state machine. These

384 registers (three registers x 128 DS0 channels per port) comprise the PORT RAM for each port, controlling and providing access to the Layer 1 state machine. The registers are accessed indirectly through the channelized port register data (CP[n]RD) register. The host must first write to the channelized port register data-indirect select (CP[n]RDIS) register to choose which DS0 channel and channelized PORT RAM it wishes to configure or read. On power-up, the host must write to all the used R[n]CFG[j] and T[n]CFG[j] locations to make sure they are set into a known state.

Figure 6-3. Layer 1 Register Set

C[n]DAT[j]: Channelized DS0 Data LSB

RDATA(8): Receive DS0 Data

MSB

TDATA(8): Transmit DS0 Data

R[n]CFG[j]: Receive Configuration LSB

RCH#(8): Receive HDLC Channel Number

MSB

RCHEN RBERT n/a RV54 n/a CLLB n/a R56

T[n]CFG[j]: Transmit Configuration LSB

TCH#(8): Transmit HDLC Channel Number

MSB

TCHEN TBERT n/a n/a CNLB n/a TFAO T56

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Register Name: CP[n]RDIS, where n = 0 to 15 for each port Register Description: Channelized Port [n] Register Data Indirect Select Register Address: See the Register Map in Section 4

Bit # 7 6 5 4 3 2 1 0 Name n/a CHID6 CHID5 CHID4 CHID3 CHID2 CHID1 CHID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB IARW n/a n/a n/a n/a CPRS1 CPRS0 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 6/DS0 Channel ID (CHID0 to CHID6). The number of DS0 channels used depends on whether the port has been configured for an unchannelized application or for a channelized application. If set for a channelized application, the number of DS0 channels depends on whether the port has been configured in the T1, E1,

4.096MHz, or 8.192MHz mode. 0000000 (00h) = DS0 channel number 0 1111111 (7Fh) = DS0 channel number 127

PORT MODE

DS0 CHANNELS

AVAILABLE

Unchannelized (RUEN/TUEN = 1) 0

Channelized T1 (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 0) 0 to 23

Channelized E1 (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 0) 0 to 31

Channelized 4.096MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 1) 0 to 63

Channelized 8.192MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 1) 0 to 127

Bit 8/Channelized PORT RAM Select Bit 0 (CPRS0); Bit 9/Channelized PORT RAM Select Bit 1 (CPRS1)

00 = channelized DS0 data (C[n]DAT[j]) 01 = receive configuration (R[n]CFG[j]) 10 = transmit configuration (T[n]CFG[j]) 11 = illegal selection

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal channelized PORT RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining data from the DS0 channel location indicated by the CHID bits and the data from the PORT RAM indicated by the CPRS0 and CPRS1 bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the CP[n]RD register, the IAB bit is set to 0. When the host wishes to write data to the internal channelized PORT RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the CP[n]RD register and write it to the PORT RAM and the DS0 channel. When the device has completed the write, the IAB is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed.

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Register Name: CP[n]RD, where n = 0 to 15 for each port Register Description: Channelized Port [n] Register Data Register Address: See the Register Map in Section 4

Bit # 7 6 5 4 3 2 1 0 Name CHD7 CHD6 CHD5 CHD4 CHD3 CHD2 CHD1 CHD0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name CHD15 CHD14 CHD13 CHD12 CHD11 CHD10 CHD9 CHD8 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 15/DS0 Channel Data (CHD0 to CHD15). This is the 16-bit data that is to either be written into or read from the PORT RAM, specified by the CP[n]RDIS register.

Figure 6-4. Port RAM Indirect Access

CP[n]RDIS

CP[n]RD

Port RAM (one each for all 16 ports; n = 0 to 15)

C[n]DAT0 R[n]CFG0 T[n]CFG0 C[n]DAT1 R[n]CFG1 T[n]CFG1 C[n]DAT2 R[n]CFG2 T[n]CFG2 C[n]DAT3 R[n]CFG3 T[n]CFG3 C[n]DAT4 R[n]CFG4 T[n]CFG4

... ... ...

C[n]DAT126 R[n]CFG126 T[n]CFG126 C[n]DAT127 R[n]CFG127 T[n]CFG127

Register Name: C[n]DAT[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Register Description: Channelized Layer 1 DS0 Data Register Register Address: Indirect Access through CP[n]RD

Bit # 7 6 5 4 3 2 1 0 Name RDATA(8): Receive DS0 Data Default

Bit # 15 14 13 12 11 10 9 8 Name TDATA(8): Transmit DS0 Data Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Note: In normal device operation, the host must never write to the C[n]DAT[j] registers.

Bits 0 to 7/Receive DS0 Data (RDATA). This register holds the most current DS0 byte received. It is used by the

transmit side Layer 1 state machine when channelized network loopback (CNLB) is enabled.

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Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted. It is used by the receive side Layer 1 state machine when channelized local loopback (CLLB) is enabled.

Register Name: R[n]CFG[j] where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Register Description: Receive Layer 1 Configuration Register Register Address: Indirect Access through CP[n]RD

Bit # 7 6 5 4 3 2 1 0 Name RCH#(8): Receive HDLC Channel Number Default

Bit # 15 14 13 12 11 10 9 8 Name RCHEN RBERT n/a RV54 n/a CLLB n/a R56 Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/Receive Channel Number (RCH#). The CPU loads the number of the HDLC channels associated with this particular DS0 channel. If the port is running in an unchannelized mode (RUEN = 1), the HDLC channel number only needs to be loaded into R[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled. 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256

Bit 8/Receive 56kbps (R56). If the port is running a channelized application, this bit determines whether the LSB of each DS0 should be processed or not. If this bit is set, the LSB of each DS0 channel is not routed to the HDLC controller (or the BERT, if it has been enabled through the RBERT bit). This bit does not affect the operation of the V.54 detector. It always searches on all 8 bits in the DS0. 0 = 64kbps (use all 8 bits in the DS0) 1 = 56kbps (use only the first 7 bits received in the DS0)

Bit 10/Channelized Local Loopback Enable (CLLB). Enabling this loopback forces the transmit data to replace the receive data. This bit must be set for each and every DS0 channel that is to be looped back. In order for the loopback to become active, the DS0 channel must be enabled (RCHEN = 1) and the DS0 channel must be set into the 64kbps mode (R56 = 0). 0 = loopback disabled 1 = loopback enabled

Bit 12/Receive V.54 Enable (RV54E). If this bit is cleared, this DS0 channel is not examined to check if the V.54 loop pattern is present. If set, the DS0 is examined for the V.54 loop pattern. When searching for the V.54 pattern within a DS0 channel, all 8 bits of the DS0 channel are examined, regardless of how the DS0 channel is configured (i.e., 64k or 56k). 0 = do not examine this DS0 channel for the V.54 loop pattern 1 = examine this DS0 channel for the V.54 loop pattern

Bit 14/Route Data Into BERT (RBERT). Setting this bit routes the DS0 data into the BERT function. If the DS0 channel has been configured for 56kbps operation (R56 = 1), the LSB of each DS0 channel is not routed to the BERT block. In order for the data to make it to the BERT block, the host must also configure the BERT for the proper port through the master control register (Section 5

). 0 = do not route data to BERT 1 = route data to BERT

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Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0 channel is active, the loopback function (CLLB = 1) overrides this activation and routes transmit data back to the HDLC controller instead of the data coming in through the RD pin. In an unchannelized mode (RUEN = 1), only the RCHEN bit in R[n]CFG0 needs to be configured. 0 = deactivated DS0 channel 1 = active DS0 channel

Register Name: T[n]CFG[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0 Register Description: Transmit Layer 1 Configuration Register Register Address: Indirect Access through CP[n]RD

Bit # 7 6 5 4 3 2 1 0 Name TCH#(8): Transmit HDLC Channel Number Default

Bit # 15 14 13 12 11 10 9 8 Name TCHEN TBERT n/a n/a CNLB n/a TFAO T56 Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/Transmit Channel Number (TCH#). The CPU loads the number of the HDLC channels associated with this particular DS0 channel. If the port is running in an unchannelized mode (TUEN = 1), the HDLC channel number only needs to be loaded into T[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled. 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0)

00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2)

00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256

Bit 8/Transmit 56kbps (T56). If the port is running a channelized application, this bit determines whether or not the LSB of each DS0 should be processed. If this bit is set, the LSB of each DS0 channel is not routed from the HDLC controller (or the BERT, if it has been enabled through the RBERT bit), and the LSB bit position is forced to 1. 0 = 64kbps (use all 8 bits in the DS0) 1 = 56kbps (use only the first 7 bits transmitted in the DS0; force the LSB to 1)

Bit 9/Transmit Force All Ones (TFAO). If this bit is set, then eight 1s are placed into the DS0 channel for transmission instead of the data that is being sourced from the HDLC controller. If this bit is cleared, the data from the HDLC controller is transmitted. This bit is useful in instances when CLLB is being activated to keep the looped back data from being sent out onto the network. This bit overrides TCHEN. 0 = transmit data from the HDLC controller 1 = force transmit data to all 1s

Bit 11/Channelized Network Loopback Enable (CNLB). Enabling this loopback forces the receive data to replace the transmit data. This bit must be set for each and every DS0 channel that is to be looped back. This bit overrides TBERT, TFAO, and TCHEN. 0 = loopback disabled 1 = loopback enabled

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Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block instead of from the HDLC controller. If the DS0 channel has been configured for 56kbps operation (T56 = 1), the LSB of each DS0 channel is not routed from the BERT block but instead is forced to 1. In order for the data to make it from the BERT block, the host must also configure the BERT for the proper port through the master control register (Section 5

). This bit overrides TFAO and TCHEN.

0 = do not route data from BERT

1 = route data from BERT (override the data from the HDLC controller)

Bit 15/Transmit DS0 Channel Enable (TCHEN). This bit must be set for each active DS0 channel in a channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data from the BERT block. In addition, although a DS0 channel is active, the loopback function (CNLB = 1) overrides this activation and routes receive data to the TD pin instead of from the HDLC. In an unchannelized mode (TUEN = 1), only the TCHEN bit in T[n]CFG0 needs to be configured. 0 = deactivated DS0 channel 1 = active DS0 channel

6.4 Receive V.54 Detector

Each port within the device contains a V.54 loop pattern detector. V.54 is a pseudorandom pattern that is sent for at least 2 seconds, followed immediately by an all-ones pattern for at least 2 seconds if the channel is to be placed into loopback. The exact pattern and sequence is defined in Annex B of ANSI T1.403-1995.

When a port is configured for unchannelized operation (RUEN = 1), all data entering the port through RD is routed to the V.54 detector. If the host wishes not to use the V.54 detector, the SLBP status bits in the status V.54 (SV54) register should be ignored, and their corresponding interrupt mask bits in ISV54 should be set to 0 to keep from disturbing the host. Details about the status and interrupt bits can be found in Section 5.

When the port is configured for channelized operation (RUEN = 0), it is the host’s responsibility to determine which DS0 channels should be searched for the V.54 pattern. In channelized applications, it may be that there are multiple HDLC channels the host wishes to look in for the V.54 pattern. If this is true, then the host performs the routine shown in Table 6-B

Figure 6-5.

. A flow chart of the same routine is shown in

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Table 6-B. Receive V.54 Search Routine

STEP DIRECTION FUNCTION

By configuring the RV54 bit in the R[n]CFG[j] register, the host

1 Set up the channel search

2 Toggle VRST

3 Wait for SLBP

4 Read VTO and VLB

determines in which DS0 channels the V.54 search is to take place. If this search sequence does not detect the V.54 pattern, the host can pick some new DS0 channels and try again. Once the DS0 channels have been set, the host toggles the VRST bit in the RP[n]CR register and begins monitoring the SLBP status bit.

The SLBP status bit reports any change of state in the V.54 search process. It can also generate a hardware interrupt (Section 5 SLBP is set, the host knows that something significant has occurred and that it should read the VLB and VTO real-time status bits in the RP[n]CR register. If VTO = 1, the V.54 pattern did not appear in this set of channels and the host can reconfigure the search in other DS0 channels and move back to Step #1. If VLB = 1, the V.54 loop-up pattern has been detected and the channel should be placed into loopback. A loopback can be invoked by the host by configuring the CNLB bit in the T[n]CFG[j] register for each DS0 channel that needs to be placed into loopback. Move back to Step #3. If VLB = 0, if the DS0 channels are already in loopback, the host monitors VLB to know when the loop-down pattern has been detected and when to take the channels out of loopback. The DS0 channels are taken out of loopback by again configuring the CNLB bits. Move on to Step #1.

DS31256

). When

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Figure 6-5. Receive V.54 Host Algorithm

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NOTESALGORITHM

Set Up the DS0 Channel Search

Toggle VRST

Yes

VTO = 1?

Place DS0 Channels into Loopback

Take DS0 Channels out of Loopback

Wait for SLBP = 1

DS0 channels can be configured to search for the V.54 loop pattern via the Receive Layer 1 Configuration Register (see Section 5.3)

VRST is a control bit that is in the Receive Port Control Register (see Section 5.2)

SLBP is a status bit that is reported in the SV54 register (see Section 4.3)

VTO is a status bit that is in the Receive Port Control Register (see Section 5.2)

DS0 channels can be placed into loopback via the Receive Layer 1 Configuration Register (see Section 5.3)

SLBP is a status bit that is reported in the SV54 register (see Section 4.3)

DS0 channels can be taken out of loopback via the Receive Layer 1 Configuration Register (see Section 5.3)

v54host

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Figure 6-6. Receive V.54 State Machine

VRST = 1

VLB = 0 VTO = 0 SLBP = 0

VRST (in RP[n]CR)

SYSCLK

Search for Loop Up Pattern for 32 VCLKs

Sync = 0

Sync = 1

Reset 4 second timer; wait for Loss of Sync or All 1s (64 in a Row) or for the 4 second timer to expire

All Ones

CLK

Data

V.54 State Machine

Sysclk is used only to time a 4 second timer. It is run into a 2E27 counter which provides a 4.03 second time out with a 33MHz clock and a 5.37 second time out with a 25MHz clock

DS31256

Time Out (VTO) Loopback (VLB); both in RP[n]CR

Change of State in Status (SLBP); in SV54

Sync = 0 or 4 Second Timer Has Expired

VTO = 1

SLBP = 1

VLB = 0

Search for Loop Down Pattern VLB = 1

Sync = 1

Sync = 0

wait for Loss of Sync or All 1s (64 in a Row)

All Ones

v54sm

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6.5 BERT

The BERT block is capable of generating and detecting the following patterns:

§ The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS

§ A repetitive pattern from 1 to 32 bits in length

§ Alternating (16-bit) words that flip every 1 to 256 words

The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters. See Section 5 for details on status bits and interrupts from the BERT block. To activate the BERT block, the host must configure the BERT mux (Figure 6-7). In channelized applications, the host must also configure the Layer 1 state machine to send/obtain data to/from the BERT block through the Layer 1 configuration registers (Section 6.3).

Figure 6-7. BERT Mux Diagram

Port 0 (slow)

SBERT STATUS BIT IN SM

BERT

BLOCK

INTERNAL CONTROL AND

CONFIGURATION BUS

BERT Mux

Port 1 (slow)

Port 2 (slow)

Port 3 (slow)

Port 4 (slow)

Port 5 (slow)

Port 13 (slow)

Port 14 (slow)

Port 15 (slow)

Port 0 (fast)

Port 1 (fast)

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BERT SELECT (5) IN THE MASTER CONFIGURATION REGISTER

6.6 BERT Register Description

Figure 6-8. BERT Register Set

BERTC0: BERT Control 0 LSB

n/a TINV RINV PS2 PS1 PS0 LC RESYNC

MSB

IESYNC IEBED IEOF n/a RPL3 RPL2 RPL1 RPL0

BERTC1: BERT Control 1 LSB

EIB2 EIB1 EIB0 SBE n/a

MSB

Alternating Word Count

BERTRP0: BERT Repetitive Pattern Set 0 (lower word) LSB

BERT Repetitive Pattern Set (lower byte)

MSB

BERT Repetitive Pattern Set

BERTRP1: BERT Repetitive Pattern Set 1 (upper word) LSB

BERT Repetitive Pattern Set

MSB

BERT Repetitive Pattern Set (upper byte)

BERTBC0: BERT Bit Counter 0 (lower word) LSB

BERT 32-Bit Bit Counter (lower byte)

MSB

BERT 32-Bit Bit Counter

BERTBC1: BERT Bit Counter 0 (upper word) LSB

BERT 32-Bit Bit Counter

MSB

BERT 32-Bit Bit Counter (upper byte)

BERTEC0: BERT Error Counter 0/Status LSB

n/a RA1 RA0 RLOS BED BBCO BECO SYNC

MSB

BERT 24-Bit Error Counter (lower byte)

BERTEC1: BERT Error Counter 1 (upper word) LSB

BERT 24-Bit Error Counter

MSB

BERT 24-Bit Error Counter (upper byte)

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n/a n/a TC

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Bit # 7 6 5 4 3 2 1 0 Name n/a TINV RINV PS2 PS1 PS0 LC RESYNC Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IESYNC IEBED IEOF n/a RPL3 RPL2 RPL1 RPL0 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. It must be cleared and set again for a subsequent resynchronization.

Note: Bits 2, 3, and 4 must be set, minimum of 64 system clock cycles, before toggling the resync bit (bit 0).

Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into

the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for subsequent loads.

Bit 2/Pattern Select Bit 0 (PS0); Bit 3/Pattern Select Bit 1 (PS1); Bit 4/Pattern Select Bit 2 (PS2) 000 = pseudorandom pattern 2E7 - 1 001 = pseudorandom pattern 2E11 - 1 010 = pseudorandom pattern 2E15 - 1 011 = pseudorandom pattern QRSS (2E20 - 1 with a 1 forced, if the next 14 positions are 0) 100 = repetitive pattern 101 = alternating word pattern 110 = illegal state 111 = illegal state

Bit 5/Receive Invert Data Enable (RINV)

0 = do not invert the incoming data stream 1 = invert the incoming data stream

Bit 6/Transmit Invert Data Enable (TINV)

0 = do not invert the outgoing data stream 1 = invert the outgoing data stream

Bit 8/Repetitive Pattern Length Bit 0 (RPL0); Bit 9/Repetitive Pattern Length Bit 1 (RPL1); Bit 10/Repetitive Pattern Length Bit 2 (RPL2); Bit 11/Repetitive Pattern Length Bit 3 (RPL3). RPL0 is the

LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).

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Repetitive Pattern Length Map

Length Code Length Code Length Code Length Code

17 Bits 0000 18 Bits 0001 19 Bits 0010 20 Bits 0011 21 Bits 0100 22 Bits 0101 23 Bits 0110 24 Bits 0111 25 Bits 1000 26 Bits 1001 27 Bits 1010 28 Bits 1011 29 Bits 1100 30 Bits 1101 31 Bits 1101 32 Bits 1111

Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either the bit counter or the error counter overflows. 0 = interrupt masked 1 = interrupt enabled

Bit 14/Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an interrupt if a bit error is detected. 0 = interrupt masked 1 = interrupt enabled

Bit 15/Interrupt Enable for Change-of-Synchronization Status (IESYNC). Allows the receive BERT to cause an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT either goes into or out of synchronization). 0 = interrupt masked 1 = interrupt enabled

Bit # 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIB0 SBE n/a n/a Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name Alternating Word Count Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with repetitive or pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for subsequent loads.

Bit 4/Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set again for a subsequent bit error to be inserted.

Bit 5/Error Insert Bit 0 (EIB0); Bit 6/Error Insert Bit 1 (EIB1); Bit 7/Error Insert Bit 2 (EIB2).

Automatically inserts bit errors at the prescribed rate into the generated data pattern. Useful for verifying error detection operation.

n/a TC

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EIB2 EIB1 EIB0 Error Rate Inserted

0 0 0 No errors automatically inserted 0 0 1 10E-1 0 1 0 10E-2 0 1 1 10E-3 1 0 0 10E-4 1 0 1 10E-5 1 1 0 10E-6 1 1 1 10E-7

Bits 8 to 15/Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the words repeat for the count loaded into this register, then flip to the other word and again repeat for the number of times loaded into this register. The valid count range is from 05h to FFh.

BERTRP0: BERT Repetitive Pattern Set 0 (lower word)

Bit # 7 6 5 4 3 2 1 0 Name BERT Repetitive Pattern Set (lower byte) Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name Bert Repetitive Pattern Set Default 0 0 0 0 0 0 0 0

BERTRP1: BERT Repetitive Pattern Set 1 (upper word)

Bit # 23 22 21 20 19 18 17 16 Name BERT Repetitive Pattern Set Default 0 0 0 0 0 0 0 0

Bit #

31 30 29 28 27 26 25 24

Name Bert Repetitive Pattern Set (upper byte) Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 31/BERT Repetitive Pattern Set (BERTRP0 and BERTRP1). These registers must be properly loaded for the BERT to properly generate and synchronize to either a repetitive pattern, a pseudorandom pattern, or an alternating word pattern. For a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the repeating 5-bit pattern …01101… (where the right-most bit is sent first and received first), then PBRP0 should be loaded with xB5AD and PBRP1 should be loaded with x5AD6. For a pseudorandom pattern, both registers should be loaded with all ones (i.e., xFFFF). For an alternating word pattern, one word should be placed into PBRP0 and the other word should be placed into PBRP1. For example, if the DDS stress pattern “7E” is to be described, the user would place x0000 in PBRP0 and x7E7E in PBRP1 and the alternating word counter would be set to 50 (decimal) to allow 100 Bytes of 00h followed by 100 Bytes of 7Eh to be sent and received.

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BERTBC0: BERT Bit Counter 0 (lower word)

Bit # 7 6 5 4 3 2 1 0 Name BERT 32-Bit Bit Counter (lower byte) Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name BERT 32-Bit Bit Counter Default 0 0 0 0 0 0 0 0

BERTBC1: BERT Bit Counter 0 (upper word)

Bit # 23 22 21 20 19 18 17 16 Name BERT 32-Bit Bit Counter Default 0 0 0 0 0 0 0 0

Bit # 31 30 29 28 27 26 25 24 Name BERT 32-Bit Bit Counter (upper byte) Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write

Bits 0 to 31/BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter increments for each data bit (i.e., clock) received. This counter is not disabled when the receive BERT loses synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from low (0) to high (1). When full, this counter saturates and sets the BBCO status bit.

Register Name: BERTEC0 Register Description: BERT 24-Bit Error Counter (lower) and Status Information Register Address: 0518h

Bit # 7 6 5 4 3 2 1 0 Name reserved RA1 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name BERT 24-Bit Error Counter (lower byte) Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Real-Time Synchronization Status (SYNC). Real-time status of the synchronizer (this bit is not latched). Is set when the incoming pattern matches for 32 consecutive bit positions. Is cleared when six or more bits out of 64 are received in error.

RA0 RLOS BED BBCO BECO SYNC

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Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs.

Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Cleared when read and is not set again until another overflow occurs.

Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Cleared when read.

Bit 4/Receive Loss of Synchronization (RLOS). A latched bit that is set whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit remains set until read.

Bit 5/Receive All Zeros (RA0). A latched bit that is set when 31 consecutive 0s are received. Allowed to be cleared once a 1 is received.

Bit 6/Receive All Ones (RA1). A latched bit that is set when 31 consecutive 1s are received. Allowed to be cleared once 0 is received.

Bits 8 to 15/BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the BERTEC1 register description for details.

Bit # 7 6 5 4 3 2 1 0 Name BERT 24-Bit Error Counter Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name BERT 24-Bit Error Counter (upper byte) Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write. default value for all bits is 0.

Bits 0 to 15/BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This 24-bit counter increments for each data bit received in error. This counter is not disabled when the receive BERT loses synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from low (0) to high (1). When full, this counter saturates and sets the BECO status bit.

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7. HDLC

7.1 General Description

The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine (type #1) associated with it that can operate in either a channelized mode up to 8.192Mbps or an unchannelized mode at rates up to 10Mbps. Ports 0 and 1 also have an additional fast HDLC engine (type #2) that can operate in only an unchannelized fashion up to 52Mbps. Through the Layer 1 registers (Section 6.2), the host determines which type of HDLC controller is used on a port and if the HDLC controller is to be operated in either a channelized or unchannelized mode. If the HDLC controller is to be operated in the channelized mode, then the Layer 1 registers (Section 6.3) also determine which HDLC channels are associated with which DS0 channels. If the fast HDLC engine is enabled on port 0, HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 1 if it is enabled.

The HDLC controllers can handle all required normal real-time tasks. Table 7-B supported by the receive HDLC and Table 7-C

lists all the functions supported by the transmit HDLC.

lists all the functions

Each of the 256 HDLC channels within the DS31256 Envoy are configured by the host through the receive HDLC channel definition (RHCD) and transmit channel definition (THCD) registers. There is a separate RHCD and THCD register for each HDLC channel. The host can access the RHCD and THCD registers indirectly through the RHCDIS indirect select and THCDIS indirect select registers. See Section 7.2 for details.

On the receive side, one of the outcomes shown in Table 7-A occurs when the HDLC block is processing a packet. For each packet, one of these outcomes is reported in the receive done-queue descriptor (Section 9.2.4). On the transmit side, when the HDLC block is processing a packet, an error in the PCI block (parity or target abort) or transmit FIFO underflow causes the HDLC block to send an abort sequence (eight 1s in a row) followed continuously by the selected interfill (either 7Eh or FFh) until the HDLC channel is reset by the transmit DMA block (Section 9.3.1). This same sequence of events will occur even if the transmit HDLC channel is being operated in the transparent mode. In the transparent mode, when the FIFO empties the device sends either 7Eh or FFh.

If any of the 256 receive HDLC channels detects an abort sequence, an FCS checksum error, or if the packet length was incorrect, then the appropriate status bit in SDMA is set. If enabled, the setting of any of these statuses can cause a hardware interrupt to occur. See Section 5.3.2 for details about the operation of these status bits.

Table 7-A. Receive HDLC Packet Processing Outcomes

OUTCOME CRITERIA

EOF/Normal Packet Integral number of packets > min and < max is received and CRC is okay EOF/Bad FCS Integral number of packets > min and < max is received and CRC is bad Abort Detected Seven or more 1s in a row detected EOF/Too Few Bytes Fewer than 4 or 6 Bytes received Too Many Bytes Greater than the packet maximum is received (if detection enabled) EOF/Bad # of Bits Not an integral number of bytes received FIFO Overflow Tried to write a byte into an already full FIFO

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Table 7-B. Receive HDLC Functions

FUNCTION DESCRIPTION

DS31256

Zero Destuff

Flag Detection and Byte Alignment

Octet Length Check

CRC Check

Abort Detection

Invert Data

Bit Flip

Transparent Mode

This operation is disabled if the channel is set to transparent mode.

Okay to have two packets separated by only one flag or by two flags sharing a 0. This operation is disabled if the channel is set to transparent mode. The minimum check is for 4 Bytes with CRC-16 and 6 Bytes with CRC-32 (packets with less than the minimum lengths are not passed to the PCI bus). The maximum check is programmable up to 65,536 Bytes through the RHPL register. The maximum check can be disabled through the ROLD control bit in the RHCD register. The minimum and maximum counts include the FCS. An error is also reported if a noninteger number of octets occur between flags. Can be either set to CRC-16 or CRC-32 or none. The CRC can be passed through to the PCI bus or not. The CRC check is disabled if the channel is set to transparent mode.

Checks for seven or more 1s in a row.

All data (including the flagsand FCS) is inverted before HDLC processing. Also available in the transparent mode.

The first bit received becomes either the LSB (normal mode) or the MSB (telecom mode) of the byte stored in the FIFO. Also available in the transparent mode. If enabled, flag detection, zero destuffing, abort detection, length checking, and FCS checking are disabled. Data is passed to the PCI bus on octet (i.e., byte) boundaries in channelized operation.

Table 7-C. Transmit HDLC Functions

Only used between opening and closing flags.

Zero Stuffing

Interfill Selection

Flag Generation

CRC Generation

Invert Data

Bit Flip

Transparent Mode

Invert FCS

Is disabled between a closing flag and an opening flag and for sending aborts and/or interfill data. Disabled if the channel is set to the transparent mode.

Can be either 7Eh or FFh.

A programmable number of flags (1 to 16) can be set between packets. Disabled if the channel is set to the transparent mode. Can be either CRC-16 or CRC-32 or none. Disabled if the channel is set to transparent mode. All data (including the flags and FCS) is inverted after processing. Also available in the transparent mode. The LSB (normal mode) of the byte from the FIFO becomes the first bit sent or the MSB (telecom mode) becomes the first bit sent. Also available in the transparent mode. If enabled, flag generation, zero stuffing, and FCS generation is disabled. Passes bytes from the PCI Bus to Layer 1 on octet (byte) boundaries.

When enabled, it inverts all of the bits in the FCS (useful for HDLC testing).

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7.2 HDLC Register Description

Bit # 7 6 5 4 3 2 1 0 Name HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0) 00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1) 00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2) 00000011 (03h) = HDLC channel number 4 11111111 (FFh) = HDLC channel number 256

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive HDLC definition RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RHCD register, the IAB bit is set to 0. When the host wishes to write data to the internal receive HDLC definition RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the RHCD register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit sets to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation completes.

Bit # 7 6 5 4 3 2 1 0 Name RABTD RCS RBF RID RCRC1 RCRC0 ROLD RTRANS Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name n/a n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC controller performs flag delineation, zero destuffing, abort detection, octet length checking (if enabled through ROLD), and FCS checking (if enabled through RCRC0/1). When this bit is set high, the HDLC controller does not perform flag delineation,

IARW n/a n/a n/a n/a n/a n/a

n/a n/a n/a n/a RPEN RZDD

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zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the device must not be configured to write done-queue descriptors only at the end of a packet, if it is desired that donequeue descriptors be written; there is not an end of packet on the receive side in transparent mode by definition. Please note that an end of packet does not occur on the receive side while in transparent mode. 0 = transparent mode disabled 1 = transparent mode enabled

Bit 1/Receive Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC engine does not check to see if the octet length of the received packets exceeds the count loaded into the receive HDLC packet length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the octet length of the received packets exceeds the count loaded into the RHPL register. When an incoming packet exceeds the maximum length, the packet is aborted and the remainder is discarded. This bit is ignored if the HDLC channel is set to transparent mode (RTRANS = 1). 0 = octet length detection disabled 1 = octet length detection enabled

Bits 2, 3/Receive CRC Selection (RCRC0/RCRC1). These two bits are ignored if the HDLC channel is set into transparent mode (RTRANS = 1).

RCRC1 RCRC0 ACTION

0 0 No CRC verification performed 0 1 16-bit CRC (CCITT/ITU Q.921) 1 0 32-bit CRC 1 1 Illegal state

Bit 4/Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not inverted before processing. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and FCS) before processing the data. The data is not reinverted before passing to the FIFO. 0 = do not invert data 1 = invert all data (including flags and FCS)

Bit 5/Receive Bit Flip (RBF). When this bit is set low, the HDLC engine places the first HDLC bit received in the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the HDLC controller places the first HDLC bit received in the highest bit position of the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]). 0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI bus 1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI bus

Bit 6/Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through to the PCI bus. When this bit is set low, the HDLC engine includes the 2-Byte FCS (16-bit) or 4-Byte FCS (32-bit) in the data that it transfers to the PCI bus. This bit is ignored if the HDLC channel is set into transparent mode (RTRANS = 1). 0 = send FCS to the PCI bus 1 = do not send the FCS to the PCI bus

Bit 7/Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine examines the incoming data stream for the abort sequence, which is seven or more consecutive 1s. When this bit is set high, the incoming data stream is not examined for the abort sequence, and, if an incoming abort sequence is received, no action is taken. This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1).

Bit 8/Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine zero destuffs the incoming data stream. When this bit is set high, the HDLC engine does not zero destuff the incoming data stream. This bit is ignored when the HDLC engine is configured in the transparent mode (RTRANS = 1).

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Bit # 7 6 5 4 3 2 1 0 Name RHPL7 RHPL6 RHPL5 RHPL4 RHPL3 RHPL2 RHPL1 RHPL0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name RHPL15 RHPL14 RHPL13 RHPL12 RHPL11 RHPL10 RHPL9 RHPL8 Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write. This is a globe control; only one per device, not one for each individual HDLC channel.

Bits 0 to 15/Receive HDLC Packet Length (RHPL0 to RHPL15). If the receive length-detection enable bit is set to 1, the HDLC engine checks the number of received octets in a packet to see if they exceed the count in this register. If the length is exceeded, the packet is aborted and the remainder is discarded. The definition of “octet length” is everything between the opening and closing flags, which includes the address field, control field, information field, and FCS.

Bit # 7 6 5 4 3 2 1 0 Name HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB IARW n/a n/a n/a n/a n/a n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit HDLC definition RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the THCD register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit HDLC definition RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the THCD register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is to 0 once the write operation is complete.

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Bit # 7 6 5 4 3 2 1 0 Name TABTE TCFCS TBF TID TCRC1 TCRC0 TIFS TTRANS Default

Bit # 15 14 13 12 11 10 9 8 Name n/a n/a Default

Note: Bits that are underlined are read only, all other bits are read-write.

n/a TZSD TFG3 TFG2 TFG1 TFG0

Bit 0/Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine generates flags and the FCS (if enabled through TCRC0/1) and performs zero stuffing. When this bit is set high, the HDLC controller does not generate flags or the FCS and does not perform zero stuffing. 0 = transparent mode disabled 1 = transparent mode enabled

Bit 1/Transmit Interfill Select (TIFS)

0 = the interfill byte is 7Eh (01111110) 1 = the interfill byte is FFh (11111111)

Bits 2, 3/Transmit CRC Selection (TCRC0/TCRC1). These bits are ignored if the HDLC channel is set to transparent mode (TTRANS = 1).

TCRC1 TCRC0 ACTION

0 0 No CRC is generated 0 1 16-bit CRC (CCITT/ITU Q.921) 1 0 32-bit CRC 1 1 Illegal state

Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted after being generated. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and FCS) after the packet has been generated. 0 = do not invert data 1 = invert all data (including flags and FCS)

Bit 5/Transmit Bit Flip (TBF). When this bit is set low, the HDLC controller obtains the first HDLC bit to be transmitted from the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the HDLC engine obtains the first HDLC bit to be transmitted from the highest bit position of the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]). 0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the PCI bus

1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the PCI bus

Bit 6/Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine allows the frame checksum sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC engine inverts all the bits of the FCS before transmission occurs. This is useful in debugging and testing HDLC channels at the system level. 0 = generate FCS normally 1 = invert all FCS bits

Bit 7/Transmit Abort Enable (TABTE). When this bit is set low, the HDLC engine performs normally, only sending an abort sequence (eight 1s in a row) when an error occurs in the PCI block or the FIFO underflows. When this bit is set high, the HDLC engine continuously transmits an all-ones pattern (i.e., an abort sequence). This bit is still active when the HDLC engine is configured in the transparent mode (TTRANS = 1).

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Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how many flags and interfill bytes are sent between consecutive packets.

TFG3 TFG2 TFG1 TFG0 ACTION

0 0 0 0 Share closing and opening flag 0 0 0 1 Closing flag/no interfill bytes/opening flag 0 0 1 0 Closing flag/1 interfill byte/opening flag 0 0 1 1 Closing flag/2 interfill bytes/opening flag 0 1 0 0 Closing flag/3 interfill bytes/opening flag 0 1 0 1 Closing flag/4 interfill bytes/opening flag 0 1 1 0 Closing flag/5 interfill bytes/opening flag 0 1 1 1 Closing flag/6 interfill bytes/opening flag 1 0 0 0 Closing flag/7 interfill bytes/opening flag 1 0 0 1 Closing flag/8 interfill bytes/opening flag 1 0 1 0 Closing flag/9 interfill bytes/opening flag 1 0 1 1 Closing flag/10 interfill bytes/opening flag 1 1 0 0 Closing flag/11 interfill bytes/opening flag 1 1 0 1 Closing flag/12 interfill bytes/opening flag 1 1 1 0 Closing flag/13 interfill bytes/opening flag 1 1 1 1 Closing flag/14 interfill bytes/opening flag

Bit 12/Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC engine performs zero stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is not zero stuffed. This bit is ignored when the HDLC engine is configured in the transparent mode (TTRANS = 1).

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8. FIFO

8.1 General Description and Example

The DS31256 Envoy contains one 16kB FIFO for the receive path and another 16kB FIFO for the transmit path. Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each FIFO is made up of 1024 blocks. Figure 8-1 shows an FIFO example.

The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready for transfer to/from the FIFO from/to the HDLC engines. The 16 ports are priority decoded with port 0 getting the highest priority and port 15 getting the lowest priority. Therefore, all the enabled HDLC channels on the lower numbered ports are serviced before the higher numbered ports. As long as the maximum throughput rate of 132Mbps is not exceeded, the DS31256 ensures there is enough bandwidth in this transfer to prevent any data loss between the HDLC engines and the FIFO.

The FIFO also controls which HDLC channel the DMA should service to read data out of the FIFO on the receive side and to write data into the FIFO on the transmit side. Which channel gets the highest priority from the FIFO is configurable through some control bits in the master configuration register (Section 5.2). There are two control bits for the receive side (RFPC0 and RFPC1) and two control bits for the transmit side (TFPC0 and TFPC1) that will determine the priority algorithm as shown in

Table 8-A.

Table 8-A. FIFO Priority Algorithm Select

OPTION

1 None 1 to 256 2 1 to 3 4 to 256 3 16 to 1 17 to 256 4 64 to 1 65 to 256

HDLC CHANNELS THAT ARE

PRIORITY DECODED

To maintain maximum flexibility for channel reconfiguration, each block within the FIFO can be assigned to any of the 256 HDLC channels. Also, blocks are link-listed together to form a chain whereby each block points to the next block in the chain. The minimum size of the link-listed chain is 4 blocks (64 Bytes) and the maximum is the full size of the FIFO, which is 1024 blocks.

To assign a set of blocks to a particular HDLC channel, the host must configure the starting block pointer and the block pointer RAM. The starting block pointer assigns a particular HDLC channel to a set of link-listed blocks by pointing to one of the blocks within the chain (it does not matter which block in the chain is pointed to). The block pointer RAM must be configured for each block that is being used within the FIFO. The block pointer RAM indicates the next block in the link-listed chain.

Figure 8-1 shows an example of how to configure the starting block pointer and the block pointer RAM.

In this example, only three HDLC channels are being used (channels 2, 6, and 16). The device knows that channel 2 has been assigned to the eight link-listed blocks of 112, 118, 119, 120, 121, 122, 125, and 126 because a block pointer of 125 has been programmed into the channel 2 position of the starting block pointer. The block pointer RAM tells the device how to link the eight blocks together to form a circular chain.

HDLC CHANNELS THAT ARE SERVICED

ROUND ROBIN

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The host must set the watermarks for the receive and transmit paths. The receive path has a high watermark and the transmit path has a low watermark.

Figure 8-1. FIFO Example

HDLC Channel Number

CH 1

CH 2

CH 3

CH 4

CH 5

CH 6

CH 7

CH 8

CH 9

CH 10

CH 11

CH 12

CH 13

CH 14

CH 15

Starting Block Pointer

not used

Block Pointer 125

not used

Block Pointer 113

not used

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 112

Block 113

Block 114

Block 115

Block 116

Block 117

1024 Block FIFO (1 Block = 4 dwords)

not used

Channel 16

not used

Channel 2

Channel 6

not used

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 112

Block 113

Block 114

Block 115

Block 116

Block 117

Block Pointer RAM

not used

Block 4

Block 5

Block 3

Block 2

not used

Block 118

Block 114

Block 113

not used

CH 16

CH 17

CH 18

CH 19

CH 20

CH 21

CH 255

CH 256

Block Pointer 5

not used

fifobd.drw

Block 118

Block 119

Block 120

Block 121

Block 122

Block 123

Block 124

Block 125

Block 126

Block 127

Block 1022

Block 1023

Channel 2

not used

Channel 2

not used

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Block 118

Block 119

Block 120

Block 121

Block 122

Block 123

Block 124

Block 125

Block 126

Block 127

Block 1022

Block 1023

Block 119

Block 120

Block 121

Block 122

Block 125

not used

Block 126

Block 112

not used

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8.1.1 Receive High Watermark

The high watermark tells the device how many blocks the HDLC engines should write into the receive FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before it should be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected. For example, if four blocks were link-listed together and the host programmed the high watermark to three blocks, then the DMA would read the data out of the FIFO and transfer it to the PCI bus after the HDLC controller had written three complete blocks in succession into the FIFO and still had one block left to fill. The DMA would not read the data out of the FIFO again until another three complete blocks had been written into the FIFO in succession by the HDLC engine or until an EOF was detected. In this example of four blocks being link-listed together, the high watermark could also be set to 1 or 2, but no other values would be allowed. If an incoming packet does not fill the FIFO enough to reach the high watermark before an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does not wait for additional data the HDLC engines write into the FIFO.

8.1.2 Transmit Low Watermark

The low watermark tells the device how many blocks should be left in the FIFO before the DMA should begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For example, if five blocks were link-listed together and the host programmed the low watermark to two blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC engine has read three complete blocks in succession from the FIFO and, therefore, still had two blocks left before the FIFO was empty. The DMA would not read the data from the PCI bus again until another three complete blocks had been read from the FIFO in succession by the HDLC controllers. In this example of five blocks being link-listed together, the low watermark could also be set to any value from 1 to 3 (inclusive) but no other values would be allowed. In other words, the tranmist low watermark can be set to a value of 1 to N - 2, where N = number of blocks linked together. When a new packet is written into a completely empty FIFO by the DMA, the HDLC controllers wait until the FIFO fills beyond the low watermark or until an EOF is seen before reading the data out of the FIFO.

8.2 FIFO Register Description

Bit # 7 6 5 4 3 2 1 0 Name HCID7 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)

00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256

HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0

IARW n/a n/a n/a n/a n/a n/a

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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0.

Note: The RFSBPIS is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory.

Bit # 7 6 5 4 3 2 1 0 Name RSBP7 RSBP6 RSBP5 RSBP4 RSBP3 RSBP2 RSBP1 RSBP0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a Default

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a RSBP9 RSBP8

Bits 0 to 9/Starting Block Pointer (RSBP0 to RSBP9). These bits determine which of the 1024 blocks within the receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block

Bit # 7 6 5 4 3 2 1 0 Name BLKID7 BLKID6 BLKID5 BLKID4 BLKID3 BLKID2 BLKID1 BLKID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB IARW n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a BLKID9 BLKID8

Bits 0 to 9/Block ID (BLKID0 to BLKID9) 0000000000 (000h) = block number 0 0111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023

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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal receive block pointer RAM, the host should write this bit to 0. This causes the device to take the data that is currently present in the RFBP register and write it to the channel location indicated by the BLKID bits. When the device completes the write, the IAB is set to 0.

Note: The RFSBP is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory.

Bit # 7 6 5 4 3 2 1 0 Name RBP7 RBP6 RBP5 RBP4 RBP3 RBP2 RBP1 RBP0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a Default

Note: Bits that are underlined are read only, all other bits are read-write.

n/a n/a n/a n/a n/a RBP9 RBP8

Bits 0 to 9/Block Pointer (RBP0 to RBP9). These bits indicate which of the 10242 blocks is the next block in the link-list chain. A block is not allowed to point to itself. 0000000000 (000h) = block 0 is the next linked block 0111111111 (1FFh) = block 511 is the next linked block 1111111111 (3FFh) = block 1023 is the next linked block

Bit # 7 6 5 4 3 2 1 0 Name HCID7

HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

IARW n/a n/a n/a n/a n/a n/a

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive highwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFHWM register, the IAB bit is set to 0. When the host wishes to write data to the internal receive high-watermark RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the RFHWM register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0.

Bit # 7 6 5 4 3 2 1 0 Name RHWM7 RHWM6 RHWM5 RHWM4 RHWM3 RHWM2 RHWM1 RHWM0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a Default

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a RHWM9 RHWM8

Bits 0 to 9/High Watermark (RHWM0 to RHWM9). These bits indicate the setting of the receive highwatermark. The high-watermark setting is the number of successive blocks that the HDLC controller writes to the FIFO before the DMA sends the data to the PCI bus. The high-watermark setting must be between (inclusive) one block and one less than the number of blocks in the link-list chain for the particular channel involved. For example, if four blocks are linked together, the high watermark can be set to either 1, 2, or 3. In other words, the high watermark can be set to a value of 1 to N - 1, where N = number of block linked together. Any other numbers are illegal. 0000000000 (000h) = invalid setting 0000000001 (001h) = high watermark is 1 block 0000000010 (002h) = high watermark is 2 blocks 0111111111 (1FFh) = high watermark is 511 blocks 1111111111 (3FFh) = high watermark is 1023 blocks

Register Name: TFSBPIS Register Description: Transmit FIFO Starting Block Pointer Indirect Select Register Address: 0980h

Bit # 7 6 5 4 3 2 1 0 Name HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

IARW n/a n/a n/a n/a n/a n/a

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Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to the internal transmit starting block pointer RAM, this bit should be written to 1 by the host. This causes the device to take the data that is in the TFSBP register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0.

Note: The TFSBP register is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory.

Bit # 7 6 5 4 3 2 1 0 Name TSBP7 TSBP6 TSBP5 TSBP4 TSBP3 TSBP2 TSBP1 TSBP0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a Default

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a TSBP9 TSBP8

Bits 0 to 9/Starting Block Pointer (TSBP0 to TSBP9). These bits determine which of the 1024 blocks within the transmit FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to read data from the transmit FIFO by the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block

Bit # 7 6 5 4 3 2 1 0 Name BLKID7 BLKID6 BLKID5 BLKID4 BLKID3 BLKID2 BLKID1 BLKID0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

IARW n/a n/a n/a n/a BLKID9 BLKID8

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Bits 0 to 9/Block ID (BLKID0 to BLKID9) 00000000000 (000h) = block number 0 01111111111 (1FFh) = block number 511

1111111111 (3FFh) = block number 1023

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit block pointer RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit block pointer RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the TFBP register and write it to the channel location indicated by the BLKID bits. When the device has completed the write, the IAB is set to 0.

Bit # 7 6 5 4 3 2 1 0 Name TBP7 TBP6 TBP5 TBP4 TBP3 TBP2 TBP1 TBP0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a n/a Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 9/Block Pointer (TBP0 to TBP9). These bits indicate which of the 1024 blocks is the next block in the link list chain. A block is not allowed to point to itself. 0000000000 (000h) = block 0 is the next linked block 0111111111 (1FFh) = block 511 is the next linked block 1111111111 (3FFh) = block 1023 is the next linked block

Bit # 7 6 5 4 3 2 1 0 Name HCID7

HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0

Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name IAB Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only, all other bits are read-write.

IARW n/a n/a n/a n/a n/a n/a

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256

n/a n/a n/a n/a TBP9 TBP8

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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit lowwatermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the TFLWM register, the IAB bit is set to 0. When the host wishes to write data to the internal transmit low-watermark RAM, this bit should be written to 0 by the host. This causes the device to take the data that is currently present in the TFLWM register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0.

Bit # 7 6 5 4 3 2 1 0 Name TLWM7 TLWM6 TLWM5 TLWM4 TLWM3 TLWM2 TLWM1 TLWM0 Default

Bit # 15 14 13 12 11 10 9 8 Name n/a Default

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a n/a TLWM9 TLWM8

Bits 0 to 9/Low Watermark (TLWM0 to TLWM9). These bits indicate the setting of the transmit low watermark. The low watermark setting is the number of blocks left in the transmit FIFO before the DMA gets more data from the PCI bus. The low-watermark setting must be between (inclusive) one block and one less than the number of blocks in the link-list chain for the particular channel involved. For example, if five blocks are linked together, the low watermark can be set to 1, 2, or 3. In other words, the low watermark can be set at a value of 1 to N - 2, where N = number of block linked together. Any other numbers are illegal. 0000000000 (000h) = invalid setting 0000000001 (001h) = low watermark is 1 block 0000000010 (002h) = low watermark is 2 blocks 0111111111 (1FFh) = low watermark is 511 blocks 1111111111 (3FFh) = low watermark is 1023 blocks

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9. DMA

9.1 Introduction

The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block and vice versa. Throughout this section, the terms host and descriptor are used. Host is defined as the CPU or intelligent controller that sits on the PCI bus and instructs the device about how to handle the incoming and outgoing packet data. Descriptor is defined as a preformatted message that is passed from the host to the DMA block or vice versa to indicate where packet data should be placed or obtained from.

On power-up, the DMA is disabled because the RDE and TDE control bits in the master configuration register (Section 5) are set to 0. The host must configure the DMA by writing to all of the registers listed in Table 9-A (which includes all 256 channel locations in the receive and transmit configuration RAMs), then enable the DMA by setting to the RDE and TDE control bits to 1.

The structure of the DMA is such that the receive and transmit side descriptor-address spaces can be shared, even among multiple chips on the same bus. Through the master control register, the host determines how long the DMA is allowed to burst onto the PCI bus. The default value is 32 dwords (128 Bytes) but, through the DT0 and DT1 control bits, the host can enable the receive or transmit DMAs to burst either 64 dwords (256 Bytes), 128 dwords (512 Bytes), or 256 dwords (1024 Bytes).

The receive and transmit packet descriptors have almost identical structures (Sections 9.2.2 and 9.3.2), which provide a minimal amount of host intervention in store-and-forward applications. In other words, the receive descriptors created by the receive DMA can be used directly by the transmit DMA. The receive and transmit portions of the DMA are completely independent and are discussed separately.

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Table 9-A. DMA Registers to be Configured by the Host on Power-Up

ADDRESS NAME REGISTER SECTION

0700 RFQBA0 Receive Free-Queue Base Address 0 (lower word) 9.2.3 0704 RFQBA1 Receive Free-Queue Base Address 1 (upper word) 9.2.3 0708 RFQEA Receive Free-Queue End Address 9.2.3

070C RFQSBSA Receive Free-Queue Small Buffer Start Address 9.2.3

071C RFQSBRP Receive Free-Queue Small Buffer DMA Read Pointer 9.2.3

0730 RDQBA0 Receive Done-Queue Base Address 0 (lower word) 9.2.4 0734 RDQBA1 Receive Done-Queue Base Address 1 (upper word) 9.2.4 0738 RDQEA Receive Done-Queue End Address 9.2.4

073C RDQRP Receive Done-Queue Host Read Pointer 9.2.4

0740 RDQWP Receive Done-Queue DMA Write Pointer 9.2.4 0744 RDQFFT Receive Done-Queue FIFO Flush Timer 9.2.4 0750 RDBA0 Receive Descriptor Base Address 0 (lower word) 9.2.2 0754 RDBA1 Receive Descriptor Base Address 1 (upper word) 9.2.2 0770 RDMACIS Receive DMA Configuration Indirect Select 9.2.5 0774 RDMAC Receive DMA Configuration (all 256 channels) 9.2.5 0780 RDMAQ Receive DMA Queues Control 9.2.3, 9.2.4 0790 RLBS Receive Large Buffer Size 9.2.1 0794 RSBS Receive Small Buffer Size 9.2.1 0800 TPQBA0 Transmit Pending-Queue Base Address 0 (lower word) 9.3.3 0804 TPQBA1 Transmit Pending-Queue Base Address 1 (upper word) 9.3.3 0808 TPQEA Transmit Pending-Queue End Address 9.3.3

080C TPQWP Transmit Pending-Queue Host Write Pointer 9.3.3

083C TDQRP Transmit Done-Queue Host Read Pointer 9.3.4

0840 TDQWP Transmit Done-Queue DMA Write Pointer 9.3.4 0844 TDQFFT Transmit Done-Queue FIFO Flush Timer 9.3.4 0850 TDBA0 Transmit Descriptor Base Address 0 (lower word) 9.3.2 0854 TDBA1 Transmit Descriptor Base Address 1 (upper word) 9.3.2 0870 TDMACIS Transmit DMA Configuration Indirect Select 9.3.5 0874 TDMAC Transmit DMA Configuration (all 256 channels) 9.3.5 0880 TDMAQ Transmit Queues FIFO Control 9.3.3, 9.3.4

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9.2 Receive Side

9.2.1 Overview

The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps track of and decides where the DMA should place the incoming packet data. There are a set of descriptors that get handed back and forth between the DMA and the host. Through these descriptors the host can inform the DMA where to place the packet data and the DMA can tell the host when the data is ready to be processed.

The operation of the receive DMA has three main areas, as shown in Figure 9-1, Figure 9-2, and

Table 9-B. The host writes to the free-queue descriptors informing the DMA where it can place the

incoming packet data. Associated with each free data buffer location is a free packet descriptor where the DMA can write information to inform the host about the attributes of the packet data (i.e., status information, number of bytes, etc.) that it outputs. To accommodate the various needs of packet data, the host can quantize the free data buffer space into two different buffer sizes. The host sets the size of the buffers through the receive large buffer size (RLBS) and the receive small buffer size (RSBS) registers.

Bit # 7 6 5 4 3 2 1 0 Name LBS7 LBS6 LBS5 LBS4 LBS3 LBS2 LBS1 LBS0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name n/a n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 12/Large Buffer Select Bit (LBS0 to LBS12) 0000000000000 (0000h) = buffer size is 0 Bytes 1111111111100 (1FFCh) = buffer size is 8188 Bytes

Bit # 7 6 5 4 3 2 1 0 Name SBS7 SBS6 SBS5 SBS4 SBS3 SBS2 SBS1 SBS0 Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name n/a n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 12/Small Buffer Select Bit (SBS0 to SBS12) 0000000000000 (0000h) = buffer size is 0 Bytes 1111111111100 (1FFCh) = buffer size is 8188 Bytes

n/a LBS12 LBS11 LBS10 LBS9 LBS8

n/a SBS12 SBS11 SBS10 SBS9 SBS8

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On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers for the incoming packet data on that particular HDLC channel. The host has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer, then, if the incoming packet requires more buffer space, use one or more large buffers for the remainder of the packet. The host selects the option through the size field in the receive configuration RAM (Section 9.2.5). Large buffers are best used for data-intensive, time-insensitive packets like graphics files, whereas small buffers are best used for time-sensitive information like real-time voice.

Table 9-B. Receive DMA Main Operational Areas

DESCRIPTORS FUNCTION SECTION

Packet

Free Queue

Done Queue

A dedicated area of memory that describes the location and attributes of the packet data. A dedicated area of memory that the host writes to inform the DMA where to store incoming packet data. A dedicated area of memory that the DMA writes to inform the host that the packet data is ready for processing.

9.2.2

9.2.3

9.2.4

The done-queue descriptors contain information that the DMA wishes to pass to the host. Through the done-queue descriptors, the DMA informs the host about the incoming packet data and where to find the packet descriptors that it has written into main memory. Each completed descriptor contains the starting address of the data buffer where the packet data is stored.

If enabled, the DMA can burst read the free-queue descriptors and burst write the done-queue descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time critical functions. See Sections 9.2.3 and 9.2.4 for more details about this feature.

Receive DMA Actions

A typical scenario for the receive DMA is as follows:

1) The receive DMA gets a request from the receive FIFO that it has packet data that needs to be sent to

the PCI bus.

2) The receive DMA determines whether the incoming packet data should be stored in a large buffer or

a small buffer.

3) The receive DMA then reads a free-queue descriptor (either by reading a single descriptor or a burst

of descriptors), indicating where, in main memory, there exists some free data buffer space and where the associated free packet descriptor resides.

4) The receive DMA starts storing packet data in the previously free buffer data space by writing it out

through the PCI bus.

5) When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it

can calculate this), it then reads another free-queue descriptor to find another free data buffer and packet descriptor location.

6) The receive DMA then writes the previous packet descriptor and creates a linked list by placing the

current descriptor in the next descriptor pointer field; it then starts filling the new buffer location.

Figure 9-1

provides an example of packet descriptors being link listed together (see channel 2).

7) This continues until the entire packet data is stored.

8) The receive DMA either waits until a packet has been completely received or until a programmable

number (from 1 to 7) of data buffers have been filled before writing the done-queue descriptor, which indicates to the host that packet data is ready for processing.

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Host Actions

The host typically handles the receive DMA as follows:

1) The host is always trying to make free data buffer space available and therefore tries to fill the free-

queue descriptor.

2) The host either polls, or is interrupted, when some incoming packet data is ready for processing.

3) The host then reads the done-queue descriptor circular queue to find out which channel has data

available, what the status is, and where the receive packet descriptor is located.

4) The host then reads the receive packet descriptor and begins processing the data.

5) The host then reads the next descriptor pointer in the link-listed chain and continues this process

until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been reached.

6) The host then checks the done-queue descriptor circular queue to see if any more data buffers are

ready for processing.

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Figure 9-1. Receive DMA Operation

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00h

08h

10h

Free Queue Descriptors

(circular queue)

Free Data Buffer Address

unused

Free Data Buffer Address

unused

Free Data Buffer Address

unused Free Desc. Ptr.

Free Desc. Ptr.

Open Descriptor Space Available for Use by the DMA

Free Data Buffer (up to 8191 bytes)

Open Descriptor Space Available for Use by the DMA

Free Data Buffer (up to 8191 bytes)

00h

04h

08h

0Ch

Done Queue Descriptors

(circular queue)

Status CH #5 Desc. Ptr.

EOF

Status CH #2 Desc. Ptr.

EOF

Status CH #9 Desc. Ptr.

EOF

Status CH # Desc. Ptr.

EOF

Data Buffer Address

Status

# Bytes Next Desc. Ptr.

Timestamp CH #2

Unused

Data Buffer Address

Status # Bytes Next Desc. Ptr.

Timestamp CH #5

Free Packet Descriptors & Data Buffers

Used Packet Descriptors & Data Buffers

First Filled Data Buffer for Channel 2

Single Filled Data Buffer for Channel 5

dmarbd

Data Buffer Address

Status # Bytes Next Desc. Ptr.

Timestamp CH #2

Data Buffer Address

Status # Bytes Next Desc. Ptr.

Timestamp CH #2

Data Buffer Address

Status # Bytes Next Desc. Ptr.

Timestamp CH #9

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Second Filled Data Buffer for Channel 2

Last Filled Data Buffer for Channel 2

Single Filled Data Buffer for Channel 9

Figure 9-2. Receive DMA Memory Organization

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Internal CHEATEAU Registers

Free-Queue Base Address (32)

Free-Queue Large Buffer Host Write Pointer (16)

Free-Queue Large Buffer DMA Read Pointer (16)

Free-Queue Small Buffer Start Address (16)

Free-Queue Small Buffer Host Write Pointer (16)

Free-Queue Small Buffer DMA Read Pointer (16)

Free-Queue End Address (16)

Main Off-Board Memory (32-Bit Address Space)

Free Data Buffer Space

Used Data Buffer Space

Receive Free-Queue Descriptors:

Contains 32-Bit Addresses for Free Data

Buffers and their Associated

Free Packet Descriptors

Up to 64k Dual dwords

Free-Queue Descriptors Allowed

Done-Queue Base Address (32)

Done-Queue DMA Write Pointer (16)

Done-Queue Host Read Pointer (16)

Done-Queue End Address (16)

Descriptor Base Address (32)

Receive Done-Queue Descriptors:

Contains Index Pointers to

Used Packet Descriptors

Up to 64k dwords Done Queue

Descriptors Allowed

Receive Packet Descriptors:

Contains 32-Bit Addresses

to Free Buffer as well as

Status

Links to Other Packet Descriptors

Control Information and

Up to 64k Quad dwords

Descriptors Allowed

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9.2.2 Packet Descriptors

A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed anywhere in the 32-bit address space through the receive descriptor base address (Table 9-C). A data buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a contiguous section of main memory. The host can set two different data buffer sizes through the receive large buffer size (RLBS) and the receive small buffer size (RSBS) registers (Section 9.2.1). If an incoming packet requires more space than the data buffer allows, packet descriptors are link-listed together by the DMA to provide a chain of data buffers. Figure 9-3 shows an example of how three descriptors were linked together for an incoming packet on HDLC channel 2. Figure 9-2 shows a similar example. Channel 9 only required a single data buffer and therefore only one packet descriptor was used.

Packet descriptors can be either free (available for use by the DMA) or used (currently contain data that needs to be processed by the host). The free-queue descriptors point to the free-packet descriptors. The done-queue descriptors point to the used-packet descriptors.

Table 9-C. Receive Descriptor Address Storage

Receive Descriptor Base Address 0 (lower word) RDBA0 0750h Receive Descriptor Base Address 1 (upper word) RDBA1 0754h

Figure 9-3. Receive Descriptor Example

Base + 00h

Free-Queue Descriptor Address

Done-Queue Descriptor Pointe

Maximum of 65,536 Descriptors

Base + 10h

Base + 20h

Base + 30h

Base + 40h

Base + 50h

Base + 60h

Base + 70h

Base + 80h

Base + FFFD0h

Base + FFFF0h

Free Descripto

Channel 2 First Buffer Descripto

Channel 9 Single Buffer Descripto

Free Descripto

Channel 2 Second Buffer Descripto

Free Descripto

Channel 2 Last Buffer Descripto

Free Descripto

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Figure 9-4. Receive Packet Descriptors

dword 0

Data Buffer Address (32)

dword 1

BUFS (3) Byte Count (13) Next Descriptor Pointer (16)

dword 2

Timestamp (24) 00b HDLC CH#(8)

dword 3

Note: The organization of the receive descriptor is not affected by the enabling of Big Endian.

dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated with this receives descriptor.

dword 1; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of the next descriptor in the chain. Only valid if buffer status = 001 or 010. Note: This is an index, not absolute address.

dword 1; Bits 16 to 28/Byte Count. Number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFFh = 8188 Bytes).

dword 1; Bits 29 to 31/Buffer Status. Must be one of the three states listed below. 001 = first buffer of a multiple buffer packet 010 = middle buffer of a multiple buffer packet 100 = last buffer of a multiple or single buffer packet (equivalent to EOF)

dword 2; Bits 0 to 7/HDLC Channel Number. HDLC channel number, which can be from 1 to 256. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256

dword 2; Bits 8 to 31/Timestamp. When each descriptor is written into memory by the DMA, this 24-bit timestamp is provided to keep track of packet arrival times. The timestamp is based on the PCLK frequency divided by 16. For a 33MHz PCLK, the timestamp increments every 485ns and rolls over every 8.13 seconds. For a 24MHz clock, the timestamp increments every 640ns and rolls over every 10.7 seconds. The host can calculate the difference in packets’ arrival times by knowing the PCLK frequency and then taking the difference in timestamp readings between consecutive packet descriptors.

dword 3; Bits 0 to 31/Unused. Not written to by the DMA. Can be used by the host. Application Note: dword 3 is used by the transmit DMA and, in store and forward applications, the receive and transmit packet descriptors have been designed to eliminate the need for the host to groom the descriptors before transmission. In these type of applications, the host should not use dword 3 of the receive packet descriptor.

unused (32)

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9.2.3 Free Queue

The host writes the 32-bit addresses of the available (free) data buffers and their associated packet descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of the associated receive packet descriptor.

Figure 9-5. Receive Free-Queue Descriptor

dword 0

Free Data Buffer Address (32)

dword 1

Unused (16) Free Packet Descriptor Pointer (16)

Note: The organization of the free queue is not affected by the enabling of Big Endian.

dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of a free data buffer.

dword 1; Bits 0 to 15/Free Packet Descriptor Pointer. This 16-bit value is the offset from the receive descriptor

base address of the free descriptor space associated with the free data buffer in dword 0. Note: This is an index, not an absolute address.

dword 1; Bits 16 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the receive DMA.

The receive DMA reads from the receive free-queue descriptor circular queue which data buffers and their associated descriptors are available for use by the DMA.

The receive free-queue descriptor is actually a set of two circular queues (Figure 9-6). There is one circular queue that indicates where free large buffers and their associated free descriptors exist. There is another circular queue that indicates where free small buffers and their associated free descriptors exist.

Large and Small Buffer Size Handling

Through the receive configuration-RAM buffer-size field, the DMA knows for a particular HDLC channel whether the incoming packets should be stored in the large or the small free data buffers. The host informs the DMA of the size of both the large and small buffers through the receive large and small buffer size (RLBS/RSBS) registers. For example, when the DMA knows that data is ready to be written onto the PCI bus, it checks to see if the data is to be sent to a large buffer or a small buffer, and then it goes to the appropriate free-queue descriptor and pulls the next available free buffer address and free descriptor pointer. If the host wishes to have only one buffer size, then the receive free queue smallbuffer start address is set equal to the receive free-queue end address. In the receive configuration RAM, none of the active HDLC channels are configured for the small buffer size.

There are a set of internal addresses within the device to keep track of the addresses of the dual circular queues in the receive free queue. These are accessed by the host and the DMA. On initialization, the host configures all of the registers shown in Table 9-E the read pointers and the host only writes to the write pointers.

. After initialization, the DMA only writes to (changes)

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Empty Case

The receive free queue is considered empty when the read and write pointers are identical.

Receive Free-Queue Empty State

empty descriptor empty descriptor empty descriptor

read pointer > empty descriptor < write pointer

empty descriptor empty descriptor empty descriptor

Full Case

The receive free queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty.

Receive Free-Queue Full State

valid descriptor valid descriptor empty descriptor < write pointer read pointer > valid descriptor valid descriptor valid descriptor valid descriptor

Table 9-D describes how to calculate the absolute 32-bit address of the read and write pointers for the

receive free queue.

Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation

BUFFER ALGORITHM

Absolute Address = Free Queue Base + Write Pointer x 8

Large

Absolute Address = Free Queue Base + Read Pointer x 8

Absolute Address = Free Queue Base + Small Buffer Start x 8 + Write Pointer x 8

Small

Absolute Address = Free Queue Base + Small Buffer Start x 8 + Read Pointer x 8

Table 9-E. Receive Free-Queue Internal Address Storage

Receive Free-Queue Base Address 0 (lower word) RFQBA0 0700h Receive Free-Queue Base Address 1 (upper word) RFQBA1 0704h Receive Free-Queue Large Buffer Host Write Pointer RFQLBWP 0710h Receive Free-Queue Large Buffer DMA Read Pointer RFQLBRP 0718h Receive Free-Queue Small Buffer Start Address RFQSBSA 070Ch Receive Free-Queue Small Buffer Host Write Pointer RFQSBWP 0714h Receive Free-Queue Small Buffer DMA Read Pointer RFQSBRP 071Ch Receive Free-Queue End Address RFQEA 0708h

Note: Both RFQSBSA and RFQEA are not absolute addresses, i.e., the absolute end address is “Base + RFQEA x 8.”

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Figure 9-6. Receive Free-Queue Structure

Base + 00h

Free-Queue Large Buffe Host Write Pointe

Base + 08h

Base + 10h

Base + 18h

Free-Queue Large Buffe DMA Read Pointe

Base + 20h

Free-Queue Small Buffe Start Address

Free-Queue Small Buffe Host Write Pointe

Free-Queue Small Buffe DMA Read Pointe

Maximum of 65,536 Free-Queue Descriptors

Base + End Address

Once the receive DMA is activated (by setting the RDE control bit in the master configuration register, see Section 5

), it can begin reading data out of the free queue. It knows where to read data out of the free queue by reading the read pointer and adding it to the base address to obtain the actual 32-bit address. Once the DMA has read the free queue, it increments the read pointer by two dwords. A check must be made to ensure the incremented address does not equal or exceed either the receive free-queue smallbuffer start address (in the case of the large buffer circular queue) or the receive free-queue end address (in the case of the small buffer circular queue). If the incremented address does equal or exceed either of these addresses, the incremented read pointer is set equal to 0000h.

Host Readied

Free-Queue Descripto

DMA Acquired

Free-Queue Descripto

DMA Acquired

Free-Queue Descripto

DMA Acquired

Free-Queue Descripto

Host Readied

Free-Queue Descripto

Host Readied

Free-Queue Descripto

Host Readied

Free-Queue Descripto

Host Readied

Free Queue Descripto

DMA Acquired

Free-Queue Descripto

DMA Acquired

Free-Queue Descripto

DMA Acquired

Free-Queue Descripto

Host Readied

Free-Queue Descripto

Host Readied

Free-Queue Descripto

Large Buffe Circula Queue

Small Buffe Circula Queue

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Status/Interrupts

On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). The DMA also checks the receive free-queue large-buffer host write pointer and the receive free-queue small-buffer host write pointer to ensure that an underflow does not occur. If it does occur, the DMA sets either the status bit for receive DMA large buffer read error (RLBRE) or the status bit for receive DMA small buffer read error (RSBRE) in the status register for DMA (SDMA), and it does not read the free queue nor does it increment the read pointer. In such a scenario, the receive FIFO can overflow if the host does not provide free-queue descriptors. Each of the status bits can also (if enabled) cause an hardware interrupt to occur. See Section 5 for more details.

Free-Queue Burst Reading

The DMA has the ability to read the free queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can grab messages from the free queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions.

An internal FIFO stores up to 16 free-queue descriptors (32 dwords, as each descriptor occupies two dwords). The free queue can either opeate in dual or singular circular queue mode. It can be divided into large buffer and small buffer. The LBSA (large buffer starting address) and the LBEA (large buffer ending address) form the large buffer queue, and the SBSA (small buffer starting address) and the RFQEA (receive free-queue end address) form the small buffer queue. When the SBSA is not equal to and greater than the RFQEA, the free queue is set up in a dual circular mode. If the SBSA is equal to the FRQEA, the free queue is operating in a single queue mode. When the free queue is operated as a dual circular queue supporting both large and small buffers, then the FIFO is cut into two 8-message FIFOs. If the free queue is operated as a single circular queu supporting only the large buffers, then the FIFO is set up as a single 16-descriptor FIFO. The host must configure the free-queue FIFO for proper operation through the receive DMA queues control (RDMAQ) register (see the following).

When enabled through the receive free-queue FIFO-enable (RFQFE) bit, the free-queue FIFO does not read the free queue until it reaches the low watermark. When the FIFO reaches the low watermark (which is two descriptors in the dual mode or four descriptors in the single mode), it attempts to fill the FIFO with additional descriptors by burst reading the free queue. Before it reads the free queue, it checks (by examining the receive free-queue host write pointer) to ensure the free queue contains enough descriptors to fill the free-queue FIFO. If the free queue does not have enough descriptors to fill the FIFO, it only reads enough to keep from underflowing the free queue. If the FIFO detects that there are no free-queue descriptors available for it to read, then it sets either the status bit for the receive DMA large buffer read error (RLBRE) or the status bit for the receive DMA small buffer read error (RSBRE) in the status register for DMA (SDMA); it does not read the free queue nor does it increment the read pointer. In such a scenario, the receive FIFO can overflow if the host does not provide free-queue descriptors. If the free-queue FIFO can read descriptors from the free queue, it burst reads them, increments the read pointer, and sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for the receive DMA small buffer read (RSBR) in the status register for DMA (SDMA). See Section 5 for more details on status bits.

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Bit # 7 6 5 4 3 2 1 0 Name n/a n/a RDQF RDQFE RFQSF RFQLF n/a RFQFE Default 0 0 0 0 0 0 0 0

Bit # 15 14 13 12 11 10 9 8 Name n/a Default 0 0 0 0 0 0 0 0

Note: Bits that are underlined are read-only; all other bits are read-write.

n/a n/a n/a n/a RDQT2 RDQT1 RDQT0

Bit 0/Receive Free-Queue FIFO Enable (RFQFE). To enable the DMA to burst read descriptors from the free queue, this bit must be set to 1. If this bit is set to 0, descriptors are read one at a time. 0 = free-queue burst read disabled 1 = free-queue burst read enabled

Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). When this bit is set to 1, the internal large buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed

Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). When this bit is set to 1, the internal small buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for proper operation. 0 = FIFO in normal operation 1 = FIFO is flushed

Bit 4/Receive Done-Queue FIFO Enable (RDQFE). See Section 9.2.4

for details.

Bit 5/Receive Done-Queue FIFO Flush (RDQF). See Section 9.2.4

for details.

Bits 8 to 10/Receive Done-Queue Status Bit Threshold Setting (RDQT0 to RDQT2). See Section 9.2.4

for

details.

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9.2.4 Done Queue

The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the associated packet descriptor with all the necessary information. The descriptor location is indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the exact 32-bit address of the associated receive descriptor.

Figure 9-7. Receive Done-Queue Descriptor

dword 0

V EOF Status(3) BUFCNT(3) HDLC CH#(8) Descriptor Pointer (16)

Note 1: The organization of the done queue is not affected by the enabling of Big Endian. Note 2: Descriptor pointer is an index, not an absolute address.

dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base address of a receive packet descriptor that has been readied by the DMA and is available for the host to begin processing. Note: This is an index, not an absolute address.

dword 0; Bits 16 to 21/HDLC Channel Number. This is an HDLC channel number, which can be from 1 to

40. 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256

dword 0; Bits 24 to 26/Buffer Count (BUFCNT). If an HDLC channel has been configured to only write to the done queue after a packet has been completely received (i.e., the threshold field in the receive DMA configuration RAM is set to 000), then BUFCNT is always set to 000. If the HDLC channel has been configured through the threshold field to write to the done queue after a programmable number of buffers (from 1 to 7) has been filled, then BUFCNT corresponds to the number of buffers that have been written to host memory. The BUFCNT is less than the threshold field value when the incoming packet does not require the number of buffers specified in the threshold field. 000 = indicates that a complete packet has been received (only used when threshold = 000) 001 = 1 buffer has been filled 010 = 2 buffers have been filled 111 = 7 buffers have been filled

dword 0; Bits 27 to 29/Packet Status. These three bits report the final status of an incoming packet. They are only valid when the EOF bit is set to 1 (EOF = 1). 000 = no error, valid packet received 001 = receive FIFO overflow (remainder of the packet discarded) 010 = CRC checksum error 011 = HDLC frame abort sequence detected (remainder of the packet discarded) 100 = nonaligned byte count error (not an integral number of bytes) 101 = long frame abort (max packet length exceeded; remainder of the packet discarded) 110 = PCI abort or parity data error (remainder of the packet discarded) 111 = reserved state (never occurs in normal device operation)

dword 0; Bit 30/End of Frame (EOF). This bit is set to 1 when this receive descriptor is the last one in the current descriptor chain. This indicates that a packet has been fully received or an error has been detected, which has caused a premature termination.

dword 0; Bit 31/Valid Done-Queue Descriptor (V). This bit is set to 0 by the receive DMA. Instead of reading the receive done queue read pointer to locate completed done-queue descriptors, the host can use this bit, since the DMA sets the bit to 0 when it is written into the queue. If the latter scheme is used, the host must set this bit to 1 when the done queue descriptor is read.

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The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing.

The receive done queue is circular. A set of internal addresses within the device that are accessed by the host and the DMA keep track of the queue’s addresses. On initialization, the host configures all of the registers, as shown in Table 9-F. After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the read pointer.

Empty Case

The receive done queue is considered empty when the read and write pointers are identical.

Receive Done-Queue Empty State

empty descriptor empty descriptor empty descriptor

read pointer > empty descriptor < write pointer empty descriptor empty descriptor empty descriptor

Full Case

The receive done queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty.

Receive Done-Queue Full State

valid descriptor valid descriptor empty descriptor < write pointer

read pointer > valid descriptor valid descriptor valid descriptor valid descriptor

Table 9-F. Receive Done-Queue Internal Address Storage

Receive Done-Queue Base Address 0 (lower word) RDQBA0 0730h Receive Done-Queue Base Address 1 (upper word) RDQBA1 0734h Receive Done-Queue DMA Write Pointer RDQWP 0740h Receive Done-Queue Host Read Pointer RDQRP 073Ch Receive Done-Queue End Address RDQEA 0738h Receive Done-Queue FIFO Flush Timer RDQFFT 0744h

Note: Receive done-queue end address is not an absolute address. The absolute end address is “Base + RDQEA x 4.”

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Figure 9-8. Receive Done-Queue Structure

Base + 00h

Base + 04h

Done-Queue DMA Write Pointe

Base + 08h

Base + 0Ch

Base + 10h

Done-Queue Host Read Pointe

Base + 14h

Maximum of 65,536

Done-Queue Descriptors

Base + End Address

Once the receive DMA is activated (through the RDE control bit in the master configuration register, see Section 5

), it can begin writing data to the done queue. It knows where to write data into the done queue by reading the write pointer and adding it to the base address to obtain the actual 32-bit address. Once the DMA has written to the done queue, it increments the write pointer by one dword. A check must be made to ensure the incremented address does not exceed the receive done queue end address. If the incremented address exceeds this address, the incremented write pointer is set equal to 0000h (i.e., the base address).

Status Bits/Interrupts

On writes to the done queue by the DMA, the DMA sets the status bit for the receive DMA done-queue write (RDQW) in the SDMA. The host can configure the DMA to either set this status bit on each write to the done queue or only after multiple (from 2 to 128) writes. The host controls this by setting the RDQT0 to RDQT2 bits in the receive DMA queues control (RDMAQ) register. See the description of the RDMAQ register at the end of Section 9.2.4

for more details. The DMA also checks the receive done-queue host read pointer to ensure an overflow does not occur. If this does occur, the DMA then sets the status bit for the receive DMA done-queue write error (RDQWE) in the status register for DMA (SDMA), and it does not write to the done queue nor does it increment the write pointer. In such a scenario, packets can be lost and unrecoverable. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 5 for more details.

Buffer Write Threshold Setting

In the DMA configuration RAM (Section 9.2.5

), there is a host-controlled field called “threshold” (bits RDT0 to RDT2) that informs the DMA when it should write to the done queue. The host has the option to have the DMA place information in the done queue after a programmable number (from 1 to 7) data

DMA Readied

Done-Queue Descripto

DMA Readied

Done-Queue Descripto

Host Processed

Done-Queue Descripto

Host Processed

Done-Queue Descripto

Host Processed

Done-Queue Descripto

DMA Readied

Done-Queue Descripto

DMA Readied

Done-Queue Descripto

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buffers have been filled or wait until the completed packet data has been written. The DMA always writes to the done queue when it has finished receiving a packet, even if the threshold has not been met.

Done-Queue Burst Writing

The DMA has the ability to write to the done queue in bursts, which allows for a more efficient use of the PCI bus. The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions.

An internal FIFO stores up to eight done-queue descriptors (8 dwords as each descriptor occupies one dword). The host must configure the FIFO for proper operation through the receive DMA queues-control (RDMAQ) register (see the following).

When enabled through the receive done-queue FIFO-enable (RDQFE) bit, the done-queue FIFO does not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to the done queue. Before it writes to the done queue, it checks (by examining the receive done-queue host read pointer) to ensure the done queue has enough room to empty the done-queue FIFO. If the done queue does not have enough room, then it only burst writes enough descriptors to keep from overflowing the done queue. If the FIFO detects that there is no room for any descriptors to be written, it sets the status bit for the receive DMA done-queue write error (RDQWE) in the status register for DMA (SDMA). It does not write to the done queue nor does it increment the write pointer. In such a scenario, packets can be lost and unrecoverable. If the done-queue FIFO can write descriptors to the done queue, it burst writes them, increments the write pointer, and sets the status bit for the receive DMA done-queue write (RDQW) in the status register for DMA (SDMA). See Section 5 for more details on status bits.

Done-Queue FIFO Flush Timer

To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the DMA uses the receive done-queue FIFO flush timer (RDQFFT) to determine the maximum wait time between writes. The RDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256. It is only monitored by the DMA when the receive done-queue FIFO is enabled (RDQFE = 1). For a 33MHz PCLK, the timer is decremented every 7.76ms. For a 25MHz clock, it is decremented every 10.24µs. Each time the DMA writes to the done queue it resets the timer to the count placed into it by the host. On initialization, the host sets a value into the RDQFFT that indicates the maximum time the DMA should wait in between writes to the done queue. For example, with a PCLK of 33MHz, the range of wait times is from 7.8ms (RDQFFT = 0001h) to 508ms (RDQFFT = FFFFh). With a PCLK of 25MHz, the wait times range from 10.2µs (RDQFFT = 0001h) to 671ms (RDQFFT = FFFFh).

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