The DS2705 provides the master side of a Secure
Hash Algorithm (SHA) based token authentication
scheme. Hardware-based SHA authentication allows
for security without the added cost and complexity of
a microprocessor-based system. Batteries and other
accessories are authenticated using a single contact
through the Dallas 1-WireÒ interface. Authentication
is performed on demand or automatically, with the
pass/fail status reported on open-drain output pins to
signal the charge system and/or drive LEDs. The
DS2705 stores a predetermined challenge-andresponse pair in nonvolatile (NV) EEPROM. The
DS2705 works in conjunction with Dallas Battery
Management SHA-1 token products, including the
DS2703 and DS2704.
APPLICATIONS
Digital Cameras
Portable DVD and Media Players
Cradle and Accessory Chargers
Cell Phones/Smartphones
APPLICATION EXAMPLE
PIN CONFIGURATION
HAL
2
3
VSS
MAX
VDD
7
MDQ
6
SDQ
VPP
FEATURES
§ Initiates Challenge-and-Response
Authentication based on the SHA-1 Algorithm
§ Dallas 1-Wire Master/Slave Interface Operates
at Standard and Overdrive Speeds
§ Input and Output pins for Initiating Challenge
and Reporting Authentication Pass/Fail
§ Programmable Configuration
§ Operates from 2.5V to 5.5V Supply
§ Tiny mMAX Package (Pb-Free)
ORDERING INFORMATION
PART TEMP RANGE MARKING PIN-PACKAGE
DS2705U+
DS2705U+/T&R
+ Denotes lead-free package.
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 18 050506
-40°C to +85°C
-40°C to +85°C
DS2705
DS2705 DS2705U+ in Tape-and-Reel
mMAX
DS2705: SHA-1 Authentication Master
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (except VPP), Relative to VSS -0.3V to +5.5V
Voltage Range on V
Pin, Relative to VSS -0.3V to +18V
PP
Continuous Source Current, MDQ 20mA
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
DC ELECTRICAL CHARACTERISTICS
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Active mode,
MDQ low, I
Active mode,
MDQ idle, I
O_MDQ
O_MDQ
Sleep mode, I
= 0
= 0
= 0 (Note 2) 1 2
O_MDQ
2.5 mA
90 130
mA
mA
Program pulse (Notes 1, 3) 14.5 15.0 V
(Note 1) 1.8 V
(Note 1) 0.6 V
IOL = 4mA (Note 1) 0.4 V
Supply Current
Programming Voltage: VPP
Input Logic High:
MDQ, SDQ, CHAL
Input Logic Low:
MDQ, SDQ, CHAL
Output Logic Low: MDQ, SDQ V
I
I
I
V
V
V
DD1
DD2
DD3
PP
IH
IL
OL1
Output Logic Low: PASS, FAIL
Pulldown: VPP
Pulldown: SDQ, CHAL I
Pullup: MDQ
V
OL2
I
PD1
PD2
IOH
VOH
IOL = 10mA (Note 1) 0.4 V
300
(Note 5) 0.125
Communication mode
(Note 6)
Computation mode
= 2.0mA (Note 7)
I
OH
0.25 2.5 mA
V
- 0.1
DD
V
mA
mA
Input Capacitance: MDQ, SDQ CIN 60 pF
EEPROM RELIABILITY SPECIFICATION
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM Write Time t
EEPROM Write Endurance N
EEW
EEC
(Note 3) 15 ms
(Notes 3, 4) 1,000 Cycles
2 of 18
DS2705: SHA-1 Authentication Master
AC ELECTRICAL CHARACTERISTICS: MASTER 1-Wire INTERFACE
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STANDARD BUS TIMING
Time Slot t
Recovery Time t
Write-0 Low Time t
Write-1 Low Time t
Read-Data Sample Window t
Reset-Time Low t
Presence-Detect High t
Presence-Detect Low t
OVERDRIVE BUS TIMING
Time Slot t
Recovery Time t
Write-0 Low Time t
Write-1 Low Time t
Read-Data Sample Window t
(Note 10) 90
MSLOT
(Note 10) 7.5 10 12.5
MREC
(Note 10) 88.5
MLOW0
(Note 10) 1.05 1.5 2.25
MLOW1
(Note 10) 4.0 5.5 7.0
MRDV
(Note 10) 510 680 850
MRSTL
(Note 10) 2 75
MPDH
(Note 10) 2 400
MPDL
(Note 10) 12
MSLOT
(Note 10) 1 2 2.5
MREC
(Note 10) 10.5
MLOW0
(Note 10) 0.35 0.5 0.65
MLOW1
(Note 10) 1.1 1.5 1.9
MRDV
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Reset-Time Low t
Presence-Detect High t
Presence-Detect Low t
(Note 10) 53 70 88
MRSTL
(Note 10) 2 7
MPDH
(Note 10) 2 41
MPDL
ms
ms
ms
3 of 18
DS2705: SHA-1 Authentication Master
AC ELECTRICAL CHARACTERISTICS: SLAVE 1-Wire INTERFACE
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STANDARD BUS TIMING
Time Slot t
Recovery Time t
Write-0 Low Time t
Write-1 Low Time t
Read-Data Valid t
Reset-Time High t
Reset-Time Low t
Presence-Detect High t
Presence-Detect Low t
OVERDRIVE BUS TIMING
Time Slot t
Recovery Time t
Write-0 Low Time t
Write-1 Low Time t
60 120
SLOT
1
REC
60 120
LOW0
1 15
LOW1
15
RDV
480
RSTH
480 960
RSTL
15 60
PDH
60 240
PDL
6 16
SLOT
1
REC
6 16
LOW0
1 2
LOW1
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Read-Data Valid t
Reset-Time High t
Reset-Time Low t
Presence-Detect High t
Presence-Detect Low t
2
RDV
48
RSTH
48 80
RSTL
2 6
PDH
8 24
PDL
ms
ms
ms
ms
ms
4 of 18
AC ELECTRICAL CHARACTERISTICS
(2.5V £ VDD £ 5.5V, TA = -20°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DS2705: SHA-1 Authentication Master
Programming Pulse Width t
Programming Pulse Rise Time t
Programming Pulse Fall Time t
Strong Pullup Delay Time t
Strong Pullup Period t
Challenge Delay Time t
Authentication Attempt Time t
FAIL Pin Pulse Frequency
17 ms
PPW
(Note 8) 0.5 5
PPR
(Note 8) 0.5 5
PPF
2 10
SPUD
24 34 48 ms
SPUP
45 65 85 ms
CHD
(Note 9) 61 490 ms
AAT
FOM = 1, 50% duty cycle 1.5 2 2.5 Hz
t
FPF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
All voltages are referenced to V
IDD3 Sleep mode conditions:
CHAL pin inactive OR (CHAL active AND (PAA = 0 AND PPT = 00 AND FOM = 0 AND Initial Authentication sequence
complete))
[Above conditions disable the internal oscillator]
Programming temperature range is T
5 years data retention at 70°C
If CHAL pin left unconnected, CHP bit = 0 required for an authentication attempt to be initiated on power up. See Table 1.
Typical Communication mode MDQ pullup behavior equivalent to 3kW resistor.
Typical Computation mode MDQ pullup behavior approximates a 50W resistor.
Exceeding maximum rise and fall time specifications may affect device reliability.
t
= Retries per Attempt x (264bits x 90ms + 3 x (t
AAT
MAX[7 retries]: 490ms, MIN[no retries]: 61ms with standard timings
1. 1-Wire Master timings based on ±25% clock tolerance from nominal.
2. t
3. t
4. Bus rise time of ~1ms required to settle to logic high by t
[defined in design documentation] = t
RPDT
= t
MPDL-MAX
MRSTH-MIN
.
SS
– t
MPDH-MAX,
= 0°C to 50°C.
A
+ t
+ t
RSTH
MRSTH
) + t
MRSTL
MRSTL
represents the maximum presence pulse low time allowed from the slave.
) = [1 to 8] x (23.7ms + 3.54ms + 34ms)
SPUD
after MDQ released at t
MRDV
MLOW1
PIN DESCRIPTION
PIN
mMAX
TDFN
1 1 CHAL Challenge Strobe Input Pin. Initiates authentication. Active level/edge set by CHP bit.
2 2
3 3
4 4
5 5
6 6 SDQ
7 7 MDQ
8 8
SYMBOL FUNCTION
PASS
FAIL
V
SS
V
PP
Authentication “PASS” Result Open-Drain Output Pin
Authentication “FAIL” Result Open-Drain Output Pin (Programmable As Low Or Pulse)
Supply Return Pin, GND Reference for Logic Signals
EEPROM Programming Voltage Input
Slave Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Bus master must provide a weak pullup.
Master Serial interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps or
143kbps. Provides a weak pullup in communication mode and strong pullup in
computation mode.
V
Supply Input Pin. Bypass to VSS with 0.1mF capacitor.
DD
ms
ms
ms
5 of 18
Figure 1. Block Diagram
DS2705: SHA-1 Authentication Master
VDD
EEPROM
64-bit
Challenge
CHP = 0
160-bit MAC
16-bit
Configuration
Pullup
Control
CHAL
PASS
FAIL
Control FSM
t
+ t
CHD
AAT
VSS
1-Wire
Master /
Slave
MDQ
SDQ
DETAILED DESCRIPTION
The DS2705 orchestrates a challenge/response SHA-1 authentication procedure by accessing a Dallas Battery
Management SHA-1 Token product, such as the DS2703 or DS2704. The remote SHA-1 token is accessed with
the MDQ pin acting as the 1-Wire bus master. The DS2705 issues the appropriate 1-Wire command sequence on
MDQ to write the 64-bit challenge, initiates a SHA-1 computation in the token, and then reads back the 160-bit
MAC result. The DS2705 compares the 160-bit MAC received from the battery token with the preprogrammed
MAC. An exact bit for bit match is required for the authentication to be successful. The result of the operation,
PASS or FAIL, is indicated on active low status output pins which can be used to drive status LEDs and/or enable
cell charging.
The DS2705 can be configured to automatically authenticate by detection of a presence pulse on MDQ or
authentication can be controlled by the state of the CHAL input pin. The DS2705’s SDQ pin is a 1-Wire slave
interface for programming the behavior of the I.C.. All EEPROM values can be permanently locked to prevent
corruption.
Figure 2 shows a example application circuit for a standalone battery charger. The DS2705 is preprogrammed for
automatic authentication on MDQ and also contains a known good challenge/response pair. Programming occurs
during assembly through PCB test points shown on the right side of the circuit. When a battery pack is inserted into
the charger, a presence pulse on MDQ will cause the DS2705 to automatically authenticate the pack. The result of
the authentication will be displayed through the LEDs and the DS2705 will either enable or disable the charging
circuit.
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