Rainbow Electronics DS26503 User Manual
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26503 is a building-integrated timingsupply (BITS) clock-recovery element. The
receiver portion can recover a clock from T1,
E1, and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the
Synchronization Status Message (SSM) can also
be recovered. The transmit portion can directly
interface to T1 or E1 interfaces as well as source
the SSM in T1 and E1 modes. The DS26503 can
translate between any of the supported inbound
synchronization clock rates to any supported
outbound rate. A separate output is provided to
source a 6312kHz clock. The device is
controlled through a parallel, serial, or hardware
controller port.
APPLICATIONS
BITS Timing
Rate Conversion
Basic Transceiver
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS26503L 0°C to +70°C 64 LQFP
DS26503LN -40°C to +85°C 64 LQFP
DS26503
T1/E1/J1 BITS Element
FEATURES
§ G.703 2048kHz Synchronization Interface
Compliant
§ G.703 6312kHz Japanese Synchronization
Interface Compliant
§ Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
§ Interface to CMI-Coded T1/J1 and E1
§ Short- and Long-Haul Line Interface
§ Transmit and Receive T1 and E1 SSM
Messages with Message Validation
§ Crystal-Less Jitter Attenuator with Bypass
Mode
§ Fully Independent Transmit and Receive
Functionality
§ Internal Software-Selectable Receive- and
Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω
§ Monitor Mode for Bridging Applications
§ Accepts 16.384MHz, 8.192MHz, 4.096MHz,
2.048MHz, or 1.544MHz (T1 Only) Master
Clock
§ 8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
§ Serial (SPI) Control Port
§ Hardware Control Mode
§ Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
§ Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V Supply with 5V-Tolerant Inputs and
Outputs
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 070904
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DS26503 T1/E1/J1 BITS Element
TABLE OF CONTENTS
1. FEATURES.......................................................................................................................7
1.1 GENERAL ........................................................................................................................7
1.2 LINE INTERFACE ...............................................................................................................7
1.3 J
1.4 F
1.5 TEST AND DIAGNOSTICS ...................................................................................................8
1.6 CONTROL PORT ...............................................................................................................8
2. SPECIFICATIONS COMPLIANCE ...................................................................................9
3. BLOCK DIAGRAMS .......................................................................................................12
4. PIN FUNCTION DESCRIPTION .....................................................................................15
4.1 TRANSMIT PLL...............................................................................................................15
4.2 TRANSMIT SIDE..............................................................................................................15
4.3 RECEIVE SIDE................................................................................................................16
4.4 CONTROLLER INTERFACE................................................................................................17
4.5 JTAG ...........................................................................................................................21
4.6 LINE INTERFACE .............................................................................................................21
4.7 POWER .........................................................................................................................22
ITTER ATTENUATOR ........................................................................................................7
RAMER/FORMATTER .......................................................................................................8
5. PINOUT...........................................................................................................................23
6. HARDWARE CONTROLLER INTERFACE....................................................................26
6.1 TRANSMIT CLOCK SOURCE .............................................................................................26
6.2 INTERNAL TERMINATION..................................................................................................26
6.3 LINE BUILD-OUT.............................................................................................................27
6.4 RECEIVER OPERATING MODES........................................................................................27
6.5 TRANSMITTER OPERATING MODES ..................................................................................28
6.6 MCLK PRE-SCALER ......................................................................................................28
6.7 OTHER HARDWARE CONTROLLER MODE FEATURES .........................................................29
7. PROCESSOR INTERFACE............................................................................................30
7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION.....................................................................30
7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION .................................................30
7.2.1 Clock Phase and Polarity ................................................................................................... 30
7.2.2 Bit Order............................................................................................................................. 30
7.2.3 Control Byte ....................................................................................................................... 30
7.2.4 Burst Mode......................................................................................................................... 30
7.2.5 Register Writes................................................................................................................... 31
7.2.6 Register Reads ..................................................................................................................31
7.3 REGISTER MAP ..............................................................................................................32
7.3.1 Power-Up Sequence .......................................................................................................... 34
7.3.2 Test Reset Register............................................................................................................ 34
7.3.3 Mode Configuration Register.............................................................................................. 35
7.4 I
7.5 S
NTERRUPT HANDLING ....................................................................................................38
TATUS REGISTERS .......................................................................................................38
7.6 INFORMATION REGISTERS ...............................................................................................39
7.7 I
NTERRUPT INFORMATION REGISTERS ..............................................................................39
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DS26503 T1/E1/J1 BITS Element
8. T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40
8.1 T1 C
ONTROL REGISTERS ...............................................................................................40
9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46
9.1 E1 CONTROL REGISTERS ...............................................................................................46
9.2 E1 I
NFORMATION REGISTERS..........................................................................................48
10. I/O PIN CONFIGURATION OPTIONS ............................................................................52
11. T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................55
11.1 T1 BIT-ORIENTED CODE (BOC) CONTROLLER ................................................................55
11.2 TRANSMIT BOC.............................................................................................................55
11.3 RECEIVE BOC...............................................................................................................56
12. E1 SYNCHRONIZATION STATUS MESSAGE..............................................................64
12.1 S
12.2 A
A/SI BIT ACCESS BASED ON CRC4 MULTIFRAME...........................................................64
LTERNATE SA/SI BIT ACCESS BASED ON DOUBLE-FRAME...............................................74
13. LINE INTERFACE UNIT (LIU) ........................................................................................77
13.1 LIU OPERATION ............................................................................................................78
13.2 LIU RECEIVER ..............................................................................................................78
13.2.1 Receive Level Indicator...................................................................................................... 78
13.2.2 Receive G.703 Section 10 Synchronization Signal............................................................. 79
13.2.3 Monitor Mode ..................................................................................................................... 79
13.3 LIU TRANSMITTER .........................................................................................................79
13.3.1 Transmit Short-Circuit Detector/Limiter............................................................................... 80
13.3.2 Transmit Open-Circuit Detector.......................................................................................... 80
13.3.3 Transmit BPV Error Insertion.............................................................................................. 80
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode) .......................................... 80
13.4 MCLK PRE-SCALER......................................................................................................80
13.5 JITTER ATTENUATOR......................................................................................................80
13.6 CMI (CODE MARK INVERSION) OPTION ...........................................................................81
13.7 LIU CONTROL REGISTERS .............................................................................................82
13.8 R
ECOMMENDED CIRCUITS ..............................................................................................90
13.9 COMPONENT SPECIFICATIONS ........................................................................................92
14. LOOPBACK CONFIGURATION.....................................................................................96
15. 6312KHZ SYNCHRONIZATION INTERFACE................................................................97
15.1 R
15.2 T
ECEIVE 6312KHZ SYNCHRONIZATION INTERFACE OPERATION ........................................97
RANSMIT 6312KHZ SYNCHRONIZATION INTERFACE OPERATION.......................................97
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................98
16.1 INSTRUCTION REGISTER...............................................................................................102
16.2 T
EST REGISTERS.........................................................................................................103
16.3 BOUNDARY SCAN REGISTER.........................................................................................103
16.4 B
16.5 I
YPASS REGISTER ......................................................................................................103
DENTIFICATION REGISTER............................................................................................103
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DS26503 T1/E1/J1 BITS Element
17. FUNCTIONAL TIMING DIAGRAMS .............................................................................106
17.1 P
17.1.1 Parallel Port Mode............................................................................................................ 106
17.1.2 SPI Serial Port Mode........................................................................................................ 106
ROCESSOR INTERFACE ...............................................................................................106
18. OPERATING PARAMETERS.......................................................................................109
19. AC TIMING PARAMETERS AND DIAGRAMS ............................................................111
19.1 MULTIPLEXED BUS.......................................................................................................111
19.2 NONMULTIPLEXED BUS ................................................................................................114
19.3 SERIAL BUS ................................................................................................................117
19.4 RECEIVE SIDE AC CHARACTERISTICS ...........................................................................119
19.5 TRANSMIT SIDE AC CHARACTERISTICS .........................................................................121
20. REVISION HISTORY ....................................................................................................122
21. PACKAGE INFORMATION ..........................................................................................123
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DS26503 T1/E1/J1 BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram..................................................................................................................... 12
Figure 3-2. Loopback Mux Diagram....................................................................................................... 13
Figure 3-3. Transmit PLL Clock Mux Diagram....................................................................................... 13
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 14
Figure 13-1. Basic Network Connection................................................................................................. 77
Figure 13-2. Typical Monitor Application................................................................................................ 79
Figure 13-3. CMI Coding ....................................................................................................................... 81
Figure 13-4. Basic Interface................................................................................................................... 90
Figure 13-5. Protected Interface Using Internal Receive Termination.................................................... 91
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 93
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 93
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 94
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 94
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 95
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 95
Figure 16-1. JTAG Functional Block Diagram........................................................................................ 98
Figure 16-2. TAP Controller State Diagram ......................................................................................... 101
Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0............................................. 106
Figure 17-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0............................................. 106
Figure 17-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1............................................. 106
Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1............................................. 107
Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 107
Figure 17-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 107
Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................. 108
Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................. 108
Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 112
Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 112
Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)................................................................ 113
Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 118
Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 118
Figure 19-10. Receive Timing, T1/E1 .................................................................................................. 120
Figure 19-11. Transmit Timing, T1/E1 ................................................................................................. 122
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DS26503 T1/E1/J1 BITS Element
LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications...................................................................... 9
Table 2-2. E1-Related Telecommunications Specifications ................................................................... 10
Table 5-1. LQFP Pinout......................................................................................................................... 23
Table 6-1. Transmit Clock Source ......................................................................................................... 26
Table 6-2. Internal Termination.............................................................................................................. 26
Table 6-3. E1 Line Build-Out ................................................................................................................. 27
Table 6-4. T1 Line Build-Out.................................................................................................................. 27
Table 6-5. Receive Path Operating Mode.............................................................................................. 27
Table 6-6.Transmit Path Operating Mode.............................................................................................. 28
Table 6-7. MCLK Pre-Scaler for T1 Mode.............................................................................................. 28
Table 6-8. MCLK Pre-Scaler for E1 Mode ............................................................................................. 29
Table 6-9. Other Operational Modes ..................................................................................................... 29
Table 7-1. Port Mode Select.................................................................................................................. 30
Table 7-2. Register Map Sorted By Address.......................................................................................... 32
Table 8-1. T1 Alarm Criteria .................................................................................................................. 45
Table 9-1. E1 Sync/Resync Criteria....................................................................................................... 47
Table 9-2. E1 Alarm Criteria .................................................................................................................. 49
Table 10-1. TS Pin Functions ................................................................................................................ 53
Table 10-2. RLOF Pin Functions ........................................................................................................... 53
Table 11-1. T1 SSM Messages ............................................................................................................. 55
Table 12-1. E1 SSM Messages ............................................................................................................. 64
Table 13-1. Transformer Specifications ................................................................................................. 92
Table 15-1. Specification of 6312kHz Clock Signal at Input Port........................................................... 97
Table 15-2. Specification of 6312kHz Clock Signal at Output Port......................................................... 97
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture................................................................ 102
Table 16-2. ID Code Structure............................................................................................................. 103
Table 16-3. Device ID Codes............................................................................................................... 103
Table 16-4. Boundary Scan Control Bits.............................................................................................. 104
Table 18-1. Thermal Characteristics.................................................................................................... 109
Table 18-2. Theta-JA (q
Table 18-3. Recommended DC Operating Conditions ......................................................................... 109
Table 18-4. Capacitance ..................................................................................................................... 109
Table 18-5. DC Characteristics............................................................................................................ 110
Table 19-1. AC Characteristics, Multiplexed Parallel Port.................................................................... 111
Table 19-2. AC Characteristics, Non-Mux Parallel Port ....................................................................... 114
Table 19-3. AC Characteristics, Serial Bus.......................................................................................... 117
Table 19-4. Receive Side AC Characteristics ...................................................................................... 119
Table 19-5. Transmit Side AC Characteristics ..................................................................................... 121
) vs. Airflow.................................................................................................. 109
JA
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DS26503 T1/E1/J1 BITS Element
1. FEATURES
1.1 General
§ 64-pin, 10mm x 10mm LQFP package
§ 3.3V supply with 5V-tolerant inputs and outputs
§ Evaluation kits
§ IEEE 1149.1 JTAG Boundary Scan
§ Driver source code available from the factory
1.2 Line Interface
§ Requires a single master clock (MCLK) for E1, T1, or J1 operation. Master clock can be
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,
6.176MHz, or 12.352MHz for T1-only operation.
§ Fully software configurable
§ Short- and long-haul applications
§ Automatic receive sensitivity adjustments
§ Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB
for T1 applications
§ Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
§ Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
§ Monitor application gain settings of 20dB, 26dB, and 32dB
§ G.703 receive-synchronization signal mode
§ Flexible transmit-waveform generation
§ T1 DSX-1 line build-outs
§ E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
§ AIS generation independent of loopbacks
§ Alternating ones and zeros generation
§ Square-wave output
§ Open-drain output option
§ Transmitter power-down
§ Transmitter 50mA short-circuit limiter with exceeded indication of current limit
§ Transmit open-circuit-detected indication
1.3 Jitter Attenuator
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use
1.544MHz for T1 operation
§ Can be placed in either the receive or transmit path or disabled
§ Limit trip indication
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1.4 Framer/Formatter
§ Full receive and transmit path transparency
§ T1 framing formats include D4 and ESF
§ E1 framing formats include FAS and CRC4
§ Detailed alarm and status reporting with optional interrupt support
§ RLOF, RLOS, and RAIS alarms interrupt on change of state
§ Japanese J1 support includes:
- Ability to calculate and check CRC6 according to the Japanese standard
- Ability to generate yellow alarm according to the Japanese standard
1.5 Test and Diagnostics
§ Remote and Local Loopback
1.6 Control Port
§ 8-bit parallel or serial control port
§ Multiplexed or nonmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt-driven environments
§ Software access to device ID and silicon revision
§ Software-reset supported with automatic clear on power-up
§ Hardware controller port
§ Hardware reset pin
DS26503 T1/E1/J1 BITS Element
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DS26503 T1/E1/J1 BITS Element
2. SPECIFICATIONS COMPLIANCE
The DS26503 meets all applicable sections of the relevant latest telecommunications specifications. The
following table provides the T1 and E1 specifications and relevant sections that are applicable to the
DS26503.
Table 2-1. T1-Related Telecommunications Specifications
ANSI T1.102- Digital Hierarchy Electrical Interface
AMI Coding
B8ZS Substitution Definition
DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6V peak; power level
between 12.6dBm to 17.9dBm; the T1 pulse mask is provided that we comply. DSX-1 for cross connects
if the return loss is greater than -26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cables of
1000 feet.
ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition
ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100W. Pulse shape and template compliance
according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB, and -15dB. Line rate is ±32ppm. Pulse
Amplitude is 2.4 to 3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26503 will function with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different --- specifically at Times 0.61,
-0.27, -34 and 0.77. The DS26524 is complaint to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter the G.823.
(ANSI) “Digital Hierarchy – Electrical Interfaces”
(ANSI) “Digital Hierarchy – Formats Specification”
(ANSI) “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces – DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended
Super frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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DS26503 T1/E1/J1 BITS Element
Table 2-2. E1-Related Telecommunications Specifications
ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75W coax or 120W twisted
pair; peak-to-peak space voltage is ±0.237V; nominal pulse width is 244ns.
Return loss 51Hz to 102Hz is 6dB; 102Hz to 3072Hz is 8dB; 2048Hz to 3072Hz is 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse template for E1 is defined in G.703.
ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps
The peak-to-peak jitter at 2048kbps has to be less than 0.05 UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps
The DS26503 jitter attenuator is complaint with Jitter transfer curve for sinusoidal jitter input.
ITUT G.772
This specification provides the method for using receiver for transceiver 0 as a monitor for the remainder
of the seven transmitter/receiver combinations.
ITUT G.775
A LOS detection criterion is defined.
ITUT G.823 The control of jitter and wander within digital networks, which are based on 2.048kbps
hierarchy
G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz,
and 100kHz.
ETSI 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter then G.823.
(ITU) “Synchronous Frame Structures used at 1544, 6312k, 2048, 8488, and 44,736kbps Hierarchical
Levels”
(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame
Structures Defined in Recommendation G.704”
(ITU) “Characteristics of primary PCM Multiplex Equipment Operating at 2048kbps”
(ITU) Characteristics of a synchronous digital multiplex equipment operating at 2048kbps”
(ITU) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria”
(ITU) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps
Hierarchy”
(ITU) “Primary Rate User-Network Interface – Layer 1 Specification”
(ITU) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”
(ITU) “In-service code violation monitors for digital systems”
(ETSI) “Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part
1/ Layer 1 specification”
(ETSI) “Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital
interfaces for equipment using the 2048kbps-based plesiochronous or synchronous digital hierarchies”
(ETSI) “Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate”
(ETSI) “Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment
to connect to an ISDN using ISDN primary rate access”
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DS26503 T1/E1/J1 BITS Element
Table 2-3. E1-Related Telecommunications Specifications (continued)
(ETSI) “Business Telecommunications (BT); Open Network Provision (ONP) technical requirements;
2048lkbps digital unstructured leased lines (D2048U) attachment requirements for terminal equipment
interface”
(ETSI) “Business Telecommunications (BTC); 2048kbps digital structured leased lines (D2048S);
Attachment requirements for terminal equipment interface”
(ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736kbps Hierarchical
Levels”
(ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame
Structures Defined in Recommendation G.704”
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3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
MCLK
MASTER CLOCK
JA CLOCK
DS26503 T1/E1/J1 BITS Element
DS26503
RCLK
RTIP
RRING
RLOS
RAIS
TTIP
RX
RX
LIU
LIU
TX
LIU
CLOCK
+ DATA
- DATA
L
O
C
A
L
L
ATTENUATOR
O
O
ASSIGNED TO
P
TRANSMIT PATH
B
OR DISABLED
A
C
K
M
U
X
JA
JA
ENABLED
ENABLED
AND IN RX
AND IN RX
PATH
PATH
JITTER
CAN BE
RECEIVE OR
JA
ENABLED
AND IN TX
PATH
R
E
M
O
T
E
L
O
O
P
B
A
C
K
M
U
X
PLL
CLOCK
MUX
TX CLOCK
+ DATA
- DATA
T1/E1 SSM
FRAMER
T1/E1 SSM
FORMATTER
LOF_CCE
RSER
RS
TCLK
PLL_OUT
TSER
TS
JTAG PORT
JTAG PORTJTAG PORTJTAG PORT
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
JTDOJTDIJTCLKJTMS JTRST BIS1 BIS0
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
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TSTRST
Figure 3-2. Loopback Mux Diagram
FROM RX
LIU
TO TX
LIU
CLOCK
+ DATA
- DATA
CLOCK
+ DATA
- DATA
ATTENUATOR
ENABLED AND
ATTENUATOR
ENABLED AND
REMOTE
LOOPBACK
(LBCR.4)
JITTER
IN RX PATH
LOCAL
LOOPBACK
(LBCR.3)
JITTER
IN TX PATH
DS26503 T1/E1/J1 BITS Element
RCLK
+ DATA
TO RX
FRAMER
- DATA
TX CLOCK
+ DATA
FROM TX
FORMATTER
- DATA
Figure 3-3. Transmit PLL Clock Mux Diagram
TPCR.2
RECOVERED CLOCK
TCLK PIN
JA CLOCK
(HARDWARE MODE PIN NAME)
TPCR.3
TPCR.4
IN
SEL
TX PLL
OUTPUT = 1.544MHz,
2.048MHz, 6.312MHz
TPCR.6
TPCR.7
OUT
SEL
TPCR.0
(TCSS0)
TPCR.1
(TCSS1)
TPCR.5
PLL_OUT PIN
TX CLOCK
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Figure 3-4. Master Clock PLL Diagram
MCLK PIN
PRE-SCALER
DIVIDE BY 1, 2, 4,
OR 8
DS26503 T1/E1/J1 BITS Element
LIC4.6
(MPS0)
LIC4.7
(MPS1)
X12,X16
MULTIPLIER
PLL
TO CLOCK AND DATA
RECOVERY ENGINE IN
RECEIVE LIU
2.048MHz to
1.544MHz PLL
(HARDWARE MODE PIN NAME)
JA CLOCK
LIC2.3
(JACKS)
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4. PIN FUNCTION DESCRIPTION
4.1 Transmit PLL
NAME TYPE FUNCTION
PLL_OUT O
Transmit PLL Output. 1544kHz, 2048kHz, 64kHz, or 6312kHz output from
the internal TX PLL.
Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz
TCLK I
primary clock. May be selected by the TX PLL mux to provide a clock to the
transmit section.
4.2 Transmit Side
NAME TYPE FUNCTION
TSER I
TS I/O
TCLKO O
TPOSO O
TNEGO O
Transmit Serial Data. Source of transmit data sampled on the falling edge of
the selected transmit clock.
TSYNC. When in “input” mode, a pulse at this pin will establish either frame
or multiframe boundaries for the transmit side. In output mode, the pin can be
programmed to output a frame or multiframe sync pulse useful for aligning
data.
Transmit Clock Output. Buffered clock that is used to clock data through the
transmit-side formatter (i.e., either TCLK or RCLK).
Transmit Positive-Data Output. In T1 or E1 mode, updated on the rising
edge of TCLKO with the bipolar data out of the transmit-side formatter. Can
be programmed to source NRZ data via the output-data format (IOCR1.0)
control bit. In 6312 mode, this pin is low.
Transmit Negative-Data Output. In T1 or E1 mode, updated on the rising
edge of TCLKO with the bipolar data out of the transmit-side formatter. In
6312 mode, this pin is low.
DS26503 T1/E1/J1 BITS Element
15 of 123
4.3 Receive Side
NAME TYPE FUNCTION
RCLK O
RS O
RSER O
RLOF O
RLOS O
Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), or 6312 kHz
(G.703 Synchronization Interface).
Receive Sync
T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that
identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1)
boundaries. If set to output frame boundaries, then through IOCR1.6, RS can
also be set to output double-wide pulses on signaling frames in T1 mode.
6312K Mode: This pin will be in a high-impedance state.
Receive Serial Data
T1/E1 Mode: This is the received NRZ serial data updated on rising edges of
RCLK.
6312K Mode: This pin will be in a high-impedance state.
Receive Loss Of Frame. This output can be configured to be a Loss Of
Transmit Clock indicator via IOCR.4 when operating in T1 or E1 mode.
T1/E1 Mode: Set when the receive synchronizer is searching for frame
alignment (RLOF mode), or set when the signal at the TCLK pin has not
transitioned for approximately 15 periods of the scaled MCLK (LOTC mode).
6312K Mode: This pin will be in a high-impedance state.
Receive Loss Of Signal
T1 Mode: High when 192 consecutive zeros detected.
E1 Mode: High when 255 consecutive zeros detected.
DS26503 T1/E1/J1 BITS Element
6312K Mode: High when consecutive zeros detected for 65ms typically.
Receive Alarm Indication Signal
T1 Mode: Will toggle high when receive Blue Alarm is detected.
RAIS O
E1 Mode: Will toggle high when receive AIS is detected.
6312K Mode: This pin will be in a high-impedance state.
16 of 123
4.4 Controller Interface
NAME TYPE FUNCTION
Interrupt/JA Clock Source Select 1
INT: Flags host controller during events, alarms, and conditions defined in
INT/
JACKS
TMODE1 I
TMODE2 I
TSTRST I
BIS[1:0] I
AD[7]/
RITD
AD[6]/
TITD
AD[5]/
RMODE1
I/O
I/O
I/O
I/O
the status registers. Active-low open-drain output.
JACKS: Hardware Mode: JA Clock Select. Set this pin high for T1 mode
operation when either a 2.048MHz, 4.096MHz, 8.192MHz or 16.382MHz
signal is applied at MCLK.
Transmit Mode Select 1. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
Transmit Mode Select 2. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
Tri-State Control and Device Reset. A dual-function pin. A zero-to-one
transition issues a hardware reset to the DS26503 register set. Configuration
register contents are set to the default state. Leaving TSTRST high tri-states
all output and I/O pins (including the parallel control port). Set low for
normal operation. Useful for in-board level testing.
Processor Interface Mode Select 1, 0. These bits select the processor
interface mode of operation.
BIS[1:0] : 00 = Parallel Port Mode (Multiplexed)
01 = Parallel Port Mode (Nonmultiplexed)
10 = Serial Port Mode
11 = Hardware Mode
Data Bus D[7] or Address/Data Bus AD[7]/Transmit Termination Select
A[7]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[7].
AD[7]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[7].
RITD: In Hardware Mode (BIS[1:0] = 11), it disables the internal receive
termination.
Data Bus D[6] or Address/Data Bus AD[6]/Transmit Termination Select
A[6]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[6].
AD[6]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[6].
TITD: In Hardware Mode (BIS[1:0] = 11), it disables the internal transmit
termination.
Data Bus D[5] or Address/Data Bus AD[5]/Receive Framing Mode Select
Bit 1
A[5]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[5].
AD[5]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[5].
RMODE1: In Hardware Mode (BIS[1:0] = 11), it selects the receive side
operating mode.
DS26503 T1/E1/J1 BITS Element
17 of 123
NAME TYPE FUNCTION
Data Bus D[4] or Address/Data Bus AD[4]/Receive Framing Mode Select
Bit 0
A[4]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
AD[4]/
RMODE0
I/O
bus D[4].
AD[4]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[4].
RMODE0: In Hardware Mode (BIS[1:0] = 11), it selects the receive side
operating mode.
Data Bus D[3] or Address/Data Bus AD[3]/TS Mode Select
A[3]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[3].
AD[3]/TSM I/O
AD[3]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[3].
TSM: In Hardware Mode (BIS[1:0] = 11), this pin selects the function of TS.
Please see the register descriptions for more detailed information.
Data Bus D[2] or Address/Data Bus AD[2]/RS Mode Select/Serial Port
Clock
A[2]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
AD[2]/RSM/
SCLK
I/O
bus D[2].
AD[2]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[2].
RSM: In Hardware Mode (BIS[1:0] = 11), this pin selects the function of RS.
Please see the register descriptions for more detailed information.
SCLK: In Serial Port mode this is the serial clock input.
Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In
A[1]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
AD[1]/
RMODE3/
MOSI
I/O
bus D[1].
AD[1]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[1].
RMODE3: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive
side operating mode.
MOSI: Serial data input called Master Out-Slave In for clarity of data transfer
direction.
Data Bus D[0] or Address/Data Bus AD[0]/Transmit Clock Source Select 0/Master In-Slave Out
A[0]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
AD[0]/
TCSS0/
MISO
I/O
bus D[0].
AD[0]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[0].
TCSS0: Transmit Clock Source Select 0.
MISO: In serial bus mode (BIS[1:0] = 10), this pin serves as the serial data
output Master In-Slave Out.
DS26503 T1/E1/J1 BITS Element
TCSS1
I
Transmit Clock Source Select. Transmit Clock Source Select 1
18 of 123
NAME TYPE FUNCTION
Address Bus Bit A[6]/MCLK Prescale Select
A6: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[6].
A6/MPS0 I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
MPS0: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select is used to
set the prescale value for the PLL.
Address Bus Bit A[5]/Serial Port Clock Polarity Select/Transmit Mode
Select 0
A5: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[5].
A5/CPOL/
TMODE0
I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
CPOL: In Serial Port Mode (BIS[1:0] = 10), this pin selects the serial port
clock polarity. Please see the functional timing diagrams for the Serial Port
Interface for more information.
TMODE0: In Hardware Mode (BIS[1:0] = 11), this pin is used to configure
the transmit operating mode.
Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out
Select 2
A4: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[4].
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
A4/CPHA/
L2
I
should be tied low.
CPHA: In Serial Port Mode (BIS[1:0] = 10), this pin selects the serial port
clock phase. Please see the functional timing diagrams for the Serial Port
Interface for more information.
L2: In Hardware Mode (BIS[1:0] = 11), this pin selects the line build-out
value.
Address Bus Bit A[3]/Line Build-Out Select 1
A3: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[3].
A3/L1 I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
L1: In Hardware Mode (BIS[1:0] = 11), this pin selects the line build-out
value.
Address Bus Bit A[2]/Line Build-Out Select 0
A2: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[2].
A2/L0 I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
L0: In Hardware Mode (BIS[1:0] = 11), this pin selects the line build-out
value.
Address Bus Bit A[1]/Transmit AIS
A1: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[1].
A1/TAIS
I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
TAIS: When set to a 1 and in T1/E1 operating modes, the transmitter will
transmit an AIS pattern. This pin is ignored in all other operating modes.
DS26503 T1/E1/J1 BITS Element
19 of 123
NAME TYPE FUNCTION
Address Bus Bit A[0]/E1 Termination Select
A0: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[0].
A0/E1TS I
In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and
should be tied low.
E1TS: In Hardware Mode (BIS[1:0] = 11), selects the E1 internal termination
value (0 = 120W, 1 = 75W).
Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable
BTS: Strap high to select Motorola bus timing; strap low to select Intel bus
timing. This pin controls the function of the RD (DS), ALE (AS), and WR
BTS/HBE I
(R/W) pins. If BTS = 1, then these pins assume the function listed in
parentheses ().
HBE: In Hardware Mode (BIS[1:0] = 11), this pin enables transmit and
receive B8ZS/HDB3 when in T1/E1 operating modes.
Read Input-Data Strobe/Receive Mode Select Bit 2
RD(DS)/
RMODE2
I
RD (DS): These pins are active-low signals. DS is active high when BIS[1:0]
= 01. See the bus timing diagrams.
RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive
side operating mode.
Chip Select/Remote Loopback Enable
CS: This active-low signal must be low to read or write to the device. This
CS/RLB
I
signal is used for both the parallel port and the serial port modes.
RLB: In Hardware Mode (BIS[1:0] = 11), when high, remote loopback is
enabled. This function is only valid when the transmit side and receive side
are in the same operating mode.
Address Latch Enable (Address Strobe)/Address Bus Bit 7/MCLK
Prescale Select 1
ALE (AS)/
A7/MPS1
I
ALE (AS): In multiplexed bus operation (BIS[1:0] = 00), it serves to
demultiplex the bus on a positive-going edge.
A7: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[7].
MPS1: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select, used to set
the prescale value for the PLL.
Write Input (Read/Write)/Transmit Mode Select 3
WR (R/W)/
TMODE3
I
WR: In Processor Mode, this pin is the active-low write signal.
TMODE3: In Hardware Mode, this pin selects the transmit-side operating
mode.
DS26503 T1/E1/J1 BITS Element
20 of 123
4.5 JTAG
NAME TYPE FUNCTION
JTCLK I
JTMS I
JTDI I
JTDO O
JTRST I
JTAG Clock. This clock input is typically a low frequency (less than 10MHz)
50% duty cycle clock signal.
JTAG Mode Select (with Pullup). This input signal is used to control the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Input (with Pullup). This input signal is used to input data into
the register that is enabled by the JTAG controller state machine and is sampled
on the rising edge of JTCLK.
JTAG Data Output. This output signal is the output of an internal scan shift
register enabled by the JTAG controller state machine and is updated on the
falling edge of JTCLK. The pin is in the high-impedance mode when a register
is not selected or when the JTRST signal is high. The pin goes into and exits the
high impedance mode after the falling edge of JTCLK
JTAG Reset (Active Low). This input forces the JTAG controller logic into
the reset state and forces the JTDO pin into high impedance when low. This pin
should be low while power is applied and set high after the power is stable.
The pin can be driven high or low for normal operation, but must be high for
JTAG operation.
DS26503 T1/E1/J1 BITS Element
4.6 Line Interface
NAME TYPE FUNCTION
Master Clock Input. A (50ppm) clock source. This clock is used internally for
both clock/data recovery and for the jitter attenuator for both T1 and E1 modes.
MCLK I
RTIP I
RRING I
TTIP O
TRING O
THZE I
The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When
using the DS26503 in T1-only operation, a 1.544MHz (50ppm) clock source
can be used.
Receive Tip. Analog input for clock recovery circuitry. This pin connects via a
1:1 transformer to the network. See the Line Interface Unit section for details.
Receive Ring. Analog input for clock recovery circuitry. This pin connects via
a 1:1 transformer to the network. See the Line Interface Unit section for details.
Transmit Tip. Analog line-driver output. This pin connects via a 1:2 step-up
transformer to the network. See the Line Interface Unit section for details.
Transmit Ring. Analog line-driver output. This pin connects via a 1:2 step-up
transformer to the network. See the Line Interface Unit section for details.
Transmit High-Impedance Enable. When high, TTIP and TRING will be
placed into a high-impedance state.
21 of 123
DS26503 T1/E1/J1 BITS Element
4.7 Power
NAME TYPE FUNCTION
DVDD —
RVDD —
TVDD —
DVSS — Digital Signal Ground. 0.0V. Should be tied to the RVSS and TVSS pins.
Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD
pins.
Receive Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD and
TVDD pins.
Transmit Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD
and RVDD pins.
RVSS —
TVSS —
Receive Analog Signal Ground. 0.0V. Should be tied to the DVSS and TVSS
pins.
Transmit Analog Signal Ground. 0.0V. Should be tied to the DVSS and
RVSS pins.
22 of 123
5. PINOUT
Table 5-1. LQFP Pinout
MODE
PIN TYPE
1 I/O AD2 SCLK RSM
2 I/O AD3 — TSM
3 I/O AD4 — RMODE0
4 I/O AD5 — RMODE1
5 I/O AD6 — TITD
6 I/O AD7 — RITD
7, 24,
58
8, 22,
56
9 I A0 — E1TS
10 I A1 — TAIS
11 I A2 — L0
12 I A3 — L1
13 I A4 CPHA L2
14 I A5 CPOL TMODE0
15 I A6 — MPS0
16 I ALE (AS)/A7 — MPS1
I DVDD DVDD DVDD Digital Positive Supply
I DVSS DVSS DVSS Digital Signal Ground
PARALLEL
PORT
SERIAL
PORT
HARDWARE
DS26503 T1/E1/J1 BITS Element
FUNCTION
Parallel Port Mode: Address/Data Bus Bit 2
Serial Port Mode: Serial Clock
Hardware Mode: RS Mode Select
Parallel Port Mode: Address/Data Bus Bit 3
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: TS Mode Select
Parallel Port Mode: Address/Data Bus Bit 4
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Receive Mode Select 0
Parallel Port Mode: Address/Data Bus Bit 5
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Receive Mode Select 1
Parallel Port Mode: Address/Data Bus Bit 6
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Transmit Internal Termination Disable
Parallel Port Mode: Address/Data Bus Bit 7
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Receive Internal Termination Disable
Parallel Port Mode: Address Bus Bit 0
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: E1 Internal Termination Select
Parallel Port Mode: Address Bus Bit 1
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Transmit AIS
Parallel Port Mode: Address Bus Bit 2
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Line Build-Out Select 0
Parallel Port Mode: Address Bus Bit 3
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Line Build-Out Select 1
Parallel Port Mode: Address Bus Bit 4
Serial Port Mode: Serial Port Clock Phase Select
Hardware Mode: Line Build-Out Select 2
Parallel Port Mode: Address Bus Bit 5
Serial Port Mode: Serial Port Clock Polarity Select
Hardware Mode: Transmit Mode Select 0
Parallel Port Mode: Address Bus Bit 6
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: MCLK Prescaler Select 0
Parallel Port Mode: Address Latch Enable/Address Bus
Bit 7
Serial Port Mode: Unused, should be connected to V
Hardware Mode: MCLK Prescaler Select 1
.
SS
.
SS
23 of 123
DS26503 T1/E1/J1 BITS Element
MODE
PIN TYPE
PARALLEL
PORT
SERIAL
PORT
HARDWARE
FUNCTION
17 I TCLK TCLK TCLK External Transmit Clock Input
18 O TCLKO TCLKO TCLKO Transmit Clock Output
19 O TNEGO TNEGO TNEGO Transmit Negative-Data Output
20 O TPOSO TPOSO TPOSO Transmit Positive-Data Output
21 I TSER TSER TSER Transmit Serial Data
23 I/O TS TS TS T1/E1 Mode: Transmit Frame/Multiframe Sync
25 O RCLK RCLK RCLK Receive Clock
26 O RS RS RS T1/E1 Mode: Receive Frame/Multiframe Boundary
27 — N.C. N.C. N.C. No Connect. This pin must be left open.
28 O RSER RSER RSER Receive Serial Data
29 O RAIS RAIS RAIS Receive Alarm Indication Signal
30 O RLOF RLOF RLOF Receive Loss of Frame
Parallel Port Mode: Unused, should be connected to
.
V
31 I — — TCSS1
SS
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Transmit Clock Source Select 1
32 O RLOS RLOS RLOS Receive Loss Of Signal
33 I JTMS JTMS JTMS IEEE 1149.1 Test Mode Select
34 I JTCLK JTCLK JTCLK IEEE 1149.1 Test Clock Signal
35 I JTRST JTRST JTRST IEEE 1149.1 Test Reset
36 I JTDI JTDI JTDI IEEE 1149.1 Test Data Input
37 O JTDO JTDO JTDO IEEE 1149.1 Test Data Output
38 I RVDD RVDD RVDD Receive Analog Positive Supply
39 I TSTRST TSTRST TSTRST Test/Reset
40,
43, 45
I RVSS RVSS RVSS Receive Analog Signal Ground
41 I RTIP RTIP RTIP Receive Analog Tip Input
42 I RRING RRING RRING Receive Analog Ring Input
44 I MCLK MCLK MCLK Master Clock Input
Parallel Port Mode: Interrupt
46 I/O INT INT JACKS
Serial Port Mode: Interrupt
Hardware Mode: Jitter Attenuator clock select
47 O PLL_OUT PLL_OUT PLL_OUT Transmit PLL (TX PLL) Clock Output
Parallel Port Mode: Unused, should be connected to
.
V
48 I — — TMODE2
SS
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Transmit Mode Select 2
Parallel Port Mode: Unused, should be connected to
.
V
49 I — — TMODE1
SS
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Transmit Mode Select 1
50 I THZE THZE THZE Transmit High-Impedance Enable
51 O TTIP TTIP TTIP Transmit Analog Tip Output
52 I TVSS TVSS TVSS Transmit Analog Signal Ground
53 I TVDD TVDD TVDD Transmit Analog Positive Supply
54 O TRING TRING TRING Transmit Analog Ring Output
Parallel Port Mode: Bus Type Select (Motorola/Intel)
55 I BTS — HBE
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Receive and Transmit DB3/B8ZS
Enable
57 I BIS0 BIS0 BIS0 Bus Interface Select Mode 0
59 I BIS1 BIS1 BIS1 Bus Interface Select Mode 1
24 of 123
.
SS
.
SS
.
SS
.
SS
MODE
PIN TYPE
PARALLEL
PORT
SERIAL
PORT
HARDWARE
Parallel Port Mode: Chip Select (Active Low)
60 I CS CS RLB
Serial Port Mode: Chip Select (Active Low)
Hardware Mode: Remote Loopback Enable
Parallel Port Mode: Read Input (Data Strobe), Active
61 I RD (DS) — RMODE2
Low.
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Receive Mode Select 2
Parallel Port Mode: Write Input (Read/Write), Active
62 I WR (R/W) — TMODE3
Low
Serial Port Mode: Unused, should be connected to V
Hardware Mode: Transmit Mode Select 3
Parallel Port Mode: Address/Data Bus Bit 0
63 I/O AD0 MIS0 TCSS0
Serial Port Mode: Serial Data Out (Master In-Slave
Out)
Hardware Mode: Transmit Clock Source Select 0
Parallel Port Mode: Address/Data Bus Bit 1
64 I/O AD1 MOSI RMODE3
Serial Port Mode: Serial Data In (Master Out-Slave In)
Hardware Mode: Receive Mode Select 3
DS26503 T1/E1/J1 BITS Element
FUNCTION
SS
SS
.
.
25 of 123
DS26503 T1/E1/J1 BITS Element
6. HARDWARE CONTROLLER INTERFACE
In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to
certain functions in the port. Only a subset of the device’s functionality is available in hardware mode.
Each register description throughout the data sheet indicates the functions that may be controlled in
hardware mode and several alarm indicators that are available in both hardware and processor mode.
Also indicated are the fixed states of the functions not controllable in hardware mode.
6.1 Transmit Clock Source
Refer to Figure 3-3. In Hardware Controller mode, the input to the TX PLL is always TCLK PIN. TX
CLOCK is selected by the TCSS0 and TCSS1 pins, as shown in Table 6-1
the same signal as select for TX CLOCK. If the user wants to slave the transmitter to the recovered
clock, then the RCLK pin must be tied to the TCLK pin externally.
. The PLL_OUT pin is always
Table 6-1. Transmit Clock Source
TCSS1
PIN 31
0 0 The TCLK pin is the source of transmit clock.
0 1 The PLL_CLK is the source of transmit clock.
1 0
1 1 The signal present at RCLK is the transmit clock.
TCSS0
PIN 63
TRANSMIT CLOCK SOURCE
The scaled signal present at MCLK as the transmit
clock.
6.2 Internal Termination
In Hardware Controller mode, the internal termination is automatically set according to the receive or
transmit mode selected. It can be disabled via the TITD and RITD pins. If internal termination is enabled
in E1 mode, the E1TS pin is use to select 75W or 120W termination. The E1TS pin applies to both
transmit and receive.
Table 6-2. Internal Termination
PIN NAME FUNCTION
TITD
PIN 5
RITD
PIN 6
E1TS
PIN 9
Transmit Internal Termination Disable. Disables the internal transmit
termination. The internal transmit termination value is dependent on the state of
the TMODEx pins.
Receive Internal Termination Disable. Disables the internal receive
termination. The internal receive termination value is dependent on the state of
the RMODEx pins.
E1 Termination Select. Selects 120W or 75W internal termination when one of
the E1 modes is selected and internal termination is enabled. IF E1 is selected for
both transmit and receive, then both terminations will be the same.
0 = 75W
1 = 120W
26 of 123
6.3 Line Build-Out
Table 6-3. E1 Line Build-Out
DS26503 T1/E1/J1 BITS Element
L2
PIN 13
0 0 0 75Ω normal 1:2 N.M. 0
0 0 1 120Ω normal 1:2 N.M. 0
1 0 0 75Ω with high return loss* 1:2 21dB 6.2Ω
1 0 1 120Ω with high return loss* 1:2 21dB 11.6Ω
1 1 0 Reserved — — —
1 1 1 Reserved — — —
L1
PIN 12
L0
PIN 11
APPLICATION N (1) RETURN LOSS Rt (1)
*TTD pin must be connected high in this mode.
N.M. = not meaningful
Table 6-4. T1 Line Build-Out
L2
PIN 13
0 0 0 DSX-1 (0 to 133 feet)/0dB CSU 1:2 N.M. 0
0 0 1 DSX-1 (133 to 266 feet) 1:2 N.M. 0
0 1 0 DSX-1 (266 to 399 feet) 1:2 N.M. 0
0 1 1 DSX-1 (399 to 533 feet) 1:2 N.M. 0
1 0 0 DSX-1 (533 to 655 feet) 1:2 N.M. 0
1 0 1 Reserved — — —
1 1 0 Reserved — — —
1 1 1 Reserved — — —
L1
PIN 12
L0
PIN 11
APPLICATION N (1)
RETURN
LOSS
Rt (1)
6.4 Receiver Operating Modes
Table 6-5. Receive Path Operating Mode
RMODE3
PIN 64
0 0 0 0 T1 D4
0 0 0 1 T1 ESF
0 0 1 0 J1 D4
0 0 1 1 J1 ESF
0 1 0 0 E1 FAS
0 1 0 1 E1 CAS
0 1 1 0 E1 CRC4
0 1 1 1 E1 CAS and CRC4
1 0 0 0 E1 G.703 2048kHz Synchronization Interface
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 6312kHz Synchronization Interface
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
RMODE2
PIN 61
RMODE1
PIN 4
RMODE0
PIN 3
RECEIVE PATH OPERATING MODE
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6.5 Transmitter Operating Modes
Table 6-6.Transmit Path Operating Mode
DS26503 T1/E1/J1 BITS Element
TMODE3
PIN 62
0 0 0 0 T1 D4
0 0 0 1 T1 ESF
0 0 1 0 J1 D4
0 0 1 1 J1 ESF
0 1 0 0 E1 FAS
0 1 0 0 E1 FAS + CAS (Note 1)
0 1 0 1 Reserved
0 1 1 0 E1 CRC4
0 1 1 0 E1 CRC4 + CAS (Note 1)
0 1 1 1 Reserved
1 0 0 0 E1 G.703 2048kHz Synchronization Interface
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 6312kHz Synchronization Interface (Note 2)
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
TMODE2
PIN 48
TMODE1
PIN 49
TMODE0
PIN 14
TRANSMIT PATH OPERATING MODE
Note 1:
Note 2:
The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS
signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present
on the TSER pin and frame aligned to sync signal on the TS pin.
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be
configured to transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7).
6.6 MCLK Pre-Scaler
Table 6-7. MCLK Pre-Scaler for T1 Mode
MPS1
PIN 16
0 0 0 1.544
0 1 0 3.088
1 0 0 6.176
1 1 0 12.352
0 0 1 2.048
0 1 1 4.096
1 0 1 8.192
1 1 1 16.384
MPS0
PIN 15
JACKS
PIN 46
MCLK
(MHz)
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Table 6-8. MCLK Pre-Scaler for E1 Mode
DS26503 T1/E1/J1 BITS Element
MPS1
PIN 16
0 0 0 2.048
0 0 1 Reserved
0 1 0 4.096
0 1 1 Reserved
1 0 0 8.192
1 0 1 Reserved
1 1 0 16.384
1 1 1 Reserved
MPS0
PIN 15
JACKS
PIN 46
MCLK
(MHz)
6.7 Other Hardware Controller Mode Features
Table 6-9. Other Operational Modes
PIN
NAME
RSM
PIN 1
TSM
PIN2
RLB
PIN 60
TAIS
PIN 10
HBE
PIN 55
RS Mode Select: Selects frame or multiframe pulse at RS pin.
0 = frame mode
1 = multiframe mode
TS Mode Select: In T1 or E1 operation, selects frame or multiframe mode for the TS pin.
0 = frame mode
1 = multiframe mode
Remote Loopback Enable: In this loopback, data input to the framer portion of the
DS26503 will be transmitted back to the transmit portion of the LIU. Data will continue to
pass through the receive side framer of the DS26503 as it would normally and the data
from the transmit side formatter will be ignored.
0 = loopback disabled
1 = loopback enabled
Transmit AIS
0 = normal transmission
1 = transmit AIS alarm
Receive and Transmit HDB3/B8ZS Enable
0 = HDB3/B8ZS disabled
1 = HDB3/B8ZS enabled
DESCRIPTION
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DS26503 T1/E1/J1 BITS Element
7. PROCESSOR INTERFACE
The DS26503 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[1:0] = 00)
parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus
interface type is selected by BIS1 and BIS0 as shown in Table 7-1.
Table 7-1. Port Mode Select
BIS1 BIS0 PORT MODE
0 0 Parallel Port Mode (Multiplexed)
0 1 Parallel Port Mode (Nonmultiplexed)
1 0 Serial Port Mode (SPI)
1 1 Hardware Mode
7.1 Parallel Port Functional Description
In parallel mode, the DS26503 can operate with either Intel or Motorola bus timing configurations. If the
BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical
Characteristics section for more details.
7.2 SPI Serial Port Interface Functional Description
A serial SPI bus interface is selected when bus select is 10 (BIS[1:0] = 10). In this mode, a master/slave
relationship is enabled on the serial port with three signal lines (SCK, MOSI, and MISO) and a chip
select (CS), with the DS26503 acting as the slave. Port read/write timing is not related to the system
read/write timing, thus allowing asynchronous, half-duplex operation. See the AC Electrical
Characteristics section for the AC timing characteristics of the serial port.
7.2.1 Clock Phase and Polarity
Clock Phase and Polarity are selected by the CPHA and CPOL pins. The slave device should always be
configured to match the bus master. See the SPI Serial Port Mode section for detailed functional timing
diagrams.
7.2.2 Bit Order
The most significant bit (MSB) of each byte is transmitted first.
7.2.3 Control Byte
The bus master will transmit two control bytes following a chip select to a slave device. The MSB will be
a R/W bit (1=read, 0=write). The next 6 bits will be padded with 0s. The LSB of the first byte will be
A[7]. The second control byte will be the address bits (A[6:0]) of the target register, followed by a Burst
bit in the LSB position (1=Burst, 0=Non-burst).
7.2.4 Burst Mode
The last bit of the second control byte (LSB) is the Burst mode bit. When the Burst bit is enabled (set to
1) and a read operation is performed, the register address is automatically incremented after the LSB of
the previous byte read to the next register address. Data will be available on the next clock edge following
the LSB of the previous byte read. When the Burst bit is enabled (set to 1) and a write operation is
performed, the register address will be automatically incremented to the next byte boundary following the
LSB of the previous register write, and 8 more data bits will be expected on the serial bus. Burst accesses
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