Rainbow Electronics DS25LV02 User Manual

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GENERAL DESCRIPTION

The DS25LV02 provides data storage and serial number identification for battery packs. The lowvoltage Dallas 1-WireÒ interface enables serial communication on a single battery contact and the 64-bit unique serial number allows multidrop networking and identification of individual devices. The 1024-bit EPROM memory is organized as 4 pages of 32 bytes each and supports storage of battery cell characteristics, charging voltage, current and temperature parameters, as well as battery pack manufacturing data. CRC verification provides data integrity during communication. The EPROM pages are in-circuit writable and can be individually locked to protect data. The DS25LV02 is designed to be completely backward-compatible with the DS2502 for existing designs.

APPLICATIONS

Cell Phones/Smartphones Digital Cameras MP3 Players

TYPICAL APPLICATION CIRCUIT

DS25LV02

Low-Voltage 1024-Bit EPROM

FEATURES

§ 128 Bytes of EPROM Storage Organized into Four Separately Lockable Pages

§ Backward-Compatible with DS2502

§ Dallas 1-Wire Interface

§ Input Logic Thresholds Compatible with 1.8V

I/O Supply Rail

§ Unique 64-Bit Serial Number

§ Operates with V

§ Tiny, Thin SOT-23 Package

PIN CONFIGURATION

TOP VIEW

as Low as 2.2V

5-Pin Thin-SOT (TSOT)

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS25LV02R+U

DS25LV02R+T& R

+Denotes lead-free package.

1-Wire is a registered trademark of Dallas Semiconductor.

Certain commands, modes, and registers are capitalized for clarity.

-30°C to +85°C

5 Thin SOT

5 Thin SOT in Tape-and-Reel

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DS25LV02: Low-Voltage 1024-Bit EPROM

ABSOLUTE MAXIMUM RATINGS

Voltage Range on DQ, Relative to VSS -0.3V to +12V Voltage Range on V

, Relative to VSS -0.3V to +6V

Operating Temperature Range -30°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020A Specification

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

RECOMMENDED DC OPERATING CONDITIONS

(2.2V £ VDD £ 5.5V, TA = -30°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VDD (Notes 1, 2) 2.2 5.5 V

Data Pin Communication Voltage VDQ (Note 1) -0.3 +5.5 V

Data Pin Programming Voltage VPP (Notes 1, 2, 5) 11.5 12.0 V

DC ELECTRICAL CHARACTERISTICS

(2.2V £ VDD £ 5.5V, TA = -30°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DQ Idle (Note 4) 0.8 2

Supply Current

DD0

Communication mode, DQ active 300

DD1

Input-Logic High: DQ VIH (Note 1) 1.5 V

VDD ≥ 2.5V 0.6

Input-Logic Low: DQ (Note 1) VIL

0.4

Output-Logic Low: DQ V

Pulldown Current: DQ IPD 0.5

IOL = 4mA (Note 1) 0.4 V

EPROM RELIABILITY SPECIFICATION

(2.2V £ VDD £ 5.5V, TA = -30°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Storage t

(Notes 2, 3) 10 Years

EES

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DS25LV02: Low-Voltage 1024-Bit EPROM

AC ELECTRICAL CHARACTERISTICS: EPROM PROGRAMMING

(3.0V £ VDD £ 5.5V, TA = -30°C to +50°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Programming Pulse Width t

Program Voltage Rise Time t

(Notes 1, 2, 5, 6) 480 5000

(Notes 1, 2, 5) 0.5 5.0

Program Voltage Fall Time tFP (Notes 1, 2, 5) 0.5 5.0

Programming Current: DQ Pin I

(Notes 2, 5, 7) 6 10 mA

AC ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE

(2.2V £ VDD £ 5.5V, TA = -30°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Time Slot t

Recovery Time t

Write-0 Low Time t

Write-1 Low Time t

Read-Data Valid t

Reset-Time High t

Reset-Time Low t

60 120

SLOT

REC

60 120

LOW0

1 15

LOW1

RDV

480

RSTH

480 960

RSTL

Presence-Detect High t

Presence-Detect Low t

Delay to Program Pulse tDP 5

Delay to Verify tDV 5

15 60

PDH

60 240

PDL

DQ Capacitance CDQ 50 pF

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

All voltages are referenced to V

Programming of the EPROM Data and EPROM Status fields require a limited temperature range of 0°C to 50°C and limited V voltage range of 3.0V to 5.5V. Storage for t

DQ < V

Programming pulse on DQ pin must be shaped to conform with rise, fall, and width timing specifications. See Figure 7. EPROM Programming Diagram). The accumulative duration of all programming pulses for each address must not exceed 5ms.

Specification is guaranteed by design.

at +50°C.

EES

for t > 1.5ms or DQ > VIH for t > 1.5ms [1-Wire oscillator shut down].

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DS25LV02: Low-Voltage 1024-Bit EPROM

PIN DESCRIPTION

PIN NAME FUNCTION

1, 3 N.C. No Connection

Supply GND and Reference for Serial Communication. Attach terminal.

to battery-pack negative

5 DQ

Figure 1. Block Diagram

0.5mA

Supply Input. Bypass to VSS with 0.01mF (typ).

Serial Interface Data I/O Pin. Bidirectional data transmit and receive at 16kbps. Input for programming voltage pulse during EPROM programming. Internal 0.5mA pulldown ensures idle mode is entered when no DQ pullup is present.

VDD

HV Detect

Reg.

Vdd_int

DIN

1-Wire I/F

and

Control

DOUT

EPROM Array

HV Shaper

Vpp

VSS

DETAILED DESCRIPTION

The DS25LV02 provides battery-pack identification and data storage. A 128-byte EPROM memory array and an 8 byte status field accessed by a low-voltage 1-Wire interface. Each DS25LV02 has a unique 64-bit Net Address (ROM ID) for identification.

The EPROM is divided into four 32-byte pages. An additional 8-byte status field provides lock bit and page redirection information to the user. EPROM writing occurs one byte at a time by supplying a 12V pulse on the DQ line in-between each byte written. Each page can be individually locked by clearing the appropriate bit in the Status field. Data is read sequentially from a starting address through the end of the array. CRC verification provides integrity of all read and written data.

Functional compatibility has been maintained between the DS2502 and DS25LV02 at the Net Address/ROM Command and Function Command levels for reading and writing the Memory data and Status data fields.

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DS25LV02: Low-Voltage 1024-Bit EPROM

EPROM MEMORY DATA FIELD

The DS25LV02 has a linear address space for access to the EPROM data field. The EPROM data field is organized as 4 pages of 32 bytes each as shown in Table 1. The Read Memory and Read Data/Generate CRC Memory function commands provide read access to the 1024 bits of the EPROM data field. The Write Memory function command provides write access to the EPROM data field. When received from the factory, the entire 1024-bit EPROM data field is erased and returns logical 1’s when read. Bits within the data field are one time programmable. Programming changes the bit value to logical zero from the factory default erased value of a logical

1. Once a bit is programmed, it cannot be set back to a logical 1.

Table 1. EPROM Data Field

ADDRESS (HEX) DESCRIPTION READ/WRITE

0000–001F PAGE 0 (32 bytes) R/W*

0020–003F PAGE 1 (32 bytes) R/W*

0040–005F PAGE 2 (32 bytes) R/W*

0060–007F PAGE 3 (32 bytes) R/W*

0080–FFFF Reserved

* One-time write to “0” for each bit.

READ MEMORY [F0h]

The Read Memory command is used to read data from PAGE 0 to PAGE 3 of the 1024-bit EPROM data field. The bus master follows the command byte with a 2-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to be correct by the bus master, read time slots can be issued to receive data from the EPROM data field starting at the initial address. The bus master can issue a reset pulse at any point or continue to issue read time slots until the end of PAGE 3 of the data field is reached.

If reading continues through the end of PAGE 3, the bus master can issue eight additional read time slots and the DS25LV02 will respond with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of PAGE 3. Terminating the command transaction with a reset pulse prior to reaching the end of PAGE 3 results in a loss of availability of the 8-bit CRC.

READ DATA/GENERATE 8-BIT CRC [C3h]

The Read Data/Generate 8-bit CRC command is used to read data from PAGE 0 to PAGE 3 of the 1024-bit EPROM data field. The bus master follows the command byte with a 2-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to be correct by the bus master, read time slots can be issued to receive data from the EPROM data field starting at the initial address. The bus master can issue a reset pulse at any point or continue to issue read time slots until the end of the 32-byte page is reached. If reading occurs through the end of the 32-byte page, the bus master can issue eight additional read time slots and the DS25LV02 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of the current page. After the CRC is received, additional read time slots return data starting with the first byte of the next page. This sequence will continue until the bus master reads PAGE 3 and its accompanying CRC. Thus each page of data can be considered to be 33 bytes long: the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a reset pulse.

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DS25LV02: Low-Voltage 1024-Bit EPROM

WRITE MEMORY [0Fh]

The Write Memory command is used to program the 1024-bit EPROM data field. Programming is performed one or more bytes at a time, with CRCs of the master-to-slave bit stream provided for data integrity. To begin a memory write, the bus master issues the Write Memory function command followed by a 2-byte address argument (TA1 = (T7:T0), TA2 = (T15:T8)) and a 1-byte data argument (D7:D0). The 2-byte address argument sets the starting byte position in the EPROM data field of the first byte to be written. The data argument provides data for the first byte to be written. The master must issue 8 read timeslots following the data argument.

An 8-bit CRC of the command byte, address bytes and data byte computed by the DS25LV02 is returned in the 8 timeslots to enable the master to check the integrity of the communication. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to be correct by the bus master, a programming pulse can be issued to program the byte position within the EPROM data field pointed to by T15:T0. Following the programming pulse, the bus master must issue 8 read timeslots. The read timeslots return the EPROM data byte value (least significant bit first) for confirmation by the master.

The bus master can issue a reset pulse at any point after issuing the program pulse to end the write operation, or continue the write operation with the next byte in the EPROM data field. If a the write operation is continued, the DS25LV02 automatically increments the internal address pointer to select the next byte in the EPROM data field, and the new value of T7:T0 is loaded into the 8-bit CRC generator as the starting value. The bus master issues the next 1-byte data argument followed by 8 read timeslots to return the CRC computed by the DS25LV02. The value returned is computed with D7:D0, using T7:T0 as the starting value. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to be correct by the bus master, a programming pulse can be issued to program the byte position pointed to by T15:T0. Following the programming pulse, the bus master must issue 8 read timeslots. The read timeslots return the EPROM data byte value (least significant bit first) for confirmation by the master.

The write operation can be continued until the end of the EPROM data field is reached by repeating the sequence of issuing a 1-byte data argument, 8 read timeslots to return CRC, a programming pulse, and 8 read timeslots to return EPROM data.

EPROM STATUS

The DS25LV02 has a separate 8-byte linear address space for access to the EPROM STATUS data field using the Read Status and Write Status function commands.

READ STATUS [AAh]

The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a 2-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus master, a reset pulse should be issued and the entire sequence repeated. If the CRC is deemed to be correct by the bus master, read timeslots can be issued to receive data starting at the initial address. The bus master can issue a reset pulse at any point or continue to issue read timeslots until the end of the EPROM Status data field is reached. If reading occurs through the end of the EPROM Status data field, the bus master can issue 8 additional read timeslots and the DS25LV02 will respond with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte. Additional read timeslots return logical 1s until the internal address reaches a multiple of 128. Then data is returned from address 0000h. The Read Status command sequence can be ended at any point by issuing a reset pulse.

WRITE STATUS [55h]

The Write Status command is used to program the EPROM status field. To begin a status field write, the bus master issues the Write Status function command followed by a 2-byte address argument (TA1 = (T7:T0), TA2 = (T15:T8)) and a 1-byte data argument (D7:D0). The 2-byte address argument sets the starting byte position in the EPROM status field of the first byte to be written. The data argument provides data for the first byte to be written. The master must issue 8 read timeslots following the data argument.

An 8-bit CRC of the command byte, address bytes, and data byte computed by the DS25LV02 is returned in the 8 timeslots to enable the master to check the integrity of the communication. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to

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