Rainbow Electronics DS2431 User Manual

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DS2431

1024-Bit 1-Wire EEPROM

GENERAL DESCRIPTION

The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-b yte scratchpad, verif ied, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 stat e. The DS2431 communicates over the singleconductor 1-Wire bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol. Each device has its own unaltera ble and unique 64bit ROM registration number that is factory lasered into the chip. The registration number is used to address the device in a multidrop 1-Wire net environment.

APPLICATIONS

Accessory/PC Board Ident if ic ati on Medical Sensor Calibration Data Storage Analog Sensor Calibration Including IEEEP1451.4 Smart Sensors Ink and Toner Print Cartridge Identification After-Market Management of Consumables

FEATURES

1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits

Individual Memor y Pages can be Permanently Write Protected or Put in EPROM-Emulation Mode ("Write to 0")

Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise

IEC 1000-4-2 Level 4 ESD Protection (8kV Contact, 15kV Air)

Reads and Writes Over a Wide Voltage Range of

2.8V to 5.25V from -40°C to +85°C

Communicates to Host with a Single Digital Signal at 15.4kbps or 111kbps Using 1-Wire Protocol

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2431 -40°C to 85°C TO-92 DS2431/T&R -40°C to 85°C TO-92, tape & reel DS2431P -40°C to 85°C TSOC DS2431P/T&R -40°C to 85°C TSOC, tape & reel DS2431X -40°C to 85°C CSP, tape & reel

TYPICAL OPERATING CIRCUIT

PUP

µC

I/O

DS2431

GND

Commands, Registers, and Modes ar e capita li ze d for clarity.

PIN CONFIGURATION

TO-92

1 2 3

2 3

TSOC, TO-92 pi nout: Pin 1 ------------- GND Pin 2 ------------- I/O All other pins -- NC

2 1

A B

CSP, approx. 68 × 68 mil

TSOC, Top View

A1 = NC A2 = I/O B1 = NC B2 = GND

5 4

Top view, bumps not visible

1-Wire is a registered trademark of Dallas Semiconductor Corp.

Note: Some revisions of this device may incorporate deviations from published spec ifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For informati on about device errata, click here: www.maxim-ic.com/errata.

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REV: 050704

DS2431: 1024-Bit, 1-Wire EEPRO M

ABSOLUTE MAXIMUM RATINGS

I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -40°C to +85°C Soldering Temperature See IPC/JEDEC J-STD-020A

Stresses beyond those listed under “Absolute Maximum Ratings” may caus e permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device rel i abili ty .

ELECTRICAL CHARACTERISTICS

= 2.8V to 5.25V, TA = -40°C to +85°C.)

PUP

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/O PIN GENERAL DATA

1-Wire Pullup Resistance Input Capacitance C Input Load Current I High-to-Low Switching

Threshold Input Low Voltage V Low-to-High Switching Threshold Switching Hysteresis V Output Low Voltage V

Recovery Time (Notes 1,11)

Rising-Edge Hold-off Time t Timeslot Duration (Note 1) t

REC

REH

SLOT

PUP

IO L

HY OL

I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE

Reset Low Time (Note 1) t

Presence Detect High Time

Presence Detect Fall Time (Notes 4, 14)

Presence Detect Low Time

Presence Detect Sample Time (Note 1)

RSTL

PDH

FPD

PDL

MSP

(Notes 1, 2)

0.3 2.2

kΩ (Notes 3, 4) 100 800 pF I/O pin at V

PUP

0.05 2.2 µA (Notes 4, 5, 6) 0.5 4.1 V (Notes 1, 7) 0.3 V (Notes 4, 5, 8) 1.0 4.9 V (Notes 4, 5, 9) 0.22 1.70 V

At 4mA (Note 10) 0.4 V Standard speed, R Overdrive speed, R

PUP

= 2.2kΩ

= 2.2kΩ Overdrive speed, directly prior to reset pulse; R

PUP

= 2.2kΩ Standard speed (Note 12) 0.5 5.0 Overdrive speed Not applicable (0) Standard speed 65 Overdrive speed (Note 13) 9

Standard speed, V

> 4.5V 480 640

PUP

Standard speed (Note 12) 504 640 Overdrive speed, V

> 4.5V 48 80

PUP

5 2

µs

µs µs

µs

Overdrive speed (Note 13) 53 80 Standard speed, V Standard speed (Note 13) 15 63

> 4.5V 15 60

PUP

µs Overdrive speed (Note 13) 2 7 Standard speed, V Standard speed 1.1 7

> 4.5V 1.1 3.75

PUP

µs Overdrive speed 1.1 Standard speed 60 240 Overdrive speed, V

> 4.5V 8 24

PUP

µs Overdrive speed (Note 13) 8 26 Standard speed, V Standard speed 70 75

> 4.5V 64 75

PUP

µs Overdrive speed 8.1 10

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DS2431: 1024-Bit, 1-Wire EEPRO M

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/O PIN, 1-Wire WRITE

Write-0 Low Time (Note 1) t Write-1 Low Time

(Notes 1, 15)

I/O PIN, 1-Wire READ

Read Low Time (Notes 1, 16)

Read Sample Time (Notes 1, 16)

EEPROM

Programming Current I Programming Time t Write/Erase Cycles (Endurance) Data Retention t

W0L

W1L

MSR

PROG PROG

Standard speed 60 120 Overdrive speed (Note 13) 716 Standard speed 5 Overdrive speed 1

Standard speed 5 Overdrive speed 1 Standard speed Overdrive speed

tRL + δ tRL + δ

15 - ε

2 - ε

15 - δ

2 - δ

(Note 17) 1 mA (Note 18) 12.5 ms At 25°C 200k At 85°C (worst case) 50k At 85°C (worst case) 10 years

µs

---

Note 1: Note 2:

Note 3:

Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:

Note 15: Note 16:

Note 17:

Note 18:

System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Capacitance on the data pin could be 800pF when V after V Guaranteed by design, simulation only. Not production tested. V Voltage below which, during a falling edge on I/O, a logic 0 is detected. The voltage on I/O needs to be less or equal to V Voltage above which, during a rising edge on I/O, a logic 1 is detected. After V The I-V characteristic is linear for voltages less than 1V. Applies to a single DS2431 attached to a 1-Wire line. The earliest recognition of a negative edge is possible at t Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparis on table bel ow. Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 80% of V

ε represents the time required for the pullup circuitry to pull the voltage on I/O up from V δ represents the time required for the pullup circuitry to pull the voltage on I/O up from V

master. Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval should be such that the voltage at I/O is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a low impedance bypass of Rpup which can be activated during programming may need to be added. Interval begins t sequence. Interval ends once the device's self-timed EEPROM programm ing cycle is complete and the current drawn by the device has returned from I

has been applied the parasite capacitance will not affect normal communications.

PUP

, VTH, and V

are a function of the internal supply voltage.

is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic '0'.

and the time at which the voltage is 20% of V

PUP

after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad

WiLMIN

to IL.

PROG

is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs

PUP

whenever the master drives the line low.

ILMAX

after VTH has been previously reached.

REH

PUP

to VTH.

to the input high threshold of the bus

LEGACY VALUES DS2431 VALUES

PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED

MIN MAX MIN MAX MIN MAX MIN MAX

(incl. t

SLOT

RSTL

PDH

PDL

W0L

Intentional change, longer recovery time requirement due to modified 1-Wire front end.

) 61µs (undef.) 7µs (undef.) 65µs

REC

480µs (undef.) 48µs 80µs 504µs 640µs 53µs 80µs

15µs 60µs 2µs 6µs 15µs 63µs 2µs 7µs 60µs 240µs 8µs 24µs 60µs 240µs 8µs 26µs 60µs 120µs 6µs 16µs 60µs 120µs 7µs 16µs

(undef.) 9µs (undef.)

PIN DESCRIPTION

NAME FUNCTION

I/O 1-Wire Bus Interface. Open drain, requires external pullup resistor.

GND Ground Reference

N.C. Not Connected

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DS2431: 1024-Bit, 1-Wire EEPRO M

DESCRIPTION

The DS2431 combines 1 024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes, and a fully-featured 1-Wire interface in a single c hip. Each DS2431 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431 has an additional mem ory area ca lled the sc ratchpad t hat acts as a buff er when writing to t he main m emor y or the register page. Data is first written to the scratchpad from which it can be read back. After the data has been verified, a cop y scratchpad command transf ers the data to its final memory location. Applications of the DS2431 include accessory/PC board identification, medical sensor calibration data storage, analog sensor calibration including IEEE-P1451.4 Sm art Sensors, ink and toner pr int cartridge identif ication, and after-m arket management of consumables.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2431. The DS2431 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, and 4) 6 4- bit r egis t er pa ge. The hierarchical str uc ture of the 1-Wire protocol is shown i n Fig ur e

2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resum e, 6) Overdrive- Skip ROM or 7) Overdrive-Matc h ROM. Upon c ompletion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent comm unication occurs at a higher sp eed. The protoc ol requir ed for thes e ROM function c ommands is described in Figure 9. After a ROM function command is successfully executed, the memory functions becom e accessible and the master m ay provide any one of the four m emory function commands. The protoc ol for these memory function commands is described in Figure 7. All data is read and written least significant bit first.

Figure 1. Block Diagram

I/O

Function Control

Memory

Function

Control Unit

CRC16

Generator

Data Memory

4 Pages of

256 bits each

1-Wire

PARASITE POWER

64-bit

Lasered ROM

DS2431

64-bit

Scratchpad

64 bits

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Figure 2. Hierarchical Structure for 1-Wire Protocol

DS2431: 1024-Bit, 1-Wire EEPRO M

DS2431 Co m m a nd Level:

1-Wire ROM Function

Commands (see Figure 9)

DS2431-specific

Memory Function

Commands (see Figure 7)

Available Commands:

Read ROM Match ROM Search ROM Skip ROM Resume Overdrive Skip Overdrive Match

Write Scratchpad Read Scratchpad Copy Scratchpad Read Memory

Data Field Affected:

64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag RC-Flag RC-Flag 64-bit Reg. #, RC-Flag, OD-Flag 64-bit Reg. #, RC-Flag, OD-Flag

64-bit Scratchpad, Flags 64-bit Scratchpad Data Memory, Register Page Data Memory, Register Page

64-BIT LASERED ROM

Each DS2431 contains a uniqu e ROM code that is 6 4 bits long. T he f irst 8 bits ar e a 1-W ire f amily code. T he next 48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundanc y Check) of the f irst 56 bits. See Figure 3 for details. T he 1-Wire CRC is generated using a polynomial generator cons isting of a shift register and XOR gates as shown in Figure 4. The polynomial is X CRC is available in Application Note 27.

The shift register b its are initial ized to 0. Then s tarting with the least sig nificant bit of the f amily code, one bit at a time is shifted in. Af ter the 8t h bit of the fam ily code has b een enter ed, then th e serial number is entered. After the last bit of the serial number has been entered, the shift register contai ns the CRC value. Shifting i n the 8 bits of the CRC returns the shift register to all 0s.

+ X5 + X4 + 1. Additional infor mation about the Dall as 1- Wire

Figure 3. 64-Bit Lasered ROM

MSB LSB

8-Bit

CRC Code

MSB LSB MSB LSB MSB LSB

Figure 4. 1-Wire CRC Generator

STAGE

48-Bit Serial Number

Polynomial = X8 + X5 + X4 + 1

STAGE

INPUT DATA

8-Bit Family Code (2Dh)

STAGE

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DS2431: 1024-Bit, 1-Wire EEPRO M

Figure 5. Memory Map

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) Data Memory Page 0 0020h to 003Fh R/(W) Data Memory Page 1 0040h to 005Fh R/(W) Data Memory Page 2 0060h to 007Fh R/(W) Data Memory Page 3

0080h

0081h

0082h

0083h

0084h

R/(W) Protection Control Byte

Page 0

R/(W) Protection Control Byte

Page 1

R/(W) Protection Control Byte

Page 2

R/(W) Protection Control Byte

Page 3

55h: Write Protect P0; AAh: EPROM mode P0; 55h or AAh: Write Protect 80h

55h: Write Protect P1; AAh: EPROM mode P1; 55h or AAh: Write Protect 81h

55h: Write Protect P2; AAh: EPROM mode P2; 55h or AAh: Write Protect 82h

55h: Write Protect P3; AAh: EPROM mode P3; 55h or AAh: Write Protect 83h

R/(W) Copy Protecti on B yte 55h or AAh: Copy Protect 008 0:00 8Fh, and

any write-protected Pages

0085h R Factory byte. Set at

Factory.

AAh:Write Protect 85h, 86h, 87h;

55h: Write Protect 85h, unprotect 86h, 87h 0086h R/(W) User Byte/Manufacturer ID 0087h R/(W) User Byte/Manufacturer ID 0088h to 008Fh N/A Reserved

Once programm ed to AAh or 5 5h this a ddress bec omes read-onl y. All oth er c odes can be s tored but will neith er

write-protect the address nor activate any function.

MEMORY

Data memory and regist ers are loc ated in a linear addres s spac e, as show n in Fi gure 5. T he data m emor y and t he registers have unrestrict ed r e ad acc es s . T he DS 243 1 EE P RO M ar ra y co nsis ts of 18 rows of 8 bytes each. T he f irs t 16 rows are divided equally into 4 m emory pages (32 bytes each). These 4 pages ar e the primary data m emory. Each page can be individually set to open (unprotected), write protected, or EPROM mode by setting the associated protectio n byte in the regist er row. The last two r ows contain protect ion registers, an d reserved bytes . The register row consists of 4 protection control bytes, a copy protection byte, the factory byte, and two user byte/manufacture ID bytes. The m anufacturer ID can be a customer-suppl ied identification code that assists the application software in identifying the product the DS2431 is associated with. Contact the f actory to set up and register a custom manufacturer ID. The last row is reserved for future use. It is undefined in terms of R/W functionality and should not be use d.

In addition to the main EEPROM array, an 8-byte vo latile s cratchpa d is inc luded. Writes to the EEPROM arr ay are a two-step process. First, da ta is written to the scratchpa d, and then copied into the m ain array. This allows the user to first verif y the data written to s cratchpad pr ior to c opying into the m ain arra y. The device on ly supports full row (8-byte) copy operations. In order for data in the scratchpad to be valid for a copy operation, the address supplied with a Write Scratchpad must start on a row boundary, and 8 full bytes must be written into the scratchpad.

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DS2431: 1024-Bit, 1-Wire EEPRO M

The protection contr ol registers determine ho w incoming data on a write-scratchpad com mand is loaded into the scratchpad. A protection setting of 55h (W rite Protect) causes the incoming data to be ingnored and t he target address main memory data to be loaded into the scratchpad. A pr otection setting of AAh (EPROM Mode) c auses the logical AND of incoming data and target address main memory data to be loaded into the scratchpad. Any other protection control register setting leaves the associated m emory page open for unrestricted write access. Protection control b yte settings of 55h or AAh also wr ite protect the protection control b yte. The prot ection-contro l byte setting of 55h does n ot block the cop y. This allows write-protected data t o be refreshed ( i. e., reprogramm ed with the current data) in the device.

The copy protection b yte is used for a higher level of security, and should only be used after all other protection control bytes, user bytes, and writ e-protected pag es are set to their fin al value. If t he copy protec tion b yte is set to 55h or Aah, all copy attem pts to the register row and user byte row are block ed. In addition, all copy attem pts to write-protected main memory pages (i. e., refresh) are blocked.

ADDRESS REGISTERS AND TRANSFER STATUS

The DS2431 employs three address register s: T A1, TA2, and E/S (Figure 6) . T hes e r egist er s are c om mon to man y other 1-Wire devices but operate slig htly differ ently with the D S2431. Register s TA1 and T A2 must be lo aded with the target address to which the data is written or from which data is re ad. Register E/S is a read-only tr ansferstatus register, used to verify data integrity with write commands. ES bits E2:E0 are loaded with the incoming T2:T0 on a write-scratchpad command, and increment on each subsequent data byte. This is in effect a byteending offset counter within the 8-b yte scratchpad. Bit 5 of the E/S register, cal led PF, is a logic 1 if the data in the scratchpad is not va li d du e to a los s of po wer or if the master sends l es s b ytes tha n n eed ed to reach the end of the scratchpad. For a valid wr ite to the s cratchpa d, T2:T 0 must be 0 and t he m aster mus t have sent 8 da ta bytes . Bits 3, 4, and 6 have no function; they always read 0. The highest valued bit of the E/S register, called AA or Authorization Accepted, ac ts as a flag to indicat e that the data stor ed i n the sc ratchpa d has alre ad y been copi ed to the target memory address. Writing data to the scratchpad clears this flag.

Figure 6. Address Registers

Bit #76543210

Target Address (TA1)T7T6T5T4T3T2T1T0

Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8

Ending Address with

Data Status (E/S)

(Read Only)

AA 0 PF 0 0E2E1E0

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Rainbow Electronics DS2431 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual