Rainbow Electronics DS2417 User Manual

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DS2417

1-Wire Time Chip With Interrupt

FEATURES

PIN ASSIGNMENT

§ Real-time clock (RTC) with fully compatible

1-Wire® MicroLAN interface

§ Uses the same binary time/date representation

as the DS2404 but with 1 second resolution

§ Clock accuracy ±2 minutes per month

at 25°C

6-PIN TSOC PACKAGE

1
2
3

TOP VIEW

6
5
4

§ Programmable interrupt output for system

wakeup

§ Communicates at 16.3kbits per second

§ Unique, factory-lasered and tested 64-bit reg-

istration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures ab-

SIDE VIEW

See Mech. Drawings

Section

solute traceability because no two parts are
alike

§ 8-bit family code specifies device communi-

cation requirements to bus master

§ Built-in multidrop controller ensures com-

patibility with other MicroLAN products

§ Operates over a wide VDD voltage range of

2.5V to 5.5V from -40°C to +85°C

§ Low power, 200nA typically with oscillator

PIN DESCRIPTION

Pin 1 GND
Pin 2 1-Wire
Pin 3

Pin 4 V
Pin 5 X1
Pin 6 X2

INT

DD

running

§ Compact, low cost 6-pin TSOC surface

mount package

ORDERING INFORMATION

DS2417P 6-pin TSOC package
DS2417P/T&R Tape & Reel of DS2417P
DS2417X Chip Scale Pkg., Tape &

Reel

DESCRIPTION

The DS2417 1-Wire Time Chip with Interrupt offers a simple solution for storing and retrieving vital
time information with minimal hardware. The DS2417 contains a unique lasered ROM and a real-time
clock/calendar implemented as a binary counter. Only one pin is required for communication with the
device. Utilizing a backup energy source, the data is nonvolatile and allows for stand-alone operation.
The DS2417 features can be used to add functions such as calendar, time and date stamp, and logbook to
any type of electronic device or embedded application that uses a microcontroller.

OVERVIEW

The DS2417 has two main data components: 1) 64-bit lasered ROM, and 2) real-time clock counter
(Figure 1). The real-time clock utilizes an on-chip oscillator that is connected to an external 32.768kHz
crystal. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first
provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip
ROM. The protocol for these ROM functions is described in Figure 7. After a ROM function command

1 of 15 111901

DS2417

is successfully executed, the real-time clock functions become accessible and the master may then
provide one of the real-time clock function commands. The protocol for these commands is described in
Figure 5. All data is read and written least significant bit first.

DETAILED PIN DESCRIPTION

PIN SYMBOL DESCRIPTION

1 GND

Ground Pin

21-WireData input/output Open drain.
3

INT

Interrupt pin Open drain.

4VDDPower input pin. 2.5V to 5.5V.

5, 6 X1, X2

Crystal pins. Connections for a standard 32.768kHz quartz crystal, EPSON part
number C-002RX or C-004R (be sure to request 6pF load capacitance).
NOTE: X1 and X2 are very high impedance nodes. It is recommended that they
and the crystal be guard-ringed with ground and that high frequency signals be
kept away from the crystal area. See Figure 10 and Application Note 58 for de­tails.

BLOCK DIAGRAM Figure 1

1-WIRE

ROM

FUNCTION

CONTROL

64-BIT

LASERED

ROM

CLOCK

FUNCTION

CONTROL

READ/WRITE BUFFER

INT. GENERATOR

RTC COUNTER (32-BIT)

V

DD

OSCILLATOR

CONTROL

32.768 kHz

OSC./DIVIDER

X1 X2

INT\

INT

1 Hz

64-BIT LASERED ROM

Each DS2417 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton
Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the
family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the
serial number is entered. After the 48th bit of the serial number has been entered, the shift register
contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros. The

®

2 of 15

DS2417

64-bit ROM and ROM Function Control section allow the DS2417 to operate as a 1-Wire device and
follow the 1-Wire protocol detailed in the section "1-Wire Bus System".

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

Bus

Master

Command
Level

1-Wire ROM Function

Commands (see Figure 7)

DS2417 specific

Function Commands

(see Figure 5)

1-Wire Bus

DS2417

Available
Commands

Read ROM
Match ROM
Search ROM
Skip ROM

Write Clock
Read Clock

Other

Devices

Data Fields
Affected

64-bit ROM
64-bit ROM
64-bit ROM
N/A

RTC Counter, Device Control
RTC Counter, Device Control

64-BIT LASERED ROM Figure 3

MSB LSB

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (27h)

MSB LSB MSB LSB MSB LSB

1-WIRE CRC GENERATOR Figure 4

Polynomial = X8 + X5 + X4 + 1

0

X

1ST

STAGE

STAGE

1

X

2ND

2

X

3RD

STAGE

3

X

4TH

STAGE

5TH

STAGE

4

X

3 of 15

5

X

R

6TH

STAGE

S

7TH

STAGE

6

X

INPUT DATA

7

X

8TH

STAGE

8

X

DS2417

TIMEKEEPING

A 32.768kHz crystal oscillator is used as the time base for the real-time clock counter. The oscillator can
be turned on or off under software control. The oscillator must be on for the real-time clock to function.
The real-time clock counter is double buffered. This allows the master to read time without the data
changing while it is being read. To accomplish this, a snapshot of the counter data is transferred to a
read/write buffer, which the user accesses.

DEVICE CONTROL BYTE

The DS2417 can generate interrupt pulses to trigger activities that have to occur at regular intervals. The
selection of this interval and the on/off control of the 32.768kHz crystal oscillator are done through the
device control byte. This byte can be read and written through the Clock Function commands.

Device Control Byte

76543210

IE IS2 IS1 IS0

OSC

OSC 0 0

Bit 0 - 1

Bits 0 and 1 are hard-wired to read all 0’s.

Bit 2 - 3

These bits control/report whether the 32.768kHz crystal oscillator is running. If the oscillator is running,
both OSC bits will read 1. If the oscillator is turned off these bits will all read 0. When writing the
device control byte both occurrences of the OSC bit should have identical data. Otherwise, the value in
bit address 3 (bold) takes precedence.

Bit 4 - 6

These bits determine the time between interrupt pulses. The values available are shown below.

IS2 IS1 IS0 Interrupt Interval

0001s
0014s
0 1 0 32s = 0.53 min.
0 1 1 64s = 1.07 min.
1 0 0 2048s = 34.13 min.
1 0 1 4096s = 68.27 min.
1 1 0 65536s = 18.20 hours
1 1 1 131072s = 36.41 hours

0 No function

OSC Oscillator Enable/Disable

IS Interval Select

Bit 7

This bit controls whether the interrupt pulse will be generated at the selected interval. To enable
interrupts this bit needs to be 1.

IE Interrupt Enable

4 of 15

DS2417

REAL-TIME CLOCK

The real-time clock is a 32-bit binary counter. It is incremented once per second. The real-time clock
can accumulate 136 years of seconds before rolling over. Time/date is represented by the number of
seconds since a reference point, which is determined by the user. For example, 12:00 a.m., January 1,
1970 could be a reference point.

CLOCK FUNCTION COMMANDS

The “Clock Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the real-time
clock. With only four bytes of real-time clock and one control byte the DS2417 does not provide random
access. Reading and writing always starts with the device control byte followed by the least significant
byte of the time data.

READ CLOCK [66h]

The read clock command is used to read the device control byte and the contents of the real-time clock
counter. After having received the most significant bit of the command code the device copies the actual
contents of the real-time clock counter to the read/write buffer. Now, the bus master reads data beginning
with the device control byte followed by the least significant byte through the most significant byte of the
real-time clock. After this the bus master may continue reading from the DS2417. The data received will
be the same as in the first pass through the command flow. The read clock command can be ended at any
point by issuing a Reset Pulse.

WRITE CLOCK [99h]

The write clock command is used to set the real-time clock counter and to write the device control byte.
After issuing the command, the bus master writes first the device control byte, which becomes immedi­ately effective. After this the bus master sends the least significant byte through the most significant byte
to be written to the real-time clock counter. The new time data is copied from the read/write buffer to the
real-time clock counter and becomes effective as the bus master generates a reset pulse. If enabled, an
interrupt pulse will be generated either immediately or delayed, depending on the actual time and the se­lected interval duration (see Figure 11). If the oscillator is intentionally stopped the real-time clock coun­ter behaves as a four-byte nonvolatile memory.

5 of 15

CLOCK FUNCTION COMMAND FLOW CHART Figure 5

Master TX Control
Function Command

DS2417

66H

Read Clock

?

Y

DS2417 copies

RTC Counter
to R/W Buffer

Bus Master RX

Device Control Byte

Bus Master RX

LS Byte (7:0)

Bus Master RX

next Byte (15:8)

Bus Master RX
next Byte (23:16)

N

Device Control Byte

99H

Write Clock

?

Y

Bus Master TX

Bus Master TX

LS Byte (7:0)

Bus Master TX

next Byte (15:8)

Bus Master TX
next Byte (23:16)

Bus Master TX

MS Byte (31:24)

N

Bus Master RX

MS Byte (31:24)

N

Bus Master

TX Reset

?

Y

N

Bus Master

TX Reset

?

Y

DS2417 copies

R/W Buffer

to RTC Counter

DS2417 TX

Presence Pulse

N

Bus Master

TX Reset

?

Y

6 of 15

HARDWARE CONFIGURATION Figure 6

BUS MASTER

V

PUP

DS2417

DS2417 1-WIRE PORT

RX

TX

Open Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT

5 k W
Typ.

5 µA

Typ.

DATA

RX

TX

100 W

MOSFET

1-WIRE BUS SYSTEM

The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the
DS2417 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire input of the DS2417 is open drain with an internal circuit equivalent
to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The
1-Wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approxi­mately 5kW.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120ms, one or more of the devices on the bus may be reset. Since the DS2417 gets all its
energy for operation through its VDD pin it will NOT perform a power-on reset if the 1-Wire bus is low
for an extended time period.

TRANSACTION SEQUENCE

The protocol for accessing the DS2417 via the 1-Wire port is as follows:

§ Initialization

§ ROM Function Command

§ Clock Function Command

7 of 15

DS2417

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence con­sists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2417 is on the bus and is ready to
operate. For more details, see the “1-Wire Signaling” section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the four ROM function commands that
the DS2417 supports. All ROM function commands are eight bits long. A list of these commands
follows (refer to flowchart in Figure 7):

Read ROM [33h]

This command allows the bus master to read the DS2417’s 8-bit family code, unique 48-bit serial num­ber, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than
one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read
by the master will be invalid.

Match ROM [55h]

The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a spe­cific DS2417 on a multidrop bus. Only the DS2417 that exactly matches the 64-bit ROM sequence will
respond to the following clock function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the
bus.

SEARCH ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1­Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the de­sired value of that bit. The bus master performs this three-step routine on each bit of the ROM. After one
complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify
the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a
comprehensive discussion of a search ROM, including an actual example.

Skip ROM [CCh]

This command can save time in a single drop bus system by allowing the bus master to access the clock
functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for
example, a read command is issued following the Skip ROM command, data collision will occur on the
bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result).

8 of 15

ROM FUNCTIONS FLOW CHART Figure 7

y

y

y

(

)

Reset Pulse

DS2417 TX

Presence P ulse

Master TX ROM

Function Command

DS2417

Master TX

33H

Read ROM

Command

?

Y

DS2417 TX

Family Code

1 B

te

DS2417 TX

Serial Number

tes

6 B

N

55H

Match ROM

Command

Master TX Bit 0

Bit 0

Match ?

Master TX Bit 1

Bit 1

Match ?

N

?

Y

NN

Y

NN

F0H

Search ROM

Command

?

Y

DS2417 TX Bit 0
DS2417 TX Bit 0
Master TX Bit 0

Bit 0

Match ?

Y
DS2417 TX Bit 1
DS2417 TX Bit 1
Master TX Bit 1

Bit 1

Match ?

N

CCH
Skip ROM
Command

?

Y

N

Y

DS2417 TX Bit 63

DS2417 TX

CRC B

te

Master TX Bit 63

Bit 63

Match ?

Y

NN

DS2417 TX Bit 63
Master TX Bit 63

Master TX Control
Function Comm and

SEE FIGURE 5

9 of 15

Y

Bit 63

Match ?

Y

DS2417

1–WIRE SIGNALING

The DS2417 requires strict protocols to ensure data integrity. The protocol consists of four types of sig­naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read
Data. Except for the presence pulse the bus master initiates all these signals.

The initialization sequence required to begin any communication with the DS2417 is shown in Figure 8.
A reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. The bus
master transmits (TX) a reset pulse (t

, minimum 480ms). The bus master then releases the line and

RSTL

goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data line, the DS2417 waits (t
presence pulse (t

, 60µs to 240µs).

PDL

, 15µs to 60µs) and then transmits the

PDH

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

MASTER TX

"RESET PULSE"

t

RSTL

MASTER RX "PRESENCE PULSE"

t

RSTH

t

R

t

PDH

t

PDL

RESISTOR

MASTER

DS2417

480 µs £ t

480 µs £ t

15 µs £ t

60 £ t

PDL

* In order not to mask interrupt signaling by other devices on the 1-Wire bus t

< ¥*

RSTL

< ¥**

RSTH

< 60 µs

PDH

< 240 µs

+ tR should al-

RSTL

ways be less than 960µs.

** Includes recovery time

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots
by driving the data line low. The falling edge of the data line synchronizes the DS2417 to the master by
triggering an internal delay circuit. During write time slots, the delay circuit determines when the
DS2417 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2417 will hold the data line low. If the data bit is a “1”, the DS2417 will not
hold the data line low at all.

10 of 15

READ/WRITE TIMING DIAGRAM Figure 9

Write-one Time Slot

t

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

t

LOW1

(OD: 2µs)

15µs

SLOT

DS2417

Sampling Window

60µs

(OD: 6µs)

t

REC

DS2417

RESISTOR

MASTER

Write-zero Time Slot

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

RESISTOR

MASTER

60 µs £ t

1 µs £ t

1 µs £ t

15µs

(OD: 2µs)

60 µs £ t

1 µs £ t

< 120 µs

SLOT

< 15 µs

LOW1

¥

<

REC

t

SLOT

DS2417

Sampling Window

(OD: 6µs)

60µs

t

LOW0

< t

LOW0

REC

<

SLOT

¥

< 120 µs

t

REC

11 of 15

READ/WRITE TIMING DIAGRAM (continued) Figure 9

Read-data Time Slot

t

Master

SLOT

t

RELEASE

60 µs £ t

1 µs £ t

0 £ t

1 µs £ t
t
t

V

PULLUP

V

PULLUP MIN

V

IH MIN

V

IL MAX

0V

RESISTOR

MASTER

DS2417

t

t

LOWR

Sampling Window

SU

t

RDV

RDV

SU

< 1 µs

t

REC

SLOT

LOWR

RELEASE

REC

= 15 µs

< 120 µs

< 15 µs

< 45 µs

¥

<

DS2417

CRYSTAL PLACEMENT ON PCB Figure 10

LOCAL GROUND

PLANE BENEATH
SIGNAL PLANE
OR ON OTHER

SIDE OF PCB

GND

1-Wire

INT\

V

X1

X2

DD

CRYSTAL

PADS

GUARD RING

ON SIGNAL

PLANE

12 of 15

INTERRUPT TIMING Figure 11

V

INT

Case A: Latency < 0.5

t

INTERVAL

DS2417

t

LATENCY

V

INT

t

LATENCY

Case B: 0 < Latency <

t

INTERVAL

t

t

INTERVAL

INTERVAL

t

PULSE

t

PULSE

= 122 µs

= 122 µs

Time

Time

The latency depends on the selected interrupt interval (IS0 to IS2 settings) and the contents of the RTC
counter at the time of writing the device control byte. In Case A, the flip-flop that determines the interval
duration is reset and toggles before half of the interval time is over. In Case B, this flip-flop is set that
generates an immediate interrupt pulse; the latency, therefore, can be up to one full interval duration.

If enabled, the interrupt pulse may also be triggered while reading from or writing to the control byte.

13 of 15

DS2417

ABSOLUTE MAXIMUM RATINGS*

Voltage on 1-Wire to Ground -0.5V to +7.0V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See J-STD-020A Specification

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to abso­lute maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS

(V

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 V
Logic 0 V
Output Logic Low @ 4mA V
Output Logic High V
Input Load Current I
Interrupt Sink Current
@ 0.4V
Operating Current (Osc. On) I
Quiescent Current (Osc. Off) I
Interrupt Sink Current
@ 0.4V
Operating Current (Osc. On) I
Quiescent Current (Osc. Off) I

= 2.5V to 6.0V; VDD = 2.5V to 5.5V, -40°C to +85°C)

PUP

IH1

IL1

OL1

OH1

L1

I

INT3

DD3

DDQ3

I

INT5

DD5

DDQ5

2.2 6.0 V 1, 11

-0.3 TBD V 1, 6

0.4 V 1

V

PUP

V 1, 3

5 µA4

5mA9

250 nA 2, 9

50 nA 2, 8, 9

10 mA 10

450 nA 2, 10
100 nA 2, 8, 10

CAPACITANCE (TA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance 1-Wire C

IN

50 pF

AC ELECTRICAL CHARACTERISTICS

(V

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Time Slot t
Write 1 Low Time t
Write 0 Low Time t
Read Low Time t
Read Data Valid t
Release Time t
Read Data Setup t
Recovery Time t
Reset High Time t
Reset Low Time t
Presence Detect High t
Presence Detect Low t

= 2.5V to 6.0V; VDD = 2.5V to 5.5V, -40°C to +85°C)

PUP

SLOT

LOW1

LOW0

LOWR

RDV

RELEASE

SU

REC

RSTH

RSTL

PDH

PDL

60 120 µs

115µs13

60 120 µs

115µs13

15 µs12

01545µs

1 µs5

1 µs
480 µs
480 960 µs7

15 60 µs
60 240 µs

14 of 15

DS2417

NOTES:

1. All voltages are referenced to ground.

2. Measured with outputs open.

3. V

4. Input load is to ground.

5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

6. Under certain low voltage conditions V

7. The reset low time (t

8. When VDD ramps up, the oscillator is always off.

9. At VDD = 3V ± 10%

10. At V

11. V

12. The optimal sampling point for the master is as close as possible to the end time of the 15µs t

13. The duration of the low pulse sent by the master should be a minimum of 1µs with a maximum value

= external pullup voltage.

PUP

guaranteed to be valid within 1 µs of this falling edge.

IL1MAX

may have to be reduced to as much as 0.5V to always

guarantee a presence pulse.

) should be restricted to a maximum of 960µs, to allow interrupt signaling,

RSTL

otherwise, it could mask or conceal interrupt pulses.

= 5V ± 10%

DD

has to be VDD – 0.3V or higher.

IH1

RDV

period without exceeding t

. For the case of a Read-One Time Slot, this maximizes the amount of

RDV

time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a
read will occur before the fastest 1-Wire device(s) release the line.

as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.

15 of 15