Rainbow Electronics DS2182A User Manual
DS218A
DS2182A
T1 Line Monitor
FEATURES
• Performs framing and monitoring functions
• Supports Superframe and Extended Superframe
formats
• Four onboard error counters
– 16-bit bipolar violation
– 8-bit CRC
– 8-bit OOF
– 8-bit frame bit error
• Indication of the following
– yellow and blue alarms
– incoming B8ZS code words
– 8 and 16 zero strings
– change of frame alignment
– loss of sync
– carrier loss
• Simple serial interface used for configuration, control
and status monitoring
• Burst mode allows quick access to counters for status
updates
• Automatic counter reset feature
• Single 5V supply; low-power CMOS technology
• Available in 28-pin DIP and 28-pin PLCC
PIN ASSIGNMENT
INT
SDI
SDO
CS
SCLK
NC
RYEL
RLINK
RLCLK
RCLK
RCHCLK
RSER
NC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
28-Pin DIP (600 MIL)
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
The updated DS2182A includes the following changes
from the original DS2182:
• ability to count excessive zeros
• Severely Errored Framing Event indication
• updated AIS detection
• updated RCL detection
• AIS and RCL alarm clear indications
• The DS2182A is upward-compatible from the original
DS2182
DESCRIPTION
The DS2182A T1 Line Monitor Chip is a monolithic
CMOS device designed to monitor real-time performance on T1 lines. The DS2182A frames to the data on
the line, counts errors, and supplies detailed information about the status and condition of the line. Large onboard counters allow the accumulation of errors for ex-
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
tended periods, which permits a single CPU to monitor a
number of T1 lines. Output clocks that are synchronized
to the incoming data stream are provided for easy extraction of S-Bits, FDL bits, signaling bits, and channel
data. The DS2182A meets the requirements of ANSI
T1.231.
041995 1/22
DS2182A
DS2182A BLOCK DIAGRAM Figure 1
CS
SCLK
SDI
INT
SDO
RYEL
RSER
RABCD
RLINK
SERIAL
PORT
INTERFACE
YELLOW
ALARM
DETECT
DATA
DEMUX
INFORMATION REGISTERS
RECEIVE
SYNC
CONTROLLER
BIPOLAR
DECODER
RST
TEST
V
DD
V
SS
RLOS
RCL
RBV
RPOS
RNEG
RLCLK
RSIGFR
RSIGSEL
RCHCLK
RMSYNC
RFSYNC
041995 2/22
RECEIVE
TIMING
RCLK
CRC
SYNCHRONIZER
RFER
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
6 NC – No Connect. No internal connection. This pin can be tied to either V
7 RYEL O Receive Yellow Alarm. Transitions high when yellow alarm detected;
8 RLINK O Receive Link Data. Updated with extracted FDL data one RCLK before
9 RLCLK O Receive Link Clock. 4 KHz demand clock for RLINK.
10 RCLK I Receive Clock. 1.544 MHz primary clock.
11 RCHCLK O Receive Channel Clock. 192 KHz clock; identifies time slot (channel)
12 RSER O Receive Serial Data. Received NRZ serial data; updated on rising edges
13 NC - No Connect. No internal connection. This pin can be tied to either V
15 RFSYNC O Receive Frame Sync. Extracted 8 KHz clock, one RCLK wide; F-bit posi-
16 RMSYNC O Receive Multiframe Sync. Extracted multiframe sync; positive-going
17 RABCD O Receive ABCD Signaling. Extracted signaling data output; valid for each
18 RSIGFR O Receive Signaling Frame. High during signaling frames; low during
19 RSIGSEL O Receive Signaling Select. In 193E framing, a .667 KHz clock that identi-
21 RST I Reset. A high-low transition clears all internal registers and resets count-
22
23
RPOS
RNEG
24 RCL O Receive Carrier Loss. High if 192 consecutive 0s appear at RPOS and
25 RBV O Receive Bipolar Violation. High during accused bit time at RSER. If
26 RFER O Receive Frame Error. High during F-bit time when FT or FS errors occur
27 RLOS O Receive Loss of Sync. Indicates sync status; high when internal resync
or VDD, or it can be floated.
goes low when alarm clears.
start of odd frames (193E) and held until next update. Updated with extracted S-bit data one RCLK before start of even frames (193S) and held
until next update.
boundaries.
of RCLK.
or VDD, or it can be floated.
tion in each frame.
edge indicates start of multiframe; 50% duty cycle.
channel in signaling frames. In non-signaling frames, RABCD outputs
the LSB of each channel word.
non-signaling frames (and during resync).
fies signaling frames A and C; a 1.33 KHz clock in 193S.
ers. A high-low-high transition initiates a resync.
I Receive Bipolar Data Inputs. Sampled on falling of RCLK. Tie together
to receive NRZ data and disable bipolar violation monitoring circuitry.
RNEG; goes low upon seeing 12.5% one’s density .
bipolar violation detected, low otherwise.
(193S), or when FPS or CRC errors occur (193E). Low during resync.
is in progress, low otherwise.
DS2182A
SS
SS
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DS2182A
PORT PIN DESCRIPTION Table 2
PIN SYMBOL TYPE DESCRIPTION
1 INT O Receive Alarm Interrupt. Flags host controller during alarm conditions.
Active low; open drain output.
2 SDI I Serial Data In. Data for onboard registers. Sampled on rising edge of
SCLK.
3 SDO O Serial Data Out. Control and status information from onboard registers.
Updated on falling edge of SCLK; tri-stated during serial port write or
when CS
is high.
4 CS I Chip Select. Must be low to read or write the serial port.
5 SCLK I Serial Data Clock. Used to read or write the serial port registers.
POWER AND TEST PIN DESCRIPTION Table 3
PIN SYMBOL TYPE DESCRIPTION
14 V
SS
– Signal Ground. 0.0 volts.
20 TEST I T est Mode. Tie to VSS for normal operation.
28 V
DD
– Positive Supply. 5.0 volts.
REGISTER SUMMARY Table 4
REGISTER ADDRESS DESCRIPTION/FUNCTION
BVCR2 0000 Bipolar Violation Count Register 2. LSW of a 16-bit presettable counter
BVCR1 0001 Bipolar Violation Count Register 1. MSW of a 16-bit presettable count-
CRCCR 0010 CRC Error Count Register. 8-bit presettable counter that records CRC6
OOFCR 0011 OOF Count Register. 8-bit presettable counter that records OOF events.
FECR 0100 Frame Error Count Register. 8-bit presettable counter that records indi-
RSR1 0101 Receive Status Register 1. Reports alarm conditions.
RIMR1 0110 Receive Interrupt Mask Register 1. Allows masking of individual alarm-
RSR2 0111 Receive Status Register 2. Reports alarm conditions.
RIMR2 1000 Receive Interrupt Mask Register 2. Allows masking of individual alarm-
RCR1 1001 Receive Control Register 1. Programs device operating characteristics.
RCR2 1010 Receive Control Register 2. Programs device operating characteristics.
that records individual bipolar violations.
er that records individual bipolar violations.
errored words in the 193E frame mode.
OOF events are defined by RCR1.5 and RCR1.6.
vidual bit errors in the framing pattern.
generated interrupts from RSR1.
generated interrupts from RSR2.
041995 4/22
DS2182A
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven onboard registers allow the user to update operational
characteristics and monitor device status via a host controller, minimizing hardware interfaces. The port on the
DS2182A can be read from or written to at any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG. However, RCLK
is needed in order to clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
Reading or writing the control, configuration or status
registers requires writing one address/command byte
prior to transferring register data. The first bit written
(LSB) of the address/command word specifies register
read or write. The following four bits identify the register
address. The next two bits are reserved and must be set
to 0 for proper operation. The last bit of the address/
command word enables burst mode when set; the burst
mode causes all registers to be consecutively read or
written to. Data is read and written to the DS2182A LSB
first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input
low. Input data is latched on the rising edge of SCLK and
must be valid during the previous low period of SCLK to
prevent momentary corruption of register data during
writes. Data is output on the falling edge of SCLK and
held to the next falling edge. All data transfers are terminated if the CS
is disabled and SDO is tri-stated when CS is high.
input transitions high. Port control logic
DATA I/O
Following the eight SCLK cycles that input an address/
command byte to write, a data byte is strobed into the
addressed register on the rising edge of the next eight
SCLK cycles. Following an address/command word to
read, contents of the selected register are output on the
falling edges of the next eight SCLK cycles. The SDO
pin is tri-stated during device write and can be tied to
SDI in applications where the host processor has a bidirectional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively written to or read by the host processor. A
burst read is used to poll all registers; RSR1 and RSR2
contents will be unaffected. This feature minimizes device initialization time on system power-up or reset.
Burst mode is initiated when ACB.7 is set and the address is 0000. A burst is terminated by a low-high transition on CS
.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
BM
SYMBOL POSITION NAME AND DESCRIPTION
BM ACB.7 Burst Mode. If set (and register address is 0000) burst read or write is en-
- ACB.6 Reserved, must be 0 for proper operation.
- ACB.5 Reserved, must be 0 for proper operation.
ADD3 ACB.4 MSB of register address.
ADD0 ACB.1 LSB of register address.
R/W ACB.0 Read/Write Select.
– – ADD3 ADD2 ADD1 ADD0 R/W
abled.
0 = write addressed register
1 = read addressed register
041995 5/22
DS2182A
SERIAL PORT READ/WRITE Figure 3
CS
SCLK
SDI
SDO
R/W A0 A1 A2 A3 0 0 BM D0 D1 D2 D3 D4 D5 D6 D7
ADDRESS/COMMAND DATA INPUT/OUTPUT
NOTES:
1. SDI is sampled on rising edge of SCLK.
2. SDO is updated on falling edge of SCLK.
OPERATION OF THE COUNTERS
All four of the counters in the DS2182A can be preset by
the user to establish an event count interrupt threshold.
The counters count up from the preset value until they
reach saturation. At saturation, each additional event
reading all of the registers or only the counters. If
RCR1.4 is set, then any read of the registers, burst
mode or not, will clear the count in all four counters. If the
user wishes to read the port and not clear the counters,
then RCR1.4 must be cleared first.
occurrence sets the appropriate bit in RSR2 and generates an interrupt if enabled by RIMR2.
The counter registers can be read or written to at any
time with the serial port, which operates totally asynchThe DS2182A contains an auto counter reset feature in
the burst read mode. If RCR1.4 is set, then the user can
burst read the four counters (five registers), and all four
counters will be automatically reset to 0 after the read
takes place. Since the burst mode can be terminated at
any time by taking CS
high, the user has the option of
ronously with the monitoring of the T1 line. Reading a
register will not affect the count as long as RCR1.4 is
cleared. The dual buffer architecture of the DS2182A in-
sures that no error events will be missed while the serial
port is being accessed for reads.
BVCR1: BIPOLAR VIOLATION COUNT REGISTER 1;
BVCR2: BIPOLAR VIOLATION COUNT REGISTER 2 Figure 4
(MSB) (LSB)
BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0
SYMBOL POSITION NAME AND DESCRIPTION
BV7 BVCR.7 MSB of bipolar violation count
BV0 BVCR.0 LSB of bipolar violation count
Bipolar Violation Count Register 1 (BVCR1) is the most
significant word and BVCR2 is the least significant word
of a presettable 16-bit counter that records individual bipolar violations. If the B8ZS mode is enabled (RCR2.2 =
1), then B8ZS code words are not counted. The BVCR
can also be programmed to count excessive zeros by
count occurrences of 8 consecutive zeros when B8ZS is
enabled or 16 consecutive zeros when B8Z5 is dis-
abled. This counter increments at all times and is not
disabled by a loss of sync condition (RLOS = 1). The
counter saturates at 65,535 and generates an interrupt
for each occurrence after saturation if RIMR2.0 is set.
setting the RCR2.5 bit. In this mode, the BVCR will
NOTE:
1. In order to properly preset the Bipolar Violation Count Register, BVCR2 must be written to before BVCR1 is
written to.
041995 6/22
CRCCR: CRC COUNT REGISTER Figure 5
(MSB) (LSB)
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
SYMBOL POSITION NAME AND DESCRIPTION
CRC7 CRCCR.7 MSB of CRC6 word error count
CRC0 CRCCR.0 LSB of CRC6 word error count
DS2182A
The CRC Count Register (CRCCR) is an 8-bit presettable counter that records word errors in the Cyclic Redundancy Check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each
in this register is only valid in the 193E framing mode
(RCR2.4 = 1) and is reset and disabled in the 193S framing mode (RCR2.4 = 0). The count is disabled during a
loss of sync condition (RLOS = 1).
occurrence after saturation if RIMR2.1 is set. The count
OOFCR: OOF COUNT REGISTER Figure 6
(MSB) (LSB)
OOF7
OOF6 OOF5 OOF4 OOF3 OOF2 OOF1 OOF0
SYMBOL POSITION NAME AND DESCRIPTION
OOF7 OOFCR.7 MSB of OOF event count
OOF0 OOFCR.0 LSB of OOF event count
The OOF Count Register (OOFCR) is an 8-bit presettable counter that records Out Of Frame (OOF) events.
OOF events are defined by RCR1.5 and RCR1.6. This
rupt for each occurrence after saturation if RIMR2.2 is
set. The count is disabled during a loss of sync condition (RLOS = 1).
8-bit counter saturates at 255 and generates an inter-
FECR: FRAME ERROR COUNT REGISTER Figure 7
(MSB) (LSB)
FE7
SYMBOL POSITION NAME AND DESCRIPTION
FE7 FECR.7 MSB of frame error count
FE0 FECR.0 LSB of frame error count
FE6 FE5 FE4 FE3 FE2 FE1 FE0
The Frame Error Count Register (FECR) is an 8-bit presettable counter that records individual frame bit errors.
In the 193E mode (RCR2.4 = 1), the FECR records bit
errors in the FPS framing pattern (001011). In the 193S
mode (RCR2.4 = 0), the FECR records bit errors in both
the FT (101010) and FS (001110) framing patterns if
RCR1.3 is set. If RCR1.3 is cleared, then the FECR only
records bit errors in the FT pattern. This 8-bit counter
saturates at 255 and generates an interrupt for each occurrence after saturation if RIMR2.3 is set. The count is
disabled during a loss of sync condition (RLOS = 1).
041995 7/22
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