Rainbow Electronics DS2181A User Manual
DS2181A
DS2181A
CEPT Primary Rate Transceiver
FEATURES
• Single–chip primary rate transceiver meets CCITT
standards G.704, G.706 and G.732
• Supports new CRC4-based framing standards and
CAS and CCS signalling standards
• Simple serial interface used for device configuration
and control in processor mode
• Hardware mode requires no host processor;
intended for stand-alone applications
• Comprehensive, on-chip alarm generation, alarm
detection, and error logging logic
• Shares footprint with DS2180A T1 Transceiver
• Companion to DS2175 T1/CEPT Elastic Store,
DS2186 Transmit Line Interface, DS2187 Receive
Line Interface, and DS2188 Jitter Attenuator
• 5V supply; low-power CMOS technology
DESCRIPTION
The DS2181A is designed for use in CEPT networks
and supports all logical requirements of CCITT Red
Book Recommendations G.704, G.706 and G.732. The
transmit side generates framing patterns and CRC4
codes, formats outgoing channel and signalling data,
and produces network alarm codes when enabled. The
receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4 multiframe
alignments. Once synchronized, the device extracts
channel, signalling, and alarm data.
A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode, a host
processor controls features such as error logging, perchannel code manipulation, and alteration of the receive
synchronizer algorithm.
PIN ASSIGNMENT
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
40-Pin DIP (600 MIL)
RFSA
TCHCLK
TCLK
6543214443424140
TSER
7
TMO
8
TXD
9
TSTS
10
11
TSD
12
TIND
TAF
TPOS
TNEG
INT
SDI
13
14
15
16
17
44-PIN PLCC
18 19 20 21 22 23 24 25 26 27 28
CS
SDO
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
RMSA
TFSYNC
TMSYNC
VDD
SPS
VSS
RRA
RDMA
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RLOS
RCTO
RFER
RAF
VDD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
RCLK
RAF
RDMA
RRA
RBV
RCL
39
38
37
36
35
34
33
32
31
30
29
RCLK
RCSA
RNEG
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSER
RCHCLK
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041995 1/32
DS2181A
The hardware mode is intended for preliminary system
prototyping and/or retrofitting into existing systems.
DS2181A BLOCK DIAGRAM Figure 1
TCLK
TFSYNC
TMSYNC
TSER
TSD
TIND
TXD
SPS
CS
SCLK
SDI
SDO
TRANSMIT
TIMING
SERIAL PORT/
HARDWARE
MODE CONTROL
LOGIC
ALIGN WORD
GENERAT OR
ALARM
GENERAT OR
CONTROL, STATUS AND ALARM
This mode requires no host processor and disables
special features available in the processor mode.
HDB3
CODER
LOOPBACK
REGISTERS
DATA
SELECTOR
TMO
TAF
TSTS
TCHCLK
TPOS
TNEG
INT
RDMA
RBV
RRA
RCL
RFER
RLOS
RSER
RSD
RFSYNC
RMSYNC
RCSYNC
RAF
RSTS
RCHCLK
041995 2/32
ALARM DETECTION
DATA DEMUX
RECEIVE TIMING
RECEIVE
SYNCHRONIZER/
SYNC CONTROLLER
HDB3
DECODER
RPOS
RNEG
RCLK
TEST
RST
VDD
VSS
TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY) Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TMSYNC I Transmit Multiframe Sync. Low-high transition establishes start of CAS and/or
2 TFSYNC I Transmit Frame Sync. Low-high transition every frame period establishes frame
3 TCLK I Transmit Clock. 2.048 MHz primary clock.
4 TCHCLK O Transmit Channel Clock. 256 KHz clock which identifies timeslot boundaries.
5 TSER I Transmit Serial Data. NRZ data input, sampled on falling edges of TCLK.
6 TMO O Transmit Multiframe Out. Output of multiframe counter; high during frame 0, low
7 TXD I Transmit Extra Data. Sampled on falling edge of TCLK during bit times 5, 7, and 8
8 TSTS O Transmit Signalling Timeslot. High during timeslot 16 of every frame, low other-
9 TSD I Transmit Signalling Data. CAS signalling data input; sampled on falling edges of
10 TIND I Transmit International and National Data. Sampled on falling edge of TCLK dur-
11 TAF O Transmit Alignment Frame. High during frames containing the frame alignment
1213TPOS
TNEG
CRC4 multiframe. Can be tied low, allowing internal multiframe counter to run free.
boundaries. Can be tied low, allowing TMSYNC to establish frame boundaries.
Useful for parallel-to-serial conversion of channel data.
otherwise.
of timeslot 16 in frame 0 when CAS signalling is enabled.
wise.
TCLK for insertion into outgoing timeslot 16 when enabled.
ing bit 1 time of timeslot 0 every frame (international) and/or during bit times 4
through 8 of timeslot 0 during non-align frames (national) when enabled.
signal, low otherwise.
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
DS2181A
SYNCHRONIZER STATUS PIN (44–PIN PLCC ONLY) Table 2A
PIN SYMBOL TYPE DESCRIPTION
3 RMSA O Receive Multiframe Search Active. This pin will transition high when the synchro-
nizer searching for the CAS multiframe alignment word is active.
6 RFSA O Receive Frame Search Active. This pin will transition high when the synchronizer
searching for the FAS is active.
25 RCTO O Receive CRC4 Time Out. This pin will transition high when the RCTO counter
reaches its maximum count of 32. The pin will return low when either the
DS2181AQ reaches CRC4 multiframe synchronization, or if CRC4 is disabled via
CRC.2, or if the device is issued a hardware reset via the RST
pin.
28 RCSA O Receive CRC4 Search Active. This pin will transition high when the synchronizer
searching for the CRC4 multiframe alignment word is active.
NOTES:
1. These output status pins are only available on the DS2181AQ.
2. If the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated.
041995 3/32
DS2181A
RECEIVE PIN DESCRIPTION (40–PIN DIP ONLY) Table 2B
PIN SYMBOL TYPE DESCRIPTION
21 RRA O Receive Remote Alarm. Transitions high when alarm detected; returns low when
22 RDMA O Receive Distant Multiframe Alarm. Transitions high when alarm detected; returns
23 RAF O Receive Alignment Frame. High during frames containing the frame alignment
24 RCLK I Receive Clock. 2.048 MHz primary clock.
25 RCHCLK O Receive Channel Clock. 256 KHz clock, identifies timeslot boundaries; useful for
26 RSER O Receive Serial Data. Received NRZ data, updated on rising edges of RCLK.
27 RFSYNC O Receive Frame Sync. Trailing edge indicates start of frame.
28 RMSYNC O Receive Multiframe Sync. Low-high transition indicates start of CAS multiframe;
29 RSD O Receive Signalling Data. Extracted timeslot 16 data; updated on rising edge of
30 RSTS O Receive Signalling Timeslot. High during timeslot 16 of every frame, low other-
31 RCSYNC O Receive CRC4 Sync. Low-high transition indicates start of CRC4 multiframe; held
33 RST I Reset. Must be asserted during device power-up and when changing to/from the
3435RPOS
RNEG
36 RCL O Receive Carrier Loss. Low-high transition indicates loss of carrier.
37 RBV O Receive Bipolar Violation. Pulses high during detected bipolar violations.
38 RFER O Receive Frame Error . Pulses high when frame alignment, CAS multiframe align-
39 RLOS O Receive Loss of Sync. Indicates synchronizer status; high when frame, CAS and/
alarm cleared.
low when alarm cleared.
signal, low otherwise.
serial-to-parallel conversion of channel data.
held high during frame 0.
RCLK.
wise.
high during CRC4 frames 0 thru 7 and held low during frames 8 through 15.
hardware mode.
I Receive Bipolar Data. Sampled on falling edges of RCLK. Tie together to receive
NRZ data and disable BPV monitor circuitry.
ment or CRC4 words received in error.
or CRC4 multiframe search underway, low otherwise.
PORT PIN DESCRIPTION (40–PIN DIP ONLY) Table 3
PIN SYMBOL TYPE DESCRIPTION
14 INT O Receive Alarm Interrupt. Flags host controller during alarm conditions. Active low;
15 SDI I Serial Data In. Data for on-chip control registers; sampled on rising edge of SCLK.
16 SDO O Serial Data Out. Control and status data from on-chip registers. Updated on falling
17 CS I Chip Select. Must be low to write or read the serial port.
18 SCLK I Serial Data Clock. Used to write or read the serial port registers.
19 SPS I Serial Port Select. Tie to VDD to select the serial port. Tie to VSS to select the
041995 4/32
open drain output.
edge of SCLK; tri-stated during port write or when CS
hardware mode.
is high.
POWER AND TEST PIN DESCRIPTION (40–PIN DIP ONLY) T able 4
PIN SYMBOL TYPE DESCRIPTION
20 V
SS
– Signal Ground. 0.0 volts.
32 TEST I Test Mode. Tie to VSS to select the old DS2181 sync algorithm and to tri–
state the synchronizer status pins on the DS2181AQ. Tie to V
new DS2181A sync algorithm and activate the synchronizer status pins on the
to select the
DD
DS2181AQ.
40 V
DD
– Positive Supply. 5.0 volts.
REGISTER SUMMARY Table 5
REGISTER ADDRESS T/R
RIMR 0000 R Receive Interrupt Mask Register . Allows masking of alarm
RSR 0001 R
BVCR 0010 R Bipolar Violation Count Register . 8-bit presettable counter
CECR 0011 R CRC4 Error Count Register. 8-bit presettable counter which
FECR 0100 R Frame Error Count Register. 8-bit presettable counter which
RCR 0101 R Receive Control Register. Establishes receive side operating
CCR 0110 T/R Common Control Register. Establishes additional operating
TCR 0111 T Transmit Control Register. Establishes transmit side operation
TIR1
TIR2
TIR3
TIR4
1000
1001
1010
1011
TINR 1100 T Transmit International and National Register. When enabled
TXR 1101 T Transmit Extra Register. When enabled via the TCR, contents
1
DESCRIPTION/FUNCTION
generated interrupts.
2
Receive Status Register. Reports all receive alarm conditions.
which records individual bipolar violations.
records individual errors.
logs individual errors in the received frame alignment signal.
characteristics.
characteristics for transmit and receive sides.
characteristics.
T Transmit Idle Registers. Designates which outgoing timeslots
are to be substituted with idle code.
via the TCR, contents inserted into the outgoing national and/or
international bit positions.
inserted into the out going extra bit positions.
DS2181A
NOTES:
1. Transmit or receive side register .
2. RSR is a read-only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
041995 5/32
DS2181A
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/microcontroller-compatible serial port. Fourteen
on-chip registers allow the user to update operational
characteristics and monitor device status via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit
and receive timing, allowing asynchronous reads and/
or writes by the host. The timing set is identical to that of
8051-type microcontrollers operating in serial port
mode 0. For proper operation of the port and the transmit and receive registers, the user should provide TCLK
and RCLK as well as SCLK.
ADDRESS/COMMAND
An address/command byte write must precede any
read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or
write. The following nibble identifies register address.
The next two bits are reserved and must be set to zero
for proper operation. The last bit of the address/command word enables the burst mode when set; the burst
mode allows consecutive reading or writing of all register data. Data is written to and read from the port LSB
first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input
low. Data is sampled on the rising edge of SCLK. Data is
output on the falling edge of SCLK and held to the next
falling edge. All data transfers are terminated and SDO
tri-stated when CS returns to high.
CLOCKS
T o access the serial port registers both TCLK and RCLK
are required along with the SCLK. The TCLK and RCLK
are used to internally access the transmit and receive
registers, respectively. The CCR is considered a receive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/
command byte, data at SDI is strobed into the addressed register on the next eight SCLK cycles (register
write) or data is presented at SDO on the next eight
SCLK cycles (register read). SDO is tri-stated during
writes and may be tied to SDI in applications where the
host processor has bidirectional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This
feature minimizes device initialization time on system
power-up or reset. Burst mode is initiated when ACB.7
is set and the address nibble is 0000.
be read or written during the burst mode. If CS
tions high before the burst is complete, data validity is
not guaranteed.
All registers must
transi-
041995 6/32
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
BM – – ADD3 ADD2 ADD1 ADD0 R/W
SYMBOL POSITION NAME AND DESCRIPTION
BM ACB.7 Burst Mode. If set (and ACB.1 through ACB.4 = 0), burst read or write is
enabled.
– ACB.6 Reserved; must be 0 for proper operation.
– ACB.5 Reserved; must be 0 for proper operation.
ADD3 ACB.4 MSB of register address.
ADD2 ACB.3
ADD1 ACB.2
ADD0 ACB.1 LSB of register address.
R/W ACB.0 Read/Write Select.
0 = Write address register.
1 = Read address register.
SERIAL PORT READ/WRITE Figure 3
DS2181A
CS
SCLK
SDI,SDO
ADD0 ADD1 ADD2 ADD3 0 0 BM D0 D1 D2 D3 D4 D5 D6 D7R/W
ADDRESS/COMMAND DATA INPUT/OUTPUT
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
041995 7/32
DS2181A
TCR: TRANSMIT CONTROL REGISTER Figure 4
(MSB) (LSB)
TUA1 TSS TSM INBS NBS XBS TSA1 ODM
SYMBOL POSITION NAME AND DESCRIPTION
TUA1 TCR.7 Transmit Unframed All 1’s.
0 = Normal operation.
1 = Replace outgoing data at TPOS and TNEG with unframed all 1’s code.
TSS TCR.6 Transmit Signalling Select
0 = Signalling data embedded in the serial bit stream is sampled at TSER
during timeslot 16.
1 = Signalling data is channel associated and sampled at TSD as shown in
Table 6.
TSM TCR.5 Transmit Signalling Mode
0 = Channel Associated Signalling (CAS).
1 = Common Channel Signalling (CCS).
INBS TCR.4 International Bit Select
0 = Sample international bit at TIND.
1 = Outgoing international bit = TINR.7.
NBS TCR.3 National Bit Select
0 = Sample national bits at TIND.
1 = Source outgoing national bits from TINR.4 through TINR.0.
XBS TCR.2 Extra Bit Select
0 = Sample extra bits at TXD.
1 = Source extra bits from TXR.0 through TXR.1 and TXR.3.
TSA1 TCR.1 Transmit Signalling All 1’s
0 = Normal operation.
1 = Force contents of timeslot 16 in all frames to all 1’s.
ODM TCR.0 Output Data Mode
0 = TPOS and TNEG outputs are 100% duty cycle.
1 = TPOS and TNEG outputs are 50% duty cycle.
1
1
NOTE:
1. When the common channel signalling mode is enabled (TCR.5 = 1), the TSD input is disabled internally; all
timeslot 16 data is sampled at TSER.
041995 8/32
CCR: COMMON CONTROL REGISTER Figure 5
(MSB) (LSB)
– TAFP THDE RHDE TCE RCE SAS LLB
SYMBOL POSITION NAME AND DESCRIPTION
– CCR.7 Reserved; must be 0 for proper operation.
TAFP CCR.6 Transmit Align Frame Position
When clear, the CAS multiframe begins with a frame containing the frame
alignment signal. When set, the CAS multiframe begins with a frame not
containing the frame alignment signal.
THDE CCR.5 Transmit HDB3 Enable
0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
RHDE CCR.4 Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.
1 = Incoming data is RPOS and RNEG is HDB3 coded.
TCE CCR.3 Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through 12 and 14
are replaced by CRC4 multiframe alignment and checksum words.
RCE CCR.2 Receive CRC4 Enable
0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe alignment
once frame alignment complete.
SAS CCR.1 Sync Algorithm Select
0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
LLB CCR.0 Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG, and RCLK.
1
DS2181A
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not affect CCS
framing (RCR.5 = 1).
2. CCR is considered a receive register and operates from RCLK and SCLK.
041995 9/32
DS2181A
RCR: RECEIVE CONTROL REGISTER Figure 6
(MSB) (LSB)
– – RSM CMSC CMRC FRC SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
– RCR.7 Reserved; must be 0 for proper operation.
– RCR.6 Reserved; must be 0 for proper operation.
RSM RCR.5 Received Signalling Mode
0 = Channel Associated Signalling (CAS).
1 = Common Channel Signalling (CCS).
CMSC RCR.4 CAS Multiframe Sync Criteria
0 = Declare sync when fixed sync criteria met.
1 = Declare sync when fixed criteria are met and two additional consecutive
valid multiframe alignment signals are detected.
CMRC RCR.3 CAS Multiframe Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if two consecutive timeslot 16 words
have values of 0 in the first four MSB positions (0000xxxx).
FRC RCR.2 Frame Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if bit 2 in timeslot 0 of non-align frames
is received in error on three consecutive occasions.
SYNCE RCR.1 Sync Enable
If clear, the synchronizer will automatically begin resync if error criteria are
met. If high, no auto resync occurs.
RESYNC RCR.0 Resync
When toggled low to high, the receive synchronizer will initiate immediately .
The bit must be cleared, then set again for subsequent resyncs.
CEPT FRAME STRUCTURE
The CEPT frame is made up of 32 8-bit channels (timeslots) numbered from 0 to 31. The frame alignment signal in bit positions 2 through 8 of timeslot 0 of every other
frame is independent of the various multiframe modes
described below. Outputs T AF and RAF indicate frames
which contain the alignment signal. Timeslot 0 of frames
not containing the frame alignment signal is used for
alarm and national data. See the separate DS2181A
CEPT Transceiver Application Note for more details.
CAS SIGNALLING
CEPT networks support Channel Associated Signalling
(CAS) or Common Channel Signalling (CCS). These
041995 10/32
signalling modes are independently selectable for
transmit and receive sides.
CAS (selected when TCR.5 = 0 and/or when RCR.5 = 0)
is a bit-oriented signalling technique which utilizes a
16-frame multiframe. The multiframe alignment signal
(0-hex), extra and alarm bits occupy timeslot 16 of frame
0. Timeslot 16 of the remaining 15 frames is reserved for
channel signalling data. Four signalling bits (A, B, C and
D) are transmitted once per multiframe as shown in Figure 7. Input TMSYNC establishes the transmitted CAS
multiframe position. Signalling data can be sourced
from input TSD (TCR.6 = 1) or multiplexed into TSER
(TCR.6 = 0).
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