Rainbow Electronics DS2180A User Manual
DS2180A
DS2180A
T1 Transceiver
FEATURES
• Single chip DS1 rate transceiver
• Supports common framing standards
– 12 frames/superframe “193S”
– 24 frames/superframe “193E”
• Three zero suppression modes
– B7 stuffing
– B8ZS
– Transparent
• Simple serial interface used for configuration, control
and status monitoring in “processor” mode
• “Hardware” mode requires no host processor; in-
tended for stand-alone applications
• Selectable 0, 2, 4, 16 state robbed bit signaling modes
• Allows mix of “clear” and “non-clear” DS0 channels on
same DS1 link
• Alarm generation and detection
• Receive error detection and counting for transmission
performance monitoring
• 5V supply, low-power CMOS technology
• Surface mount package available, designated
DS2180AQ
• Industrial temperature range of -40°C to +85°C avail-
able, designated DS2180AN or DS2180AQN
• Compatible to DS2186 Transmit Line Interface,
DS2187 Receive Line Interface, DS2188 Jitter Attenuator, DS2175 T1/CEPT Elastic Store, DS2290 T1
Isolation Stik, and DS2291 T1 Long Loop Stik
DESCRIPTION
The DS2180A is a monolithic CMOS device designed to
implement primary rate (1.544 MHz) T -carrier transmission systems. The 193S framing mode is intended to
support existing Ft/Fs applications (12 frames/superframe). The 193E framing mode supports the extended
superframe format (24 frames/superframe). Clear
channel capability is provided by selection of appropriate zero suppression and signaling modes.
PIN ASSIGNMENT
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
40-Pin DIP (600 MIL)
NC
TCHCLK
TCLKNCTFSYNC
TSER
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
6543214443424140
7
TMO
8
9
10
11
12
13
14
15
16
INT
17
SDI
18 19 20 21 22 23 24 25 26 27 28
CS
SDO
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
TMSYNC
VDD
44-PIN PLCC
SPS
VSS
RYEL
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RLOS
NC
RLINK
VDD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
RSER
RCHCLK
RCLK
RLCLK
RLINK
RYEL
RFER
RBV
RCLK
RLCLK
39
38
37
36
35
34
33
32
31
30
29
RCL
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
RSER
RCHCLK
NC
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041995 1/36
DS2180A
Several functional blocks exist in the transceiver. The
transmit framer/formatter generates appropriate framing bits, inserts robbed bit signaling, supervises zero
suppression, generates alarms, and provides output
clocks useful for data conditioning and decoding.
The receive synchronizer establishes frame and multiframe boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and transmission
errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero sup-
DS2180A BLOCK DIAGRAM Figure 1
TMSYNC
TFSYNC
TCLK
TLCLK
TLINK
TSER
TABCD
Transmit
Timing
F-Bit
Data
Yellow
Alarm
pression, alarm and signaling formats. User access to
the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a microprocessor/microcontroller-compatible serial port which
can be used for device configuration, control and status
monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into “hardwired” select pins. Features such as selection “clear”
DS0 channels, insertion of idle code and alteration of
sync algorithm are unavailable in the hardware mode.
TSIGSEL
TMO
TCHCLK
TSIGFR
Data
Selector
Bipolar
Coder
TPOS
TNEG
SCLK
RSER
RYEL
RABCD
RLINK
RLCLK
RSIGFR
RSIGSEL
RCHCLK
RMSYNC
RFSYNC
041995 2/36
INT
CS
SDI
SDO
SPS
Serial
Control
Interface
Yellow
Alarm
Detect
Data
Demux
Receive
Timing
Code
Gen
Information
Registers
Receive
Sync
Controller
Synchronizer
CRC
Bipolar
Coder
CRC
VDD
VSS
RST
TEST
RLOS
RBV
RCL
RPOS
RNEG
RCLK
RFER
TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY) Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TMSYNC I Transmit Multiframe Sync. May be pulsed high at multiframe boundaries
2 TFSYNC I Transmit Frame Sync. Rising edge identifies frame boundary; may be
3 TCLK I Transmit Clock. 1.544 MHz primary clock.
4 TCHCLK O Transmit Channel Clock. 192 KHz clock which identifies time slot (channel)
5 TSER I Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6 TMO O Transmit Multiframe Out. Output of internal multiframe counter indicates
7 TSIGSEL O Transmit Signaling Select. .667 KHz clock which identifies signaling frame
8 TSIGFR O Transmit Signaling Frame. High during signaling frames, low otherwise.
9 TABCD I Transmit ABCD Signaling. When enabled via TCR.4, sampled during
10 TLINK I T ransmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of
11 TLCLK O Transmit Link Clock. 4 KHz demand clock for TLINK input.
12
13
TPOS
TNEG
to reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
pulsed every frame to reinforce internal frame counter or tied low (allowing
TMSYNC to establish frame and multiframe alignment).
boundaries. Useful for parallel-to-serial conversion of channel data.
multiframe boundaries. 50% duty cycle.
A and C in 193E framing. 1.33 KHz clock in 193S.
channel LSB time in signaling frames on falling edge of TCLK.
odd frames for insertion into the outgoing data stream (193E-FDL insertion).
Sampled during the F-bit time of even frames for insertion into the outgoing
data (193S-External S-Bit insertion).
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
DS2180A
PORT PIN DESCRIPTION (40–PIN DIP ONLY) Table 2
PIN SYMBOL TYPE DESCRIPTION
14 INT
1
O Receive Alarm Interrupt. Flags host controller during alarm conditions. Ac-
tive low, open drain output.
15 SDI
16 SDO
1
1
I Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
O Serial Data Out. Control and status information from onboard registers. Up-
dated on falling edge of SCLK, tri-stated during serial port write or when CS
is high.
17 CS
18 SCLK
1
1
I Chip Select. Must be low to write or read the serial port registers.
I Serial Data Clock. Used to write or read the serial port registers.
19 SPS I Serial Port Select. T ie to VDD to select serial port. Tie to VSS to select hard-
ware mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description.”
041995 3/36
DS2180A
POWER AND TEST PIN DESCRIPTION (40–PIN DIP ONLY) Table 3
PIN SYMBOL TYPE DESCRIPTION
20 V
SS
– Signal Ground. 0.0 volts.
32 TEST I Test Mode. T ie to VSS for normal operation.
40 V
DD
– Positive Supply. 5.0 volts.
RECEIVE PIN DESCRIPTION (40–PIN DIP ONLY) Table 4
PIN SYMBOL TYPE DESCRIPTION
21 RYEL O Receive Yellow Alarm. Transitions high when yellow alarm detected, goes
22 RLINK O Receive Link Data. Updated with extracted FDL data one RCLK before start
23 RLCLK O Receive Link Clock. 4 KHz demand clock for RLINK.
24 RCLK I Receive Clock. 1.544 MHz primary clock.
25 RCHCLK O Receive Channel Clock. 192 KHz clock identifies time slot (channel) bound-
26 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges of
27 RFSYNC O Receive Frame Sync. Extracted 8 KHz clock, one RCLK wide, indicates F-
28 RMSYNC O Receive Multiframe Sync. Extracted multiframe sync; edge indicates start
29 RABCD O Receive ABCD Signaling. Extracted signaling data output, valid for each
30 RSIGFR O Receive Signaling Frame. High during signaling frames, low during resync
31 RSIGSEL O Receive Signaling Select. In 193E framing a .667 KHz clock which identi-
33 RST I Reset. A high-low transition clears all internal registers and resets receive
34
35
RPOS
RNEG
36 RCL O Receive Carrier Loss. High if 32 consecutive 0’s appear at RPOS and
37 RBV O Receive Bipolar Violation. High during accused bit time at RSER if bipolar
38 RFER O Receive Frame Error. High during F-Bit time when FT or FS errors occur
39 RLOS O Receive Loss of Sync. Indicates sync status; high when internal resync is
low when alarm clears.
of odd frames (193E) and held until next update. Updated with extracted S-bit
data one RCLK before start of even frames (193S) and held until next update.
aries.
RCLK.
Bit position in each frame.
of multiframe, 50% duty cycle.
channel time in signaling frames. In non-signaling frames, RABCD outputs
the LSB of each channel word.
and non-signaling frames.
fies signaling frames A and C. A 1.33 KHz clock in 193S.
side counters. A high-low-high transition will initiate a receive resync.
Receive Bipolar Data Inputs. Samples on falling edge of RCLK. Tie togeth-
er to receive NRZ data and disable bipolar violation monitoring circuitry.
I
RNEG; goes low after next 1.
violation detected, low otherwise.
(193S) or when FPS or CRC errors occur (193E). Low during resync.
in progress, low otherwise.
041995 4/36
REGISTER SUMMARY Table 5
REGISTER ADDRESS T/R
RSR 0000 R2Receive Status Register. Reports all receive alarm conditions.
RIMR 0001 R Receive Interrupt Mask Register. Allows masking of individual alarm-gen-
BVCR 0010 R Bipolar Violation Count Register. 8-bit presettable counter which records
ECR 0011 R Error Count Register. Two independent 4-bit counters which record OOF
3
CCR
RCR
TCR
TIR1
TIR2
TIR3
TTR1
TTR2
TTR3
RMR1
RMR2
RMR3
3
3
0100 T/R Common Control Register. Selects device operating characteristics com-
0101 R Receive Control Register. Programs device operating characteristics
0110 T Transmit Control Register. Selects additional transmit side modes.
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
DESCRIPTION/FUNCTION
erated interrupts.
individual bipolar violations.
occurrences and individual frame bit or CRC errors.
mon to receive and transmit sides.
unique to the receive side.
T
Transmit Idle Registers. Designate which outgoing channels are to be substituted with idle code.
T
T
T
Transmit Transparent Registers. Designate which outgoing channels are
to be treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
T
T
R
Receive Mark Registers. Designate which incoming channels are to be replaced with idle or digital milliwatt codes (under control of RCR).
R
R
DS2180A
NOTES:
1. Transmit or receive side register .
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility with future
transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port. Sixteen
onboard registers allow the user to update operational
characteristics and monitor device status via host controller, minimizing hardware interfaces. Port read/write
timing is unrelated to the system transmit and receive
timing, allowing asynchronous reads and/or writes by
the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status
registers requires writing one address command byte
prior to transferring register data. The first bit written
(LSB) of the address/command word specifies register
read or write. The following 4-bit nibble identifies regis-
ter address. The next two bits are reserved and must be
set to 0 for proper operation. The last bit of the address/
command word enables burst mode when set; the burst
mode causes all registers to be consecutively written or
read.
Data is written to and read from the transceiver
LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input
low. Input data is latched on the rising edge of SCLK and
must be valid during the previous low period of SCLK to
prevent momentary corruption of register data during
Data is output on the falling edge of SCLK and
writes.
held on the next falling edge. All data transfers are terminated if the CS input transitions high. Port control logic is
disabled and SDO is tri-stated when CS is high.
041995 5/36
DS2180A
DATA I/O
Following the eight SCLK cycles that input an address/
command byte to write, a data byte is strobed into the
addressed register on the rising edges of the next eight
SCLK cycles. Following an address/command word to
read, contents of the selected register are output on the
falling edges of the next eight SCLK cycles. The SDO
pin is tri-stated during device write and may be tied to
BURST MODE
The burst mode allows all onboard registers to be consecutively read and written by the host processor. A
burst read is used to poll all registers; RSR contents will
be unaffected. This feature minimizes device initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address nibble is 0000.
Burst is terminated by a low-high transition on CS
SDI in applications where the host processor has a bidirectional I/O pin.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
BM
SYMBOL POSITION NAME AND DESCRIPTION
BM ACB.7 Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or write is en-
– ACB.6 Reserved, must be 0 for proper operation.
– ACB.5 Reserved, must be 0 for proper operation.
ADD3 ACB.4 MSB of register address.
ADD0 ACB.1 LSB of register address.
R/W
– – ADD3 ADD2 ADD1 ADD0 R/W
abled.
ACB.0 Read/Write Select.
0 = write addressed register.
1 = read addressed register.
.
SERIAL PORT READ/WRITE Figure 3
CS
SCLK
SDI
R/W ADD0 ADD1 ADD2 0 0 BM D0 D2 D3D1 D4 D5 D6 D7
1
2
,SDO
ADDRESS/COMMAND DATA INPUT/OUTPUT
ADD3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
041995 6/36
COMMON CONTROL REGISTER Figure 4
(MSB) (LSB)
– FRSR2 EYELMD FM SYELMD B8ZS B7 LPBK
SYMBOL POSITION NAME AND DESCRIPTION
– CCR.7 Reserved, must be 0 for proper operation.
FRSR2 CCR.6 Function of REC Status Register 2.
0 = Detected B8ZS code words reported at RSR.2.
1 = COFA (Change-of-Frame Alignment) reported at RSR.2 when last resync resulted in change of frame or multiframe alignment.
EYELMD CCR.5 193E Yellow Mode Select.
0 = Y ellow alarm is a repeating pattern set of 00 hex and FF hex.
1 = Y ellow alarm is a 0 in the bit 2 position of all channels.
FM CCR.4 Frame Mode Select.
0 = D4 (193S, 12 frames/superframe).
1 = Extended (193E, 24 frames/superframe).
SYELMD CCR.3 193S Yellow Mode Select. Determines yellow alarm type to be transmitted
and detected while in 193S framing. If set, yellow alarms are a 1 in the S-bit
position of frame 12; if cleared, yellow alarm is a 0 in bit 2 of all channels.
Does not affect 193E yellow alarm operation.
B8ZS CCR.2 Bipolar eight zero substitution.
0 = No B8ZS.
1 = B8ZS enabled.
(Note: This bit must be set to 0 when CCR.1=1)
B7 CCR.1 Bit seven zero suppression. If CCR.1=1, channels with an all zero con-
tent will be transmitted with bit 7 forced to 1. If CCR.1=0, no bit 7 stuffing
occurs.
(Note: This bit must be set to 0 when CCR.2=1)
LPBK CCR.0 Loopback. When set, the device internally loops output transmit data into
the incoming receive data buffers and TCLK is internally substituted for
RCLK.
DS2180A
LOOPBACK (Refer to Figure 4)
Enabling loopback will typically induce an out-of-frame
(OOF) condition. If appropriate bits are set in the receive
control register, the receiver will resync to the looped
transmit frame alignment. During the looped condition,
the transmit outputs (TPOS, TNEG) will transmit unframed all 1’s. All operating modes (B8ZS, alarm,
signaling, etc.) except for blue alarm transmission are
available in loopback.
BIT SEVEN STUFFING
Existing systems meet 1’s density requirements by forcing bit 7 of all zero channels to 1. Bit 7 stuffing is globally
enabled by asserting bit CCR.1 and may be disabled on
an individual channel basis by setting appropriate bits in
TTR1–TTR3. Bit 7 stuffing and B8ZS modes should not
be enabled simultaneously. Enabling both results in
LOS.
041995 7/36
DS2180A
B8ZS
The DS2180A supports existing and emerging zero
suppression formats. Selection of B8ZS coding maintains system 1’s density requirements without disturbing data integrity as required in emerging clear channel
applications. B8ZS coding replaces eight consecutive
outgoing 0’s with a B8ZS code word. Any received
B8ZS code word is replaced with all 0’s. B8ZS and bit 7
stuffing modes should not be enabled simultaneously.
Enabling both results in LOS.
TCR: TRANSMIT CONTROL REGISTER Figure 5
(MSB) (LSB)
ODF TFPT TCP RBSE TIS 193SI TBL TYEL
SYMBOL POSITION NAME AND DESCRIPTION
ODF TCR.7 Output Data Format.
TFPT TCR.6 Transmit Framing Pass-through.
TCP TCR.5 Transmit CRC Pass-through.
RBSE TCR.4 Robbed Bit Signaling Enable.
TIS TCR.3 Transmit Idle Code Select. Determines idle code format to be inserted
193SI TCR.2 193S S-bit Insertion. Determines source of transmitted S-bit.
TBL TCR.1 Transmit Blue Alarm.
TYEL TCR.0 Transmit Yellow Alarm.
0 = Bipolar data at TPOS and TNEG.
1 = NRZ data at TPOS; TNEG=0.
0 = FT/FPS sourced internally.
1 = FT/FPS sampled at TSER during F-bit time.
0 = Transmit CRC code internally generated.
1 = TSER sampled at CRC F-bit time for external CRC insertion.
1 = Signaling inserted in all channels during signaling frames.
0 = No signaling inserted. (The TTR registers allow the user to disable
signaling insertion on selected DS0 channels.)
into channels marked by the TIR registers.
0 = Insert 7F (Hex) into marked channels.
1 = Insert FF (Hex) into marked channels.
0 = Internal S-bit generator.
1 = External (sampled at TLINK input).
0 = Disabled.
1 = Enabled.
0 = Disabled.
1 = Enabled.
TRANSMIT BLUE ALARM
The blue alarm (also known as the AIS, Alarm Indication
Signal) is an unframed, all 1’s sequence enabled by asserting TCR.1. Blue alarm overrides all other transmit
data patterns and is disabled by clearing TCR.1. Use of
the TIR registers allows a framed, all 1’s alarm transmission if required by the network.
041995 8/36
TRANSMIT YELLOW ALARM
In 193E framing, a yellow alarm is a repeating pattern
set of FF(Hex) and 00 (Hex) on the 4 KHz facility data
link (FDL). In 193S framing the yellow alarm format is
dependent on the state of bit CCR.3. In all modes, yellow alarm is enabled by asserting TCR.0 and disabled
by clearing TCR.0.
DS2180A
TRANSMIT SIGNALING
When enabled (via TCR.4) channel signaling is inserted
in frames 6 and 12 (193S) or in frames 6, 12, 18 and 24
(193E) in the 8th bit position of every channel word.
Signaling data is sampled at T ABCD on the falling edge
of TCLK during bit 8 of each input word during signaling
frames. Logical combination of clocks TMO, TSIGFR
and TSIGSEL allows external multiplexing of separate
serial links for A, B or A, B, C, D signaling sources.
TTR1–TTR3: TRANSMIT TRANSPARENCY REGISTERS Figure 6
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TTR1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TTR2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TTR3
SYMBOL POSITION NAME AND DESCRIPTION
CH24 TTR3.7 T ransmit Transparent Registers. Each of these bit positions represents a
CH1 TTR1.0 DS0 channel in the outgoing frame. When set, the corresponding channel
is transparent.
TIR1–TIR3: TRANSMIT IDLE REGISTERS Figure 7
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3
SYMBOL POSITION NAME AND DESCRIPTION
CH24 TIR3.7 Transmit Idle Registers. Each of these bit positions represents a DS0
CH1 TIR1.0 channel in the outgoing frame. When set, the corresponding channel will
TRANSMIT CHANNEL TRANSPARENCY
Individual DS0 channels in the T1 frame may be programmed clear (no inserted robbed bit signaling and no
bit 7 zero suppression) by setting the appropriate bits in
the transmit transparency registers. Channel transparency is required in mixed voice/data or data-only environments such as ISDN, where data integrity must be
maintained.
output an idle code format determined by TCR.2.
TRANSMIT IDLE CODE INSERTION
Individual outgoing channels in the frame can be programmed with idle code by asserting the appropriate
bits in the transmit idle registers. One of two idle code
formats, 7F (Hex) and FF (Hex) may be selected by the
user via TCR.3. If enabled, robbed bit signaling data is
inserted into the idle channel, unless the appropriate
TTR bit is set for that channel. This feature eliminates
external hardware currently required to intercept and
stuff unoccupied channels in the DS1 bit stream.
041995 9/36
DS2180A
TRANSMIT INSERTION HIERARCHY Figure 8
TSER TLINK TABCD
F-BIT
TSER
TSER
TSER + ABCD
+ B7
Y
Y
TSER + ABCD
B7 STUFF
TSER + ABCD TSER + B7
193S YELLOW ALARM – B2 STUFF
YY
IDLE
N
TSER
CLEAR
N
TSER
SIG
N
TSER
B7 STUFF
NN
TSER
Y
IDLE
CLEAR
N
IDLE
SIG
N
IDLE IDLE + ABCD
Y
IDLE
Y
041995 10/36
B8ZS
BLUE or LPBK
TPOS, TNEG
193S TRANSMIT MULTIFRAME TIMING Figure 9
DS2180A
FRAME #
TFSYNC
TMSYNC
1
TMO
TSIGSEL
TSIGFR
TLCLK
TABCD
3
TLINK
1
2
123 4567 891011121 23 45612
BABA
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish multiframe
boundaries, allowing internal counters to determine frame timing.
b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe bound-
aries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and superframe tim-
ing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establish an arbi-
trary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in frames indi-
cated.
3. When external S-bit insertion is enabled, TLINK will be sampled during the F-bit time of even frames and in-
serted into the outgoing data stream.
041995 11/36
Loading...