Rainbow Electronics DS2172 User Manual

DS2172

Bit Error Rate Tester (BERT)

FEATURES

• Generates/Detects digital bit patterns for analyzing,

evaluating and troubleshooting digital communications systems

• Operates at speeds from DC to 52 MHz

• Programmable polynomial length and feedback taps

for generation of any other pseudorandom pattern up to 32 bits in length including: 26–1, 29–1, 211–1,

–1, 220–1, 223–1, and 232–1

• Programmable user–defined pattern and length for

generation of any repetitive pattern up to 32 bits in length

• Large 32–bit error count and bit count registers

• Software programmable bit error insertion

• Fully independent transmit and receive sections

• 8–bit parallel control port

• Detects test patterns with bit error rates up to 10

DESCRIPTION

The DS2172 Bit Error Rate T ester (BERT) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudorandom and Repetitive) conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, Routers, Bridges, CSUs, DSUs, and CPE equipment.

The DS2172 user programmable pattern registers provide the unique ability to generate loopback patterns required for T1, Fractional–T1, Smart Jack, and other

–2

PIN ASSIGNMENT

TDATA

TDIS

TCLK

VSS

VDD

RCLK

RDIS

RDATA

32 31 30 29 28 27 26 25

TL AD0 AD1

TEST

VSS AD2 AD3 AD4

1 2 3 4

DS2172

32–PIN TQFP

5 6 7 8

9 101112131415 16

AD5

AD6

AD7

BTS

VSS

VDD

RD (DS)

test procedures. Hence the DS2172 can initiate the loopback, run the test, check for errors, and finally deactivate the loopback.

The DS2172 consists of four functional blocks: the pattern generator, pattern detector , error counter , and control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up to 2 bits (See T able 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional–T1, Switched–56, DDS, normal framing requirements, and per–channel test procedures. In addition, the DS2172 can insert single or 10

–1

to 10–7 bit errors to verify equipment

operation and connectivity .

24 23

RLOS LC

22 21

VSS

VDD

INT WR (R/W)

18 17

ALE (AS)

32–1

Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

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DS2172

1.0 GENERAL OPERATION

1.1 Pattern Generation

The DS2172 is programmed to generate a particular test pattern by programming the following registers:

– Pattern Set Registers (PSR) – Pattern Length Register (PLR) – Polynomial Tap Register (PTR) – Pattern Control Register (PCR) – Error Insertion Register (EIR)

Please see Tables 4 and 5 for examples of how to program these registers in order to generate some standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin appearing at the TDATA pin.

1.2 Pattern Synchronization

The DS2172 expects to receive the same pattern that it transmitted. The synchronizer examines the data at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.

In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all zeros pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by using the RA1 and RA0 indicators in the Status Register. Once in

synchronization (SR0. = 1) any deviation from this pattern will be counted by the Bit Error Count Register.

In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test. Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in the Status Register and examining the Pattern Receive Register (PRR0––3). See section 10 for an explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this pattern will be counted by the Bit Error Count Register.

1.3 BER Calculation

Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration period.

1.4 Generating Errors

Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the transmitted data stream. Injecting errors allows users to stress communication links and to check the functionality of error monitoring equipment along the path.

1.5 Power–Up Sequence

On power–up, the registers in the DS2172 will be in a random state. The user must program all the internal registers to a known state before proper operation can be insured.

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DS2172 FUNCTIONAL BLOCK DIAGRAM Figure 1

DS2172

RDIS

RCLK

RDATA

TDIS

TCLK

TDATA

RECEIVE

RATE

CONTROL

TRANSMIT

RATE

CONTROL

DETECTOR

LOOPBACK MUX

RECEIVE PATTERN

REGISTERS

ERROR

INSERTION

PARALLEL CONTROL PORT

BTS RD WR TEST ALE CS INT AD0–AD7

DS2172 PATTERN GENERATION BLOCK DIAGRAM Figure 2

TAP A FEEDBACK

BIT ERROR COUNTER

BIT COUNTER

PATTERN

GENERATOR

SYNC

EIR.5

XOR

XOR DFF DFF DFF DFF

0 1 N–2 N–1

TAP B FEEDBACK

PCR.5

NOTES:

1. Tap A always equals length (N–1) of pseudorandom or repetitive pattern.

2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.

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DS2172

DETAILED PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1 TL I Transmit Load. A positive–going edge loads the pattern generator with the

2 AD0 I/O Data Bus. A 8–bit multiplexed address/data bus. 3 AD1 I/O Data Bus. A 8–bit multiplexed address/data bus. 4 TEST I Test. Set high to 3–state all output pins (INT, ADx, TDATA, RLOS). Should

5 V

6 AD2 I/O Data Bus. A 8–bit multiplexed address/data bus. 7 AD3 I/O Data Bus. A 8–bit multiplexed address/data bus. 8 AD4 I/O Data Bus. A 8–bit multiplexed address/data bus.

9 AD5 I/O Data Bus. A 8–bit multiplexed address/data bus. 10 AD6 I/O Data Bus. A 8–bit multiplexed address/data bus. 11 AD7 I/O Data Bus. A 8–bit multiplexed address/data bus. 12 V 13 V

SS DD

14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to select

15 RD (DS) I Read Input (Data Strobe). 16 CS I Chip Select. Must be low to read or write the port. 17 ALE (AS) I Address Latch Enable (Address Strobe). A positive going edge serves to

18 WR (R/W) I Write Input (Read/Write). 19 INT O Alarm Interrupt. Flags host controller during conditions defined in Status

20 V 21 V

DD SS

22 LC I Load Count. A positive–going edge latches the current bit and bit error count

23 RLOS O Receive Loss Of Sync. Indicates the real time status of the receive synchro-

contents of the Pattern Set Registers. The MSB of the repetitive or pseudorandom pattern appears at TDATA after the third positive edge of TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should be tied to V not used. See Figure 8 for timing information.

be tied to V

to enable all outputs.

– Signal Ground. 0.0 volts. Should be tied to local ground plane.

– Signal Ground. 0.0 volts. Should be tied to local ground plane. – Positive Supply. 5.0 volts.

Intel bus timing. This pin controls the function of the RD

(R/W) pins. If BTS = 1, then these pins assume the function listed in

(DS), ALE(AS), and

parenthesis ().

demultiplex the bus.

Register. Active low, open drain output. – Positive Supply. 5.0 volts. – Signal Ground. 0.0 volts. Should be tied to local ground plane.

into the user accessible BCR and BECR registers and clears the internal

count registers. LC is logically OR’ed with control bit PCR.4. Should be tied

if not used.

to V

nizer. Active high output; transitions low after receiving 32 matching bits.

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PIN DESCRIPTIONTYPESYMBOL

24 RL I Receive Load. A positive–going edge loads the previous 32 bits of data

received at RDATA into the Pattern Receive Registers. RL is logically OR’ed with control bit PCR.3. Should be tied to V

if not used.

25 RDATA I Receive Data. Received NRZ serial data, sampled on the rising edge of

RCLK.

26 RDIS I Receive Disable. Set high to prevent the data at RDATA from being

sampled. Set low to allow bits at RDATA to be sampled. Should be tied to V if not used. See Figure 6 for timing information. All receive side operations are disabled when RDIS is high.

27 RCLK I Receive Clock. Input clock from transmission link. 0 to 52 MHz. Can be a

gapped clock. Fully independent from TCLK. 28 V 29 V

DD SS

– Positive Supply. 5.0 volts. – Signal Ground. 0.0 volts. Should be tied to local ground plane.

30 TCLK I Transmit Clock. Transmit demand clock. 0 to 52 MHz. Can be a gapped

clock. Fully independent of RCLK. 31 TDIS I Transmit Disable. Set high to hold the current bit being transmitted at

TDATA. Set low to allow the next bit to appear at TDATA. Should be tied to

if not used. See Figure 7 for timing information. All transmit side opera-

tions are disabled when TDIS is high. 32 TDATA O Transmit Data. Transmit NRZ serial data, updated on the rising edge of

TCLK.

DS2172

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DS2172

DS2172 REGISTER MAP Table 2

ADDRESS R/W REGISTER NAME

00 R/W Pattern Set Register 3. 01 R/W Pattern Set Register 2. 02 R/W Pattern Set Register 1. 03 R/W Pattern Set Register 0. 04 R/W Pattern Length Register. 05 R/W Polynomial Tap Register. 06 R/W Pattern Control Register. 07 R/W Error Insert Register. 08 R Bit Counter Register 3.

09 R Bit Counter Register 2. 0A R Bit Counter Register 1. 0B R Bit Counter Register 0. 0C R Bit Error Counter Register 3. 0D R Bit Error Counter Register 2. 0E R Bit Error Counter Register 1. 0F R Bit Error Counter Register 0. 10 R Pattern Receive Register 3.

11 R Pattern Receive Register 2. 12 R Pattern Receive Register 1. 13 R Pattern Receive Register 0. 14 R Status Register. 15 R/W Interrupt Mask Register. 1C R/W Test Register (see note 1)

NOTE:

1. The Test Register must be set to 00 hex to insure proper operation of the DS2172.

2.0 PARALLEL CONTROL INTERFACE

The DS2172 is controlled via a multiplexed bi–directional address/data bus by an external microcontroller or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or WR DS2172 outputs a byte of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can also be easily connected to non–multiplexed buses. RCLK and TCLK are used to update counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these port operations.

pulses. In a read cycle, the

3.0 PATTERN SET REGISTERS

The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is to be repeated. Please see Tables 4 and 5 for some programming examples.

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