Rainbow Electronics DS2165Q User Manual

DS2165/DS2165Q

16/24/32Kbps ADPCM Processor

FEATURES

• Compresses/expands 64Kbps PCM voice to/from

either 32Kbps, 24Kbps, or 16Kbps

• Dual, fully independent channel architecture; device

can be programmed to perform either:

– two expansions – two compressions – one expansion and one compression

• Interconnects directly to combo-codec devices

• Input to output delay is less than 375 µs

• Simple serial port used to configure the device

• Onboard Time Slot Assigner Circuit (TSAC) function

allows data to be input/output at various time slots

• Supports Channel Associated Signaling

• Each channel can be independently idled or placed

into bypass

• Available hardware mode requires no host processor;

ideal for voice storage applications

• Backward-compatible with the DS2167 ADPCM

Processor Chip

• Single +5V supply; low-power CMOS technology

• Available in 24-pin DIP and 28-pin PLCC

PIN ASSIGNMENT

RST TM0

TM1

A0 A1 A2 A3 A4 A5

SPS

MCLK

VSS

24-Pin DIP (600 MIL)

432

5 6

A3 A4

12 1314 15 16 1718

A 3–volt Operation Version

is Available (DS2165QL)

1 2 3 4

5 6 7 8

9 10 11 12

TM1

RSTNCVDD

TM0

SPS

VSS

MCLK

28-Pin PLCC

272826

XIN

24 23 22 21

20 19 18 17

16 15 14

YINCLKX

VDD YIN CLKY FSY YOUT CS SDI SCLK

XOUT FSX CLKX XIN

CLKY

25 24 23 22

21 20 19

FSX

FSY YOUT

CS SDI SCLK XOUT

DESCRIPTION

The DS2165 ADPCM Processor Chip is a dedicated Digital Signal Processing (DSP) chip that has been optimized to perform Adaptive Differential Pulse Code Modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64Kbps voice data down to (up from) either 32Kbps, 24Kbps, or 16Kbps. The compression to 32Kbps follows the algorithm specified by CCITT Recommendation G.721 (July 1986) and ANSI document

Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

T1.301 (April 1987). The compression to 24Kbps follows ANSI document T1.303. The compression to 16Kbps follows a proprietary algorithm developed by Dallas Semiconductor. The DS2165 can switch compression algorithms on-the-fly. This allows the user to make maximum use of the available bandwidth on a dynamic basis.

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DS2165/DS2165Q

OVERVIEW

The DS2165 contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A 10 MHz master clock is required by the DSP engine. The DS2165 can be configured to perform either two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256 KHz to 4.096 MHz. Typically, the PCM data rates will be 1.544 MHz for µ-law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result during a user-programmed output time slot.

Each PCM interface has a control register which specifies functional characteristics (compress, expand, bypass, and idle), data format (µ-law or A-law), and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level interconnect.

With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to time slot 0.

except the IPD bits; the IPD bits for both channels are set to 1.

SOFTWARE MODE

Tying SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2165 via the serial port through inputs SCLK, SDI, and CS DS2165 is either a 2-byte write or a 4-byte write. A 2byte write consists of the Address/Command Byte (ACB), followed by a byte to configure the Control Register (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then one byte to set the input time slot and another byte to set the output time slot.

. (See Figure 2.) Each write to the

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next three bytes written are accepted as control, input and output time slot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tristated during register updates.

CONTROL REGISTER

The control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected channel.

HARDWARE RESET

RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that the device has initialized properly. RST when changing to or from the hardware mode. RST clears all bits of the Control Register for both channels

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should also be asserted

The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not be operated faster than 39 KHz.

ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete.

DS2165/DS2165Q

PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1 RST I Reset. A high-low-high transition resets the algorithm. The device should

2 3

4 5 6 7 8 9

TM0 TM1

A0 A1 A2 A3 A4 A5

10 SPS I Serial Port Select. Tie to VDD to select the serial port; tie to VSS to select

11 MCLK I Master Clock. 10 MHz clock for the ADPCM processing engine; may be

12 V

13 XIN I X Data In. Sampled on falling edge of CLKX during selected time slots. 14 CLKX I X Data Clock. Data clock for the X side PCM interface; must be synchro-

15 FSX I X Frame Sync. 8 KHz frame sync for the X side PCM interface. 16 XOUT O X Data Output. Updated on rising edge of CLKX during selected time slots. 17 SCLK I Serial Data Clock. Used to write to the serial port registers. 18 SDI I Serial Data In. Data for onboard control registers; sampled on the rising

19 CS I Chip Select. Must be low to write to the serial port. 20 YOUT O Y Data Output. Updated on rising edge of CLKY during selected time slots. 21 FSY I Y Frame Sync. 8 KHz frame sync for the Y side PCM interface. 22 CLKY I Y Data Clock. Data clock for the Y side PCM interface; must be synchro-

23 YIN I Y Data In. Sampled on falling edge of CLKY during selected time slots. 24 V

be reset on power up and when changing to or from the hardware mode.

I Test Modes 0 and 1. Tie to VSS for normal operation.

I Address Select. A0 = LSB; A5 = MSB Must match address/command

word to enable the serial port.

the hardware mode.

asynchronous to SCLK, CLKX, and CLKY.

– SIgnal Ground. 0.0 volts.

nous with FSX.

edge of SCLK. LSB sent first.

nous with FSY.

– Positive Supply. 5.0 volts (or 3.0 volts for DS2165QL).

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DS2165/DS2165Q

ÉÉ

DS2165 BLOCK DIAGRAM Figure 1

FSX

CLKX

XIN

XOUT

SCLK

SPS

SDI

A0 - A5

FSY

CLKY

YIN

YOUT

RST TM0 TM1

X SIDE PCM/ADPCM

DATA INTERFACE

SERIAL PORT CONTROL/

HARDWARE MODE LOGIC

Y SIDE PCM/ADPCM

DATA INTERFACE

RESET AND TEST LOGIC

SERIAL PORT WRITE Figure 2

ADPCM

PROCESSING

ENGINE

MCLK

A0 A1 A2 A3 A4 A5 X/Y 0 CR0

ADDRESS/COMMAND CONTROL

NOTE:

1. A 2-byte write is shown.

The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or compression occurs. Bypass operates on bytewide (8 bits) slots when CP/EX when CP/EX is cleared.

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is set and on nibble-wide (4 bits) slots

CR2 CR3 CR4 CR5 CR6 CR7

CR1

A-law (U/A

= 0) and µ-law (U/A = 1) PCM coding is independently selected for the X and Y channels via CR.2. If BYP and IPD are cleared, then CP/EX

determines if the

input data is to be compressed or expanded.

DS2165/DS2165Q

ADDRESS/COMMAND BYTE Figure 3

(MSB) (LSB)

– X/Y A5 A4 A3 A2 A1 A0

SYMBOL POSITION NAME AND DESCRIPTION

– ACB.7 Reserved; must be 0 for proper operation X/Y ACB.6 X/Y Channel Select

0 = update channel Y characteristics

1 = update channel X characteristics A5 ACB.5 MSB of Device Address A4 ACB.4 A3 ACB.3 A2 ACB.2 A1 ACB.1 A0 ACB.0 LSB of Device Address

CONTROL REGISTER Figure 4

(MSB) (LSB)

AS0 AS1 IPD ALRST BYP U/A AS2 CP/EX

SYMBOL POSITION NAME AND DESCRIPTION

AS0 CR.7 Algorithm Select 0. See Table 2. AS1 CR.6 Algorithm Select 1. See Table 2. IPD CR.5 Idle and Power Down.

0 = channel enabled

1 = channel disabled (output 3-stated) ALRST CR.4 Algorithm Reset.

0 = normal operation

1 = reset algorithm for selected channel BYP CR.3 Bypass.

0 = normal operation

1 = bypass selected channel U/A

AS2 CR.1 Algorithm Select 2. See Table 2. CP/EX

CR.2 Data Format.

0 = A-law

1 = µ-law

CR.0 Channel Coding.

0 = expand (decode) selected channel

1 = compress (encode) selected channel

ALGORITHM SELECT BITS Table 2

ALGORITHM SELECTED AS2 AS1 AS0

64Kbps to/from 32Kbps 0 0 0 64Kbps to/from 24Kbps 1 1 1 64Kbps to/from 16Kbps 1 0 1

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DS2165/DS2165Q

INPUT TIME SLOT REGISTER Figure 5

(MSB) (LSB)

– – D5 D4 D3 D2 D1 D0

SYMBOL POSITION NAME AND DESCRIPTION

- ITR.7 Reserved; must be 0 for proper operation.

- ITR.6 Reserved; must be 0 for proper operation. D5 ITR.5 MSB of input time slot register. D4 ITR.4 D3 ITR.3 D2 ITR.2 D1 ITR.1 D0 ITR.0 LSB of input time slot register.

OUTPUT TIME SLOT REGISTER Figure 6

(MSB) (LSB)

–

SYMBOL POSITION NAME AND DESCRIPTION

- OTR.7 Reserved; must be 0 for proper operation.

- OTR.6 Reserved; must be 0 for proper operation. D5 OTR.5 MSB of output time slot register. D4 OTR.4 D3 OTR.3 D2 OTR.2 D1 OTR.1 D0 OTR.0 LSB of output time slot register.

– D5 D4 D3 D2 D1 D0

TIME SLOT ASSIGNMENT/ORGANIZATION

Onboard counters establish when PCM and ADPCM I/O occurs. The counters are programmed via the time slot registers. Time slot size (number of bits wide) is determined by the state of CP/EX slots available is determined by both the state of CP/EX and U/A. (See Figures 7 through 10.) For example, if the X channel is set to compress (CP/EX

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. The number of time

= 1) and it is set to

expect µ-law data (U/A

= 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected. NOTE: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync.

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