Rainbow Electronics DS2153Q User Manual

DS2153Q

E1 Single–Chip Transceiver

FEATURES

• Complete E1(CEPT) PCM–30/ISDN–PRI transceiver

functionality

• Onboard line interface for clock/data recovery and

waveshaping

• 32–bit or 128–bit jitter attenuator

• Generates line build–outs for both 120 ohm and 75

ohm lines

• Frames to FAS, CAS, and CRC4 formats

• Dual onboard two–frame elastic store slip buffers that

can connect to backplanes up to 8.192 MHz

• 8–bit parallel control port that can be used on either

multiplexed or non–multiplexed buses

• Extracts and inserts CAS signaling

• Detects and generates Remote and AIS alarms

• Programmable output clocks for Fractional E1, H0,

and H12 applications

• Fully independent transmit and receive functionality

• Full access to both Si and Sa bits

• Three separate loopbacks for testing

• Large counters for bipolar and code violations, CRC4

code word errors, FAS errors, and E bits

• Pin compatible with DS2151Q T1 Single–Chip Trans-

ceiver

• 5V supply; low power CMOS

• Industrial grade version (–40°C to +85°C) available

(DS2153QN)

DESCRIPTION

The DS2153Q T1 Single–Chip Transceiver (SCT) contains all of the necessary functions for connection to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream.

PIN ASSIGNMENT

FUNCTIONAL BLOCKS

FRAMER

ELASTIC STORES

LINE INTERFACE

LONG & SHORT HAUL

PARALLEL CONTROL

PORT

DALLAS

DS2153Q

E1 SCT

ALE

RLINK

RLCLK

DVSS RCLK

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

The DS2153 automatically adjusts to E1 22 AWG (0.6 mm) twisted–pair cables from 0 to 1.5 KM. The device can generate the necessary G.703 waveshapes for both 75 ohm and 120 ohm cables. The onboard jitter

ACTUAL SIZE OF

44–PIN PLCC

CSRDAD7

AD6

AD5

AD4

AD3

AD2

65432

7 8 9 10 11 12 13 14 15 16 17

1819202122232425262728

ACLKI

RCHBLK

BTS

RTIP

RVDD

RRING

4443424140

RVSS

XTAL1

AD1

XTAL2

AD0

39 38 37 36 35 34 33 32 31 30 29

INT1

TCHCLK

TSER TCLK DVDD TSYNC TLINK TLCLK TCHBLK TRING TVDD TVSS TTIP

INT2

Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

022697 1/48

DS2153Q

attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa–bit information. The device contains a set of 71 8–bit internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011 and 300 233.

TABLE OF CONTENTS

1. Introduction

2. Parallel Control Port

3. Control and Test Registers

4. Status and Information Registers

5. Error Count Registers

6. Sa Data Link Control and Operation

7. Signaling Operation

8. Transmit Idle Registers

9. Clock Blocking Registers

10. Elastic Store Operation

11. Additional (Sa) and International (Si) Bit Operation

12. Line Interface Control Function

13. Timing Diagrams, Synchronization Flowchart, and Transmit flow Diagram

14. DC and AC Characteristics

1.0 INTRODUCTION

The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing pattern. If

needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input.

The transmit side of the DS2153Q is totally independent from the receive side in both the clock requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP and TRING pins via a coupling transformer.

Reader’s Note

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8–bit timeslots in E1 systems which are numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:

FAS Frame Alignment Signal CAS Channel Associated Signaling MF Multiframe Si International Bits CRC4 Cyclical Redundancy Check CCS Common Channel Signaling Sa Additional bits E–bit CRC4 Error bits

022697 2/48

DS2153Q BLOCK DIAGRAM Figure 1–1

RCLK

RLINK

RLCLK

RCHBLK

Sa Bit

RCHCLK

Extraction

Framer

Receive Side

RSER

Timing

Control

Signaling Extraction

FAS Error Count

E Bit Count

CRC4 Error Count

Alarm Detection

Synchronizer BPV Counter

HDB3 Decoder

SYSCLK

RSYNC

Store

Elastic

TCLK

Loss of

TCLK Detect

mux

FAS Word Insertion

Si Bit Insertion

E Bit Insertion

Sa Bit Insertion Signaling Insertion Idle Code Insertion

CRC4 Generation

Transmit Side Formatter

AIS Generation

TSER

Store

Elastic

clock

data

sync

HDB3 Encode

TSYNC

TCHCLK

Timing

Control

TCHBLK

TLINK

Insert

DS2153Q

TLCLK

Logic

ACLKI XTAL1 XTAL2 RLOS

XTAL/VCO/PLL

32.768 MHz

Framer Loopback

Remote Loopback

Data

Clock/

Peak

Filter

RRING

Recovery

Detect

RTIP

Jitter Attenuation Mux

Local Loopback

Wave

Line

TRING

Shaping

Drivers

TTIP

(can be placed in either the transmit or receive paths)

(routed to all blocks)

Parallel Control Port

CS WR(R/W) RD(DS) ALE(AS) AD0 – AD7 INT1/INT2

BTS

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DS2153Q

PIN DESCRIPTION Table 1–1

PIN SYMBOL TYPE DESCRIPTION

1 2 3 4

5 RD(DS) I Read Input (Data Strobe). 6 CS I Chip Select. Must be low to read or write the port. 7 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to

8 WR(R/W) I Write Input (Read/Write). 9 RLINK O Receive Link Data. Outputs the full receive data stream including the Sa

10 RLCLK O Receive Link Clock. 4 KHz to 20 KHz demand clock for the RLINK output;

11 DVSS – Digital Signal Ground. 0.0 volts. Should be tied to local ground plane. 12 RCLK O Receive Clock. Recovered 2.048 MHz clock. 13 RCHCLK O Receive Channel Clock. 256 KHz clock which pulses high during the LSB

14 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges

15 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which

16 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.

17 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic

18 RCHBLK O Receive Channel Block. A user programmable output that can be forced

19 ACLKI I Alternate Clock Input. Upon a receive carrier loss, the clock applied at this

AD4 AD5 AD6 AD7

I/O Address/Data Bus. A 8–bit multiplexed address/data bus.

demultiplex the bus.

bits. See Section 13 for timing details.

controlled by RCR2. See Section 13 for timing details.

of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details.

of RCLK or SYSCLK.

identifies either frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If the elastic store is enabled via the RCR2.1, then this pin can be enabled to be an input via RCR1.5 at which a frame boundary pulse is applied. See Section 13 for timing details.

If TCR2.0=0, will toggle high when the synchronizer is searching for the E1 frame and multiframe; if TCR2.0=1, will toggle high if the TCLK pin has not toggled for 5 µs.

store functions are enabled via RCR2.1. Should be tied low in applications that do not use the elastic store. If tied high for at least 100 µs, will force all output pins (including the parallel port) to 3–state.

high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384K bps service (H0), 1920K bps (H12), or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications. See Section 13 for timing details.

pin (normally 2.048 MHz) will be routed to the RCLK pin. If no clock is routed to this pin, then it should be tied to DVSS.

022697 4/48

DS2153Q

PIN DESCRIPTIONTYPESYMBOL

20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD ALE(AS), and WR

(R/W) pins. If BTS=1, then these pins assume the function

(DS),

listed in parenthesis ().

21 22

RTIP

RRING

– Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects

to a 1:1 transformer (see Section 12 for details).

23 RVDD – Receive Analog Positive Supply. 5.0 volts. Should be tied to DVDD and

TVDD pins. 24 RVSS – Receive Signal Ground. 0.0 volts. Should be tied to local ground plane. 25

XTAL1 XTAL2

– Crystal Connections. A pullable 8.192 MHz crystal must be applied to

these pins. See Section 12 for crystal specifications. 27 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions

defined in Status Register 1. Active low, open drain output. 28 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined

in Status Register 2. Active low, open drain output. 29 TTIP – Transmit Tip. Analog line driver output; connects to a step–up transformer

(see Section 12 for details). 30 TVSS – Transmit Signal Ground. 0.0 volts. Should be tied to local ground plane. 31 TVDD – Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD and

RVDD pins. 32 TRING – Transmit Ring. Analog line driver outputs; connects to a step–up trans-

former (see Section 12 for details). 33 TCHBLK O Transmit Channel Block. A user programmable output that can be forced

high or low during any of the 32 E1 channels. Useful for blocking clocks to

a serial UART or LAPD controller in applications where not all E1 channels

are used such as Fractional E1, 384K bps service (H0), 1920K bps (H12),

or ISDN–PRI. Also useful for locating individual channels in drop–and–insert

applications. See Section 13 for timing details. 34 TLCLK O Transmit Link Clock. 4 KHz to 20 KHz demand clock for the TLINK input;

controlled by TCR2. See Section 13 for timing details. 35 TLINK I Transmit Link Data. If enabled, this pin will be sampled on the falling edge

of TCLK to insert the Sa bits See Section 13 for timing details. 36 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe

boundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be pro-

grammed to output either a frame or multiframe pulse at this pin. See Section

13 for timing details. 37 DVDD – Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD pins. 38 TCLK I Transmit Clock. 2.048 MHz primary clock. Needed for proper operation of

the parallel control port. 39 TSER I Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge

of TCLK.

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DS2153Q

PIN DESCRIPTIONTYPESYMBOL

40 TCHCLK O Transmit Channel Clock. 256 KHz clock which pulses high during the LSB

of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details.

41 42 43 44

AD0 AD1 AD2 AD3

I/O Address/Data Bus. A 8–bit multiplexed address/data bus.

DS2153Q REGISTER MAP

ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME

00 R BPV or Code Violation Count 1 20 R/W Transmit Align Frame 01 R BPV or Code Violation Count 2 21 R/W Transmit Non–Align Frame 02 R CRC4 Count 1/FAS Error Count

1 03 R CRC4 Error Count 2 23 R/W Transmit Channel Blocking 2 04 R E–Bit Count 1/FAS Error Count

2 05 R E–Bit Count 2 25 R/W Transmit Channel Blocking 4 06 R Status 1 26 R/W Transmit Idle 1 07 R Status 2 27 R/W Transmit Idle 2 08 R/W Receive Information 28 R/W Transmit Idle 3 10 R/W Receive Control 1 29 R/W Transmit Idle 4 11 R/W Receive Control 2 2A R/W Transmit Idle Definition 12 R/W Transmit Control 1 2B R/W Receive Channel Blocking 1 13 R/W Transmit Control 2 2C R/W Receive Channel Blocking 2 14 R/W Common Control 1 2D R/W Receive Channel Blocking 3 15 R/W Test 1 2E R/W Receive Channel Blocking 4 16 R/W Interrupt Mask 1 2F R Receive Align Frame 17 R/W Interrupt Mask 2 18 R/W Line Interface Control 19 R/W Test 2 1A R/W Common Control 2 1B R/W Common Control 3 1E R Synchronizer Status 1F R Receive Non–Align Frame

22 R/W Transmit Channel Blocking 1

24 R/W Transmit Channel Blocking 3

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ADDRESS REGISTER NAMER/WADDRESSREGISTER NAMER/W

30 R Receive Signaling 1 40 R/W Transmit Signaling 1 31 R Receive Signaling 2 41 R/W Transmit Signaling 2 32 R Receive Signaling 3 42 R/W Transmit Signaling 3 33 R Receive Signaling 4 43 R/W Transmit Signaling 4 34 R Receive Signaling 5 44 R/W Transmit Signaling 5 35 R Receive Signaling 6 45 R/W Transmit Signaling 6 36 R Receive Signaling 7 46 R/W Transmit Signaling 7 37 R Receive Signaling 8 47 R/W Transmit Signaling 8 38 R Receive Signaling 9 48 R/W Transmit Signaling 9

39 R Receive Signaling 10 49 R/W Transmit Signaling 10 3A R Receive Signaling 1 1 4A R/W Transmit Signaling 1 1 3B R Receive Signaling 12 4B R/W Transmit Signaling 12 3C R Receive Signaling 13 4C R/W Transmit Signaling 13 3D R Receive Signaling 14 4D R/W Transmit Signaling 14 3E R Receive Signaling 15 4E R/W Transmit Signaling 15 3F R Receive Signaling 16 4F R/W Transmit Signaling 16

DS2153Q

Note: the Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on power–up initialization to insure proper operation.

2.0 PARALLEL PORT

The DS2153Q is controlled via a mutliplexed bidirectional address/data bus by an external microcontroller

terminated and the bus returns to a high impedance state as RD

transitions high in Intel timing or as DS tran-

sitions low in Motorola timing. or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details. The mutliplexed bus on the DS2153Q saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2153Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS WR

pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or RD

pulses. The read cycle is

3.0 CONTROL AND TEST REGISTERS

The operation of the DS2153Q is configured via a set of seven registers. Typically , the control registers are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and three Common Control Registers (CCR1, CCR2 and CCR3). Each of the seven registers are described in this section.

The T est Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power–up, the T est Registers should be set to 00 hex in order for the DS2153Q to operate properly.

022697 7/48

DS2153Q

RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)

(MSB) (LSB)

RSMF RSM RSIO – – FRC SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is pro-

RSM RCR1.6 RSYNC Mode Select.

RSIO RCR1.5 RSYNC I/O Select.

– RCR1.4 Not Assigned. Should be set to zero when written. – RCR1.3 Not Assigned. Should be set to zero when written.

FRC RCR1.2 Frame Resync Criteria.

SYNCE RCR1.1 Sync Enable.

RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated. Must be

grammed in the multiframe mode (RCR1.6=1). 0=RSYNC outputs CAS multiframe boundaries 1=RSYNC outputs CRC4 multiframe boundaries

0=frame mode (see the timing in Section 13) 1=multiframe mode (see the timing in Section 13)

0=RSYNC is an output (depends on RCR1.6) 1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must be set to zero when RCR2.1=0)

0=resync if FAS received in error 3 consecutive times 1=resync if FAS or bit 2 of non–F AS is received in error 3 consecutive times

0=auto resync enabled 1=auto resync disabled

cleared and set again for a subsequent resync.

SYNC/RESYNC CRITERIA Table 3–1

FRAME OR

MULTIFRAME

LEVEL

FAS FAS present in frames N and N +

CRC4 Two valid MF alignment words

CAS Valid MF alignment word found

022697 8/48

SYNC CRITERIA RESYNC CRITERIA ITU SPEC.

2, and FAS not present in frame N + 1.

found within 8 ms.

and previous time slot 16 contains code other than all zeros.

Three consecutive incorrect FAS received.

Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non–FAS received.

915 or more CRC4 code words out of 1000 received in error.

Two consecutive MF alignment words received in error.

G.706

4.1.1

4.1.2

G.706

4.2

4.3.2 G.732

5.2

RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE –

SYMBOL POSITION NAME AND DESCRIPTION

Sa8S RCR2.7 Sa8 Bit Select. Set to one to report the Sa8 bit at the RLINK pin; set to zero

to not report the Sa8 bit.

Sa7S RCR2.6 Sa7 Bit Select. Set to one to report the Sa7 bit at the RLINK pin; set to zero

to not report the Sa7 bit.

Sa6S RCR2.5 Sa6 Bit Select. Set to one to report the Sa6 bit at the RLINK pin; set to zero

to not report the Sa6 bit.

Sa5S RCR2.4 Sa5 Bit Select. Set to one to report the Sa5 bit at the RLINK pin; set to zero

to not report the Sa5 bit.

Sa4S RCR2.3 Sa4 Bit Select. Set to one to report the Sa4 bit at the RLINK pin; set to zero

to not report the Sa4 bit.

RSCLKM RCR2.2 Receive Side SYSCLK Mode Select.

0=if SYSCLK is 1.544 MHz 1=if SYSCLK is 2.048 MHz

RESE RCR2.1 Receive Side Elastic Store Enable.

0=elastic store is bypassed 1=elastic store is enabled

– RCR2.0 Not Assigned. Should be set to zero when written.

DS2153Q

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)

(MSB) (LSB)

–

SYMBOL POSITION NAME AND DESCRIPTION

– TCR1.7 Not Assigned. Should be set to zero when written to.

TFPT TCR1.6 Transmit Timeslot 0 Pass Through.

T16S TCR1.5 T ransmit T imeslot 16 Data Select .

TUA1 TCR1.4 Transmit Unframed All Ones.

TSiS TCR1.3 Transmit International Bit Select.

TFPT T16S TUA1 TSiS TSA1 TSM TSIO

0=FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1=FAS bits/Sa bits/Remote Alarm sourced from TSER

0=sample timeslot 16 at TSER pin 1=source timeslot 16 from TS1 to TS16 registers

0=transmit data normally 1=transmit an unframed all one’s code at TPOS and TNEG

0=sample Si bits at TSER pin 1=source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0)

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DS2153Q

TSA1 TCR1.2 Transmit Signaling All Ones.

0=normal operation 1=force timeslot 16 in every frame to all ones

TSM TCR1.1 TSYNC Mode Select.

0=frame mode (see the timing in Section 13) 1=CAS and CRC4 multiframe mode (see the timing in Section 13)

TSIO TCR1.0 TSYNC I/O Select.

0=TSYNC is an input 1=TSYNC is an output

Note: See Figure 13–9 for more details about how the Transmit Control Registers affect the operation of the DS2153Q.

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S – AEBE P16F

SYMBOL POSITION NAME AND DESCRIPTION

Sa8S TCR2.7 Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set to

Sa7S TCR2.6 Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK pin; set to

Sa6S TCR2.5 Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK pin; set to

Sa5S TCR2.4 Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK pin; set to

Sa4S TCR2.3 Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK pin; set to

– TCR2.2 Not Assigned. Should be set to zero when written.

AEBE TCR2.1 Automatic E–Bit Enable.

P16F TCR2.0 Function of Pin 16.

zero to not source the Sa8 bit.

zero to not source the Sa7 bit.

zero to not source the Sa6 bit.

zero to not source the Sa5 bit.

zero to not source the Sa4 bit.

0=E–bits not automatically set in the transmit direction 1=E–bits automatically set in the transmit direction

0=Receive Loss of Sync (RLOS) 1=Loss of Transmit Clock (LOTC)

CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)

(MSB) (LSB)

FLB

SYMBOL POSITION NAME AND DESCRIPTION

FLB CCR1.7 Framer Loopback.

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THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4

0=loopback disabled 1=loopback enabled

DS2153Q

THDB3 CCR1.6 Transmit HDB3 Enable.

0=HDB3 disabled 1=HDB3 enabled

TG802 CCR1.5 Transmit G.802 Enable. See Section 13 for details.

0=do not force TCHBLK high during bit 1 of timeslot 26 1=force TCHBLK high during bit 1 of timeslot 26

TCRC4 CCR1.4 Transmit CRC4 Enable.

0=CRC4 disabled 1=CRC4 enabled

RSM CCR1.3 Receive Signaling Mode Select.

0=CAS signaling mode 1=CCS signaling mode

RHDB3 CCR1.2 Receive HDB3 Enable.

0=HDB3 disabled 1=HDB3 enabled

RG802 CCR1.1 Receive G.802 Enable. See Section 13 for details.

0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26

RCRC4 CCR1.0 Receive CRC4 Enable.

0=CRC4 disabled 1=CRC4 enabled

FRAMER LOOPBACK

When CCR1.7 is set to a one, the DS2153Q will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur:

1. data will be transmitted as normal at TTIP and TRING

2. data off the E1 line at RTIP and RRING will be ignored

3. the RCLK output will be replaced with the TCLK input.

CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)

(MSB) (LSB)

ECUS

SYMBOL POSITION NAME AND DESCRIPTION

ECUS CCR2.7 Error Counter Update Select.

VCRFS CCR2.6 VCR Function Select.

AAIS CCR2.5 Automatic AIS Generation.

ARA CCR2.4 Automatic Remote Alarm Generation.

VCRFS AAIS ARA RSERC LOTCMC RLB LLB

0=update error counters once a second 1=update error counters every 62.5 ms (500 frames)

0=count BiPolar Violations (BPVs) 1=count Code Violations (CVs)

0=disabled 1=enabled

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DS2153Q

RSERC CCR2.3 RSER Control.

LOTCMC CCR2.2 Loss of Transmit Clock Mux Control. Determines whether the transmit

RLB CCR2.1 Remote Loopback.

LLB CCR2.0 Local Loopback.

REMOTE LOOPBACK

When CCR2.1 is set to a one, the DS2153Q will be forced into Remote LoopBack (RLB). In this loopback, data recovered off of the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line (with any BPV’s that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2153Q as it would normally and the data at the TSER pin will be ignored. Data in this loopback will pass through the jitter attenuator. Please see Figure 1.1 for more details.

LOCAL LOOPBACK

When CCR2.0 is set to a one, the DS2153Q will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through

0=allow RSER to output data as received under all conditions 1=force RSER to one under loss of frame alignment conditions

side formatter should switch to the ever present RCLK if the TCLK should fail to transition (see Figure 1.1). 0=do not switch to RCLK if TCLK stops 1=switch to RCLK if TCLK stops

0=loopback disabled 1=loopback enabled

the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator . Please see Figure 1.1 for more details.

AUTOMATIC ALARM GENERATION

When either CCR2.4 or CCR2.5 is set to one, the DS2153Q monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the DS2151Q will either force an AIS alarm (if CCR2.5=1) or a Remote Alarm (CCR2.4=1) to be transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)

(MSB) (LSB)

TESE TCBFS TIRFS ESR LIRST – TSCLKM –

SYMBOL POSITION NAME AND DESCRIPTION

TESE CCR3.7 Transmit Elastic Store Enable.

TCBFS CCR3.6 Transmit Channel Blocking Registers (TCBR) Function Select.

TIRFS CCR3.5 T ransmit Idle Registers (TIR) Function Select.

ESR CCR3.4 Elastic Stores Reset. Setting this bit from a one to a zero will force the

022697 12/48

0 = elastic store is disabled 1 = elastic store is enabled

0=TCBRs define the operation of the TCHBLK output pin 1=TCBRs define which signaling bits are to be inserted

0=TIRs define in which channels to insert idle code 1=TIRs define in which channels to insert data from RSER

elastic stores to a known depth. Should be toggled after SYSCLK has been

DS2153Q

applied and is stable. Must be set and cleared again for a subsequent reset. Do not leave this bit set high.

LIRST CCR3.3 Line Interface Reset. Setting this bit from a zero to a one will initiate an

internal reset that affects the slicer, AGC, clock recovery state machine, and jitter attenuator . Normally this bit is only toggled on power–up. Must be cleared and set again for a subsequent reset.

– CCR3.2 Not Assigned. Should be set to zero when written.

TSCLKM CCR3.1 T ransmit Backplane Clock Select. Must be set like RCR2.2.

0 = 1.544 MHz 1 = 2.048 MHz

– CCR3.0 Not Assigned. Should be set to zero when written.

POWER–UP SEQUENCE

On power–up, after the supplies are stable, the DS2153Q should be configured for operation by writing to all of the internal registers (this includes the T est Registers) since the contents of the internal registers cannot be predicted on power–up. Next, the LIRST bit should be toggled from zero to one to reset the line interface circuitry (it will take the DS2153Q about 40 ms to recover from the LIRST bit being toggled). Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a zero to a one and back to zero (this step can be skipped if the elastic store is not being used).

4.0 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real time status of the DS2153Q, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. All of the bits in these registers operate in a latched fashion (except for the SSR). This means that if an event occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again or if the alarm is still present.

The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will write a

byte to one of these three registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with current value and it will be cleared. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND’ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write–read–write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2153Q with higher–order software languages.

The SSR register operates differently than the other three. It is a read only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this registers with a write.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1

and INT2 pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.

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DS2153Q

RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)

(MSB) (LSB)

TESF TESE JALT RESF RESE CRCRC FASRC CASRC

SYMBOL POSITION NAME AND DESCRIPTION

TESF RIR.7 Transmit Elastic Store Full. Set when the elastic store fills and a frame is

TESE RIR.6 Transmit Elastic Store Empty . Set when the elastic store empties and a

JALT RIR.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to

RESF RIR.4 Elastic Store Full. Set when the elastic store buffer fills and a frame is

RESE RIR.3 Elastic Store Empty. Set when the elastic store buffer empties and a

CRCRC RIR.2 CRC Resync Criteria Met. Set when 915/1000 code words are received in

FASRC RIR.1 FAS Resync Criteria Met. Set when three consecutive FAS words are

CASRC RIR.0 CAS Resync Criteria Met. Set when two consecutive CAS MF alignment

deleted.

frame is repeated.

within 4–bits of it’s limit; useful for debugging jitter attenuation operation.

deleted.

frame is repeated.

error.

received in error.

words are received in error.

SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)

(MSB) (LSB)

CSC5

SYMBOL POSITION NAME AND DESCRIPTION

CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6–bit counter. CSC4 SSR.6 CRC4 Sync Counter Bit 4. CSC3 SSR.5 CRC4 Sync Counter Bit 3. CSC2 SSR.4 CRC4 Sync Counter Bit 2. CSC0 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB bit is

FASSA SSR.2 F AS Sync Active. Set while the synchronizer is searching for alignment at

CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching for the CAS

CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching for the

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CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA

not accessible. This bit will toggle each time the CRC4 MF search times out at 8 ms.

the FAS level.

MF alignment word.

CRC4 MF alignment word.

DS2153Q

CRC4 SYNC COUNTER

The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode

amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.

(CCR1.0=0). This counter is useful for determining the

SR1: STATUS REGISTER 1 (Address=06 Hex)

(MSB) (LSB)

RSA1

SYMBOL POSITION NAME AND DESCRIPTION

RSA1 SR1.7 Receive Signaling All Ones. Set when the contents of timeslot 16 con-

RDMA SR1.6 Receive Distant MF Alarm. Set when bit 6 of timeslot 16 in frame 0 has

RSA0 SR1.5 Receive Signaling All Zeros. Set when over a full MF, timeslot 16 con-

RSLIP SR1.4 Receive Elastic Store Slip Occurrence. Set when the elastic store has

RUA1 SR1.3 Receive Unframed All Ones. Set when an unframed all ones code is

RRA SR1.2 Receive Remote Alarm. Set when a remote alarm is received at RTIP and

RCL SR1.1 Receive Carrier Loss. Set when 255 consecutive zeros have been

RLOS SR1.0 Receive Loss of Sync. Set when the device is not synchronized to the

RDMA RSA0 RSLIP RUA1 RRA RCL RLOS

tains less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.

been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.

tains all zeros.

either repeated or deleted a frame of data.

received at RTIP and RRING.

RRING.

detected at RTIP and RRING.

receive E1 stream.

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