Rainbow Electronics DS2152 User Manual
DS2152
PRELIMINARY
DS2152
Enhanced T1 Single Chip Transceiver
FEATURES
• Complete DS1/ISDN–PRI transceiver functionality
• Line interface can handle both long and short haul
trunks
• 32–bit or 128–bit crystal–less jitter attenuator
• Generates DSX–1 and CSU line build outs
• Frames to D4, ESF, and SLC–96
R
formats
• Dual onboard two–frame elastic store slip buffers that
can connect to asynchronous backplanes up to
8.192 MHz
• 8–bit parallel control port that can be used directly on
either multiplexed or non–multiplexed buses (Intel or
Motorola)
• Extracts and inserts robbed bit signaling
• Detects and generates yellow (RAI) and blue (AIS)
alarms
• Programmable output clocks for Fractional T1
• Fully independent transmit and receive functionality
• Integral HDLC controller with 16–byte buffers for the
FDL
• Generates and detects in–band loop codes from 1 to
8 bits in length including CSU loop codes
• Contains ANSI one’s density monitor and enforcer
• Large path and line error counters including BPV , CV ,
CRC6, and framing bit errors
• Pin compatible with DS2154 E1 Enhanced Single–
Chip Transceiver
• 5V supply; low power CMOS
• 100–pin 14mm
2
body LQFP package
PIN ASSIGNMENT
100
1
ORDERING INFORMATION
DS2152L (0°C to 70°C)
DS2152LN (–40°C to +85°C)
DESCRIPTION
The DS2152 T1 Enhanced Single–Chip Transceiver
contains all of the necessary functions for connection to
T1 lines whether they be DS–1 long haul or DSX–1 short
haul. The clock recovery circuitry automatically adjusts
to T1 lines from 0 feet to over 6000 feet in length. The
device can generate both DSX–1 line build outs as well
as CSU line build outs of –7.5 dB, –15 dB, and –22.5 dB.
Copyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
The onboard jitter attenuator (selectable to either 32 bits
or 128 bits) can be placed in either the transmit or
receive data paths. The framer locates the frame and
multiframe boundaries and monitors the data stream for
alarms. It is also used for extracting and inserting
robbed–bit signaling data and FDL data. The device
contains a set of internal registers which the user can
031897 1/79
DS2152
access and control the operation of the unit. Quick
access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI
T1.403–1995, ANSI T1.231–1993, AT&T TR 62411
(12–90), AT&T TR54016, and ITU G.703, G.704,
G.706, G.823, and I.431.
1.0 INTRODUCTION
The DS2152 is a superset version of the popular
DS2151 T1 Single–Chip Transceiver offering the new
features listed below. All of the original features of the
DS2151 have been retained and software created for
the original devices is transferable into the DS2152.
New Features
• option for non–multiplexed bus operation
• crystal–less jitter attenuation
• addtional hardware signaling capability including:
– receive signaling reinsertion to a backplane mul-
tiframe sync
– availability of signaling in a separate PCM data
stream
– signaling freezing
– interrupt generated on change of signaling data
• per–channel code insertion in both transmit and
receive paths
• full HDLC controller for the FDL with 16–byte buffers
in both transmit and receive paths
• RCL, RLOS, RRA, and RAIS alarms now interrupt on
change of state
• 8.192 MHz clock synthesizer
• per–channel loopback
• addition of hardware pins to indicate carrier loss &
signaling freeze
• line interface function can be completely decoupled
from the framer/formatter to allow:
– interface to optical, HDSL, and other NRZ inter-
faces
– be able to “tap” the transmit and receive bipolar
data streams for monitoring purposes
– be able corrupt data and insert framing errors,
CRC errors, etc.
• transmit and receive elastic stores now have indepen-
dent backplane clocks
• ability to monitor one DS0 channel in both the transmit
and receive paths
• access to the data streams in between the framer/for-
matter and the elastic stores
• AIS generation in the line interface that is independent
of loopbacks
• ability to calculate and check CRC6 according to the
Japanese standard
• ability to pass the F–Bit position through the elastic
stores in the 2.048 MHz backplane mode
• programmable in–band loop code generator and
detector
Functional Description
The analog AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RRING and RTIP pins of
the DS2152. The device recovers clock and data from
the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital
serial stream is analyzed to locate the framing/multiframe pattern. The DS2152 contains an active filter that
reconstructs the analog received signal for the non–linear losses that occur in transmission. The device has a
usable receive sensitivity of 0 dB to –36 dB which allows
the device to operate on cables up to 6000 feet in length.
The receive side framer locates D4 (SLC–96) or ESF
multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization,
blue (AIS) and yellow alarms. If needed, the receive
side elastic store can be enabled in order to absorb the
phase and frequency differences between the recovered T1 data stream and an asynchronous backplane
clock which is provided at the RSYSCLK input. The
clock applied at the RSYSCLK input can be either a
2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK
can be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS2152 is totally independent
from the receive side in both the clock requirements and
characteristics. Data off of a backplane can be passed
through a transmit side elastic store if necessary. The
transmit formatter will provide the necessary frame/multiframe data overhead for T1 transmission. Once the
data stream has been prepared for transmission, it is
sent via the jitter attenuation mux to the waveshaping
and line driver functions. The DS2152 will drive the T1
line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and
short haul (DSX–1) lines.
031897 2/79
DS2152
Reader’s Note
This data sheet assumes a particular nomenclature of
the T1 operating environment. In each 125 us frame,
there are 24 eight–bit channels plus a framing bit. It is
assumed that the framing bit is sent first followed by
D4 Superframe (12 frames per multiframe) Multiframe Structure
SLC–96 Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
B8ZS Biploar with 8 Zero Subsitution
CRC Cyclical Redundancy Check
Ft Terminal Framing Pattern in D4
Fs Signaling Framing Pattern in D4
FPS Framing Pattern in ESF
MF Multiframe
BOC Bit Oriented Code
HDLC High Level Data Link Control
FDL Facility Data LInk
channel 1. Each channel is made up of eight bits which
are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following
abbreviations will be used:
031897 3/79
DS2152
DS2152 ENHANCED T1 SINGLE–CHIP TRANSCEIVER Figure 1–1
RCL
RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIGF
RSIG
RSER
RSYNC
RMSYNC
RFSYNC
RDATA
RPOSI
RCLKI
RNEGI
RNEGO
RCLKO
RPOSO
8XCLK
XTALD
MCLK
Synthesizer
8.192 MHz Clock
FDL Extraction
16 Byte Buffer
BOM Detection
12.352 MHz
Clock/
Cystral
Interface
Power Connections
4
LIUC
mux
1.544
MHz
3
Signaling
Timing Control
Receive Side Framer
VCO/PLL
24.7MHz
4
RSYSCLK
TSYNC
Buffer
Sync Control
Store
Elastic
Payload Loopback
sync
clock
data
Per–Channel Code Insert
Channel Marking
Signaling Extraction
One’s Density Monitor
CRC/Frame Error Count
Loop Code Detector
Alarm Detection
Synchronizer
BPV Counter
B8ZS Decoder
Framer Loopback
Remote Loopback
(Can be placed in either tramsmit or receive path)
Jitter Attenuation
Local Loopback
Clock/Data
Recovery
Peak Detect
Filter
TSEO
TDATA
sync
Per–Channel Code Insert
Per–Channel Loopback
Signaling Insertion
Clear Channel
FDL Insertion
Loop Code Generation
F–Bit Insertion
CRC Generation
Yellow Alarm Generation
One’s Density Enforcer
B8ZS Encode
AIS Generation
Transmit Side Formatter
LIU AIS Generation
Wave Shaping
CSU Filters
Line Drivers
TSSYNC
TSYSCLK
TSER
Store
Elastic
clock
data
TSIG
Insertion
Signaling
Hardware
LOTC
mux
TCLK
TCHBLK
Timing Control
TCHCLK
TLINK
TLCLK
FDL Insertion
16–Byte Buffer
BOM Generation
LIUC
TPOSO
TCLKO
TNEGO
TNEGI
mux
TCLKI
TPOSI
INT
D0 to D7/AD0 to AD7
8
MUX
A0 to A6
7
ALE(AS)/A7
RD
WR
(routed to all blocks)
Paralle and Test Control Port
BTS
CS
TEST
(DS)
(R/W)
031897 4/79
RVDD
TVDD
DVDD
RVSS
TVSS
DVSS
RRING
RTIP
TRING
TTIP
PIN LIST Table 1–1
PIN SYMBOL TYPE DESCRIPTION
1 RCHBLK O Receive Channel Block
2 NC – No Connect
3 8MCLK O 8.192 MHz Clock
4 NC – No Connect
5 NC – No Connect
6 RCL O Receive Carrier Loss
7 NC – No Connect
8 NC – No Connect
9 NC – No Connect
10 NC – No Connect
11 BTS I Bus Type Select
12 LIUC I Line Interface Connect
13 8XCLK O Eight Times Clock
14 TEST I Test
15 NC – No Connect
16 RTIP I Receive Analog Tip Input
17 RRING I Receive Analog Ring Input
18 RVDD – Receive Analog Positive Supply
19 RVSS – Receive Analog Signal Ground
20 RVSS – Receive Analog Signal Ground
21 MCLK I Master Clock Input
22 XTALD O Quartz Crystal Driver
23 NC – No Connect
24 RVSS – Receive Analog Signal Ground
25 INT O Interrupt
26 NC – No Connect
27 NC – No Connect
28 NC – No Connect
29 TTIP O Transmit Analog Tip Output
30 TVSS – Transmit Analog Signal Ground
31 TVDD – Transmit Analog Positive Supply
32 TRING O Transmit Analog Ring Output
33 TCHBLK O Transmit Channel Block
34 TLCLK O Transmit Link Clock
DS2152
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DS2152
PIN DESCRIPTIONTYPESYMBOL
35 TLINK I Transmit Link Data
36 NC – No Connect
37 TSYNC I/O Transmit Sync
38 TPOSI I Transmit Positive Data Input
39 TNEGI I Transmit Negative Data Input
40 TCLKI I Transmit Clock Input
41 TCLKO O T ransmit Clock Output
42 TNEGO O Transmit Negative Data Output
43 TPOSO O T ransmit Positive Data Output
44 DVDD – Digital Positive Supply
45 DVSS – Digital Signal Ground
46 TCLK I Transmit Clock
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
49 TESO O Transmit Elastic Store Output
50 TDATA I Transmit Data
51 TSYSCLK I Transmit System Clock
52 TSSYNC I Transmit System Sync
53 TCHCLK O Transmit Channel Clock
54 NC – No Connect
55 MUX I Bus Operation
56 D0/AD0 I/O Data Bus Bit 0 / Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit 1 / Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2 / Address/Data Bus Bit 2
59 D3/AD3 I/O Data Bus Bit 3 / Address/Data Bus Bit 3
60 DVSS – Digital Signal Ground
61 DVDD – Digital Positive Supply .
62 D4/AD4 I/O Data Bus Bit 4 / Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5 / Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6 / Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7 / Address/Data Bus Bit 7
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
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PIN DESCRIPTIONTYPESYMBOL
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 A7/ALE I Address Bus Bit 7 / Address Latch Enable
74 RD (DS) I Read Input (Data Strobe)
75 CS I Chip Select
76 NC – No Connect
77 WR (R/W) I Write Input (Read/Write)
78 RLINK O Receive Link Data
79 RLCLK O Receive Link Clock
80 DVSS – Digital SIgnal Ground
81 DVDD – Digital Positive Supply
82 RCLK O Receive Clock
83 DVDD – Digital Positive Supply
84 DVSS – Digital Signal Ground
85 RDATA O Receive Data
86 RPOSI I Receive Positive Data Input
87 RNEGI I Receive Negative Data Input
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
90 RNEGO O Receive Negative Data Output
91 RPOSO O Receive Positive Data Output
92 RCHCLK O Receive Channel Clock
93 RSIGF O Receive Signaling Freeze Output
94 RSIG O Receive Signaling Output
95 RSER O Receive Serial Data
96 RMSYNC O Receive Multiframe Sync
97 RFSYNC O Receive Frame Sync
98 RSYNC I/O Receive Sync
99 RLOS/LOTC O Receive Loss Of Sync / Loss Of Transmit Clock
100 RSYSCLK I Receive System Clock
DS2152
NOTE:
Leave all no connect (NC) pins open circuited.
031897 7/79
DS2152
DS2152 PIN DESCRIPTION Table 1–2
TRANSMIT SIDE DIGITAL PINS
Transmit Clock [TCLK]. A 1.544 MHz primary clock.
Used to clock data through the transmit side formatter.
this pin is set to output pulses at frame boundaries, it can
also be set via TCR2.4 to output double–wide pulses at
signaling frames. See Section 15 for details.
Transmit Serial Data [TSER]. Transmit NRZ serial
data. Sampled on the falling edge of TCLK when the
transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic
store is enabled.
Transmit Channel Clock [TCHCLK]. A 192 KHz clock
which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic
store is disabled. Synchronous with TSYSCLK when
the transmit side elastic store is enabled. Useful for parallel to serial conversion of channel data.
Transmit Channel Block [TCHBLK]. A user programmable output that can be forced high or low during any of
the 24 T1 channels. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous
with TSYSCLK when the transmit side elastic store is
enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384 Kbps (H0),
768 Kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications, for external per–channel loopback, and for per–channel conditioning. See Section 9 for details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the transmit side
elastic store function is enabled. Should be tied low in
applications that do not use the transmit side elastic
store. Can be burst at rates up to 8.192 MHz.
Transmit Link Clock [TLCLK]. 4 KHz or 2 KHz
(ZBTSI) demand clock for the TLINK input. See Section
11 for details.Transmit Link Data [TLINK].
Transmit Link Data [TLINK]. If enabled via TCR1.2,
this pin will be sampled on the falling edge of TCLK for
data insertion into either the FDL stream (ESF) or the
Fs–bit position (D4) or the Z–bit position (ZBTSI). See
Section 11 for details.
Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS2152 can be programmed
to output either a frame or multiframe pulse at this pin. If
Transmit System Sync [TSSYNC]. Only used when
the transmit side elastic store is enabled. A pulse at this
pin will establish either frame or multiframe boundaries
for the transmit side. Should be tied low in applications
that do not use the transmit side elastic store.
Transmit Signaling Input [TSIG]. When enabled, this
input will sample signaling bits for reinsertion into outgoing PCM T1 data stream. Sampled on the falling edge
of TCLK when the transmit side elastic store is disabled.
Sampled on the falling edge of TSYSCLK when the
transmit side elastic store is enabled.
Transmit Elastic Store Data Output [TESO].
Updated on the rising edge of TCLK with data out of the
the transmit side elastic store whether the elastic store
is enabled or not. This pin is normally tied to TDATA.
Transmit Data [TDATA]. Sampled on the falling edge
of TCLK with data to be clocked through the transmit
side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO]. Updated on
the rising edge of TCLKO with the bipolar data out of the
transmit side formatter. Can be programmed to source
NRZ data via the Output Data Format (CCR1.6) control
bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated
on the rising edge of TCLKO with the bipolar data out of
the transmit side formatter . This pin is normally tied to
TNEGI.
Transmit Clock Output [TCLKO]. Buf fered clock that
is used to clock data through the transmit side formatter
(i.e., either TCLK or RCLKI). This pin is normally tied to
TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on
the falling edge of TCLKI for data to be transmitted out
onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC pin high. TPOSI and TNEGI can be
tied together in NRZ applications.
Transmit Negative Data Input [TNEGI]. Sampled on
the falling edge of TCLKI for data to be transmitted out
031897 8/79
DS2152
onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC pin high. TPOSI and TNEGI can be
tied together in NRZ applications.
Transmit Clock Input [TCLKI]. Line interface transmit
clock. Can be internally connected to TCLKO by tying
the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with either FDL
data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK
before the start of a frame. See Section 15 for details.
Receive Link Clock [RLCLK]. A 4 KHz or 2 KHz
(ZBTSI) clock for the RLINK output.
Receive Clock [RCLK]. 1.544 MHz clock that is used
to clock data through the receive side framer.
Receive Channel Clock [RCHCLK]. A 192 KHz clock
which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when
the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data.
Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low during any of
the 24 T1 channels. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with
RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for external per–channel loopback, and for per–channel conditioning. See Section 9 for details.
Receive Serial Data [RSER]. Received NRZ serial
data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive side elastic
store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one
RCLK wide, is output at this pin which identifies either
frame (RCR2.4=0) or multiframe (RCR2.4=1) boundaries. If set to output frame boundaries then via
RCR2.5, RSYNC can also be set to output double–wide
pulses on signaling frames. If the receive side elastic
store is enabled via CCR1.2, then this pin can be
enabled to be an input via RCR2.3 at which a frame or
multiframe boundary pulse is applied. See Section 15
for details.
Receive Frame Sync [RFSYNC]. An extracted 8 KHz
pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
Receive Multiframe Sync [RMSYNC]. Only used
when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this
pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Receive Data [RDA T A]. Updated on the rising edge of
RCLK with the data out of the receive side framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications
that do not use the elastic store. Can be burst at rates up
to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling
bits in a PCM format. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated
on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Loss of Sync / Loss of Transmit Clock
[RLOS/LOTC]. A dual function output that is controlled
by the CCR3.5 control bit. This pin can be programmed
to either toggle high when the synchronizer is searching
for the frame and multiframe or to toggle high if the TCLK
pin has not been toggled for 5 usec.
Receive Carrier Loss [RCL]. Set high when the line
interface detects a loss of carrier.
Receive Signaling Freeze [RSIGF]. Set high when the
signaling data is frozen via either automatic or manual
intervention. Used to alert downstream equipment of
the condition.
8 MHz Clock [8MCLK]. A 8.192 MHz output clock that
is referenced to the clock that is output at the RCLK pin
031897 9/79
DS2152
and is used to clock data through the receive side
framer.
Receive Positive Data Output [RPOSO]. Updated on
the rising edge of RCLKO with the bipolar data out of the
line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated
on the rising edge of RCLKO with the bipolar data out of
the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered
clock from the T1 line. This pin is normally tied to RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on
the falling edge of RCLKI for data to be clocked through
the receive side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input [RNEGI]. Sampled on
the falling edge of RCLKI for data to be clocked through
the receive side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input [RCLKI]. Clock used to clock
data through the receive side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC pin high.
PARALLEL CONTROL PORT PINS
Interrupt [INT]. Flags host controller during conditions
and change of conditions defined in the Status Registers 1 and 2 and the FDL Status Register. Active low,
open drain output.
3–State Control [Test]. Set high to 3–state all output
and I/O pins (including the parallel control port). Set low
for normal operation. Useful in board level testing.
Bus Operation [MUX]. Set low to select non–multiplexed bus operation. Set high to select multiplexed bus
operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to
AD7]. In non–multiplexed bus operation (MUX = 0),
serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as a 8–bit multiplexed address / data
bus.
Address Bus [A0 to A6]. In non–multiplexed bus
operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not
used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola
bus timing; strap low to select Intel bus timing. This pin
controls the function of the RD
(DS), ALE(AS), and
WR(R/W) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Read Input [RD
] (Data Strobe [DS]). RD and DS are
active low signals.
Chip Select [CS
]. Must be low to read or write to the
device. CS is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe
[AS]). In non–multiplexed bus operation (MUX = 0),
serves as the upper address bit. In multiplexed bus
operation (MUX = 1), serves to demultiplex the bus on a
positive–going edge.
Write Input [WR
] (Read/Write [R/W]). WR is an active
low signal.
LINE INTERFACE PINS
Master Clock Input [MCLK]. A 1.544 MHz (± 50 ppm)
clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and
for jitter attenuation. A quartz crystal of 1.544 MHz may
be applied across MCLK and XTALD instead of the TTL
level clock source.
Quartz Crystal Driver [XTALD]. A quartz crystal of
1.544 MHz may be applied across MCLK and XTALD
instead of a TTL level clock source at MCLK. Leave
open circuited if a TTL clock source is applied at MCLK.
Eight Times Clock [8XCLK]. A 12.352 MHz clock that
is frequency locked to the 1.544 MHz clock provided
from the clock/data recovery block (if the jitter attenuator
is enabled on the receive side) or from the TCLKI pin (if
the jitter attenuator is enabled on the transmit side). Can
be internally disabled via the TEST2 register if not
needed.
Line Interface Connect [LIUC]. Tie low to separate the
line interface circuitry from the framer/formatter circuitry
and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/
031897 10/79
DS2152
RCLKI pins. Tie high to connect the the line interface circuitry to the framer/formatter circuitry and deactivate
Receive Analog Positive Supply [RVDD]. 5.0 volts ±
5%. Should be tied to the DVDD and TVDD pins.
the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins.
When LIUC is tied high, the TPOSI/TNEGI/TCLKI/
RPOSI/RNEGI/RCLKI pins should be tied low.
Receive Tip and Ring [RTIP & RRING]. Analog inputs
for clock recovery circuitry. These pins connect via a 1:1
Transmit Analog Positive Supply [TVDD]. 5.0 volts ±
5%. Should be tied to the RVDD and DVDD pins.
Digital Signal Ground [DVSS]. Should be tied to the
RVSS and TVSS pins.
transformer to the T1 line. See Section 14 for details.
Receive Analog Signal Ground [RVSS]. 0.0 volts.
Transmit Tip and Ring [TTIP & TRING]. Analog line
Should be tied to the DVSS and TVSS pins.
driver outputs. These pins connect via a 1:1.15 or
1:1.36 step–up transformer to the T1 line. See Section
14 for details.
Transmit Analog Ground [TVSS]. 0.0 volts. Should
be tied to the RVSS and DVSS pins.
SUPPLY PINS
Digital Positive Supply [DVDD]. 5.0 volts ± 5%.
Should be tied to the RVDD and TVDD pins.
DS2152 REGISTER MAP Table 1–3
ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION
00 R/W FDL Control FDLC
01 R/W FDL Status FDLS
02 R/W FDL Interrupt Mask FIMR
03 R/W Receive Performance Report Message RPRM
04 R/W Receive Bit Oriented Code RBOC
05 R Receive FDL FIFO RFFR
06 R/W Transmit Performance Report Message TPRM
07 R/W Transmit Bit Oriented Code TBOC
08 W Transmit FDL FIFO TFFR
09 R/W Test 2 TEST2 (set to 00h)
0A R/W Common Control 7 CCR7
0B – not present –
0C – not present –
0D – not present –
0E – not present –
0F R Device ID IDR
10 R/W Receive Information 3 RIR3
11 R/W Common Control 4 CCR4
12 R/W In–Band Code Control IBCC
031897 11/79
DS2152
ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W
13 R/W Transmit Code Definition TCD
14 R/W Receive Up Code Definition RUPCD
15 R/W Receive Down Code Definition RDNCD
16 R/W Transmit Channel Control 1 TCC1
17 R/W Transmit Channel Control 2 TCC2
18 R/W Transmit Channel Control 3 TCC3
19 R/W Common Control 5 CCR5
1A R Transmit DS0 Monitor TDS0M
1B R/W Receive Channel Control 1 RCC1
1C R/W Receive Channel Control 2 RCC2
1D R/W Receive Channel Control 3 RCC3
1E R/W Common Control 6 CCR6
1F R Receive DS0 Monitor RDS0M
20 R/W Status 1 SR1
21 R/W Status 2 SR2
22 R/W Receive Information 1 RIR1
23 R Line Code Violation Count 1 LCVCR1
24 R Line Code Violation Count 2 LCVCR2
25 R Path Code Violation Count 1 PCVCR1
26 R Path Code violation Count 2 PCVCR2
27 R Multiframe Out of Sync Count 2 MOSCR2
28 R Receive FDL Register RFDL
29 R/W Receive FDL Match 1 RMTCH1
2A R/W Receive FDL Match 2 RMTCH2
2B R/W Receive Control 1 RCR1
2C R/W Receive Control 2 RCR2
2D R/W Receive Mark 1 RMR1
2E R/W Receive Mark 2 RMR2
2F R/W Receive Mark 3 RMR3
30 R/W Common Control 3 CCR3
31 R/W Receive Information 2 RIR2
32 R/W Transmit Channel Blocking 1 TCBR1
33 R/W Transmit Channel blocking 2 TCBR2
031897 12/79
ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W
34 R/W Transmit Channel Blocking 3 TCBR3
35 R/W Transmit Control 1 TCR1
36 R/W Transmit Control 2 TCR2
37 R/W Common Control 1 CCR1
38 R/W Common Control 2 CCR2
39 R/W Transmit Transparency 1 TTR1
3A R/W T ransmit Transparency 2 TTR2
3B R/W T ransmit Transparency 3 TTR3
3C R/W Transmit Idle 1 TIR1
3D R/W Transmit Idle 2 TIR2
3E R/W T ransmit Idle 3 TIR3
3F R/W Transmit Idle Definition TIDR
40 R/W Transmit Channel 9 TC9
41 R/W Transmit Channel 10 TC10
42 R/W Transmit Channel 11 TC11
43 R/W Transmit Channel 12 TC12
44 R/W Transmit Channel 13 TC13
45 R/W Transmit Channel 14 TC14
46 R/W Transmit Channel 15 TC15
47 R/W Transmit Channel 16 TC16
48 R/W Transmit Channel 17 TC17
49 R/W Transmit Channel 18 TC18
4A R/W T ransmit Channel 19 TC19
4B R/W T ransmit Channel 20 TC20
4C R/W Transmit Channel 21 TC21
4D R/W Transmit Channel 22 TC22
4E R/W T ransmit Channel 23 TC23
4F R/W Transmit Channel 24 TC24
50 R/W Transmit Channel 1 TC1
51 R/W Transmit Channel 2 TC2
52 R/W Transmit Channel 3 TC3
53 R/W Transmit Channel 4 TC4
54 R/W Transmit Channel 5 TC5
DS2152
031897 13/79
DS2152
ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W
55 R/W Transmit Channel 6 TC6
56 R/W Transmit Channel 7 TC7
57 R/W Transmit Channel 8 TC8
58 R/W Receive Channel 1 RC17
59 R/W Receive Channel 18 RC18
5A R/W Receive Channel 19 RC19
5B R/W Receive Channel 20 RC20
5C R/W Receive Channel 21 RC21
5D R/W Receive Channel 22 RC22
5E R/W Receive Channel 23 RC23
5F R/W Receive Channel 24 RC24
60 R Receive Signaling 1 RS1
61 R Receive Signaling 2 RS2
62 R Receive Signaling 3 RS3
63 R Receive Signaling 4 RS4
64 R Receive Signaling 5 RS5
65 R Receive Signaling 6 RS6
66 R Receive Signaling 7 RS7
67 R Receive Signaling 8 RS8
68 R Receive Signaling 9 RS9
69 R Receive Signaling 10 RS10
6A R Receive Signaling 11 RS11
6B R Receive Signaling 12 RS12
6C R/W Receive Channel Blocking 1 RCBR1
6D R/W Receive Channel Blocking 2 RCBR2
6E R/W Receive Channel Blocking 3 RCBR3
6F R/W Interrupt Mask 2 IMR2
70 R/W Transmit Signaling 1 TS1
71 R/W Transmit Signaling 2 TS2
72 R/W Transmit Signaling 3 TS3
73 R/W Transmit Signaling 4 TS4
74 R/W Transmit Signaling 5 TS5
75 R/W Transmit Signaling 6 TS6
031897 14/79
DS2152
ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W
76 R/W Transmit Signaling 7 TS7
77 R/W Transmit Signaling 8 TS8
78 R/W Transmit Signaling 9 TS9
79 R/W Transmit Signaling 10 TS10
7A R/W T ransmit Signaling 11 TS11
7B R/W T ransmit Signaling 12 TS12
7C R/W Line Interface Control LICR
7D R/W Test 1 TEST1 (set to 00h)
7E R/W T ransmit FDL Register TFDL
7F R/W Interrupt Mask Register 1 IMR1
80 R/W Receive Channel 1 RC1
81 R/W Receive Channel 2 RC2
82 R/W Receive Channel 3 RC3
83 R/W Receive Channel 4 RC4
84 R/W Receive Channel 5 RC5
85 R/W Receive Channel 6 RC6
86 R/W Receive Channel 7 RC7
87 R/W Receive Channel 8 RC8
88 R/W Receive Channel 9 RC9
89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15
8F R/W Receive Channel 16 RC16
NOTES:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on power–up initialization to insure proper operation.
2. Register banks 9xh, Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
2.0 PARALLEL PORT
The DS2152 is controlled via either a non–multiplexed
(MUX = 0) or a multiplexed (MUX = 1) bus by an external
microcontroller or microprocessor. The DS2152 can
operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be
selected; if tied high, Motorola timing will be selected.
All Motorola bus signals are listed in parenthesis (). See
the timing diagrams in the A.C. Electrical Characteristics in Section 16 for more details.
031897 15/79
DS2152
3.0 CONTROL, ID AND TEST REGISTER
The operation of the DS2152 is configured via a set of
eleven control registers. Typically, the control registers
are only accessed when the system is first powered up.
Once the DS2152 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two
Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and
seven Common Control Registers (CCR1 to CCR7).
There is a device IDentification Register (IDR) at
address 0Fh. The MSB of this read–only register is
fixed to a zero indicating that the DS2152 is present.
The E1 pin–for–pin compatible version of the DS2152 is
the DS2154 and it also has an ID register at address 0Fh
and the user can read the MSB to determine which chip
is present since in the DS2152 the MSB will be set to a
zero and in the DS2154 it will be set to a one. The lower
four bits of the IDR are used to display the die revision of
the chip.
Each of the eleven registers are described in this
section.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB) (LSB)
T1E1 0 0 0 ID3 ID2 ID1 ID0
SYMBOL POSITION NAME AND DESCRIPTION
T1E1 IDR.7 T1 or E1 Chip Determination Bit.
ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revi-
ID2 IDR.1 Chip Revision Bit 2.
ID1 IDR.2 Chip Revision Bit 1.
ID0 IDR.0 Chip Revision Bit 0. LSB of a decimal code that represents the chip revi-
The two T est Registers at addresses 09 and 7D hex are used by the factory in testing the DS2152. On power–up, the
Test Registers should be set to 00 hex in order for the DS2152 to operate properly.
0=T1 chip
1=E1 chip
sion.
sion.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) (LSB)
LCVCRF
SYMBOL POSITION NAME AND DESCRIPTION
LCVCRF RCR1.7 Line Code Violation Count Register Function Select.
ARC RCR1.6 Auto Resync Criteria.
OOF1 RCR1.5 Out Of Frame Select 1.
031897 16/79
ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC
0 = do not count excessive zeros
1 = count excessive zeros
0 = Resync on OOF or RCL event
1 = Resync on OOF only
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
DS2152
OOF2 RCR1.4 Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCC RCR1.3 Sync Criteria.
In D4 Framing Mode
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCT RCR1.2 Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
SYNCE RCR1.1 Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNC RCR1.0 Resync. When toggled from low to high, a resynchronization of the receive
side framer is initiated. Must be cleared and set again for a subsequent
resync.
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB) (LSB)
RCS RZBTSI RSDW RSM RSIO RD4YM FSBE MOSCRF
SYMBOL POSITION NAME AND DESCRIPTION
RCS RCR2.7 Receive Code Select. See Section 8 for more details.
RZBTSI RCR2.6 Receive Side ZBTSI Enable.
RSDW RCR2.5 RSYNC Double–Wide. (note: this bit must be set to zero when RCR2.4 = 1
RSM RCR2.4 RSYNC Mode Select. (A Don’t Care if RSYNC is programmed as an input)
RSIO RCR2.3 RSYNC I/O Select. (note: this bit must be set to zero when CCR1.2 = 0)
RD4YM RCR2.2 Receive Side D4 Yellow Alarm Select.
FSBE RCR2.1 PCVCR Fs–Bit Error Report Enable.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
0 = ZBTSI disabled
1 = ZBTSI enabled
or when RCR2.3 = 1)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
0 = frame mode (see the timing in Section 15)
1 = multiframe mode (see the timing in Section 15)
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
0 = do not report bit errors in Fs–bit position; only Ft bit position
1 = report bit errors in Fs–bit position as well as Ft bit position
031897 17/79
DS2152
MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select.
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) (LSB)
LOTCMC
SYMBOL POSITION NAME AND DESCRIPTION
LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control. Determines whether the transmit
TFPT TCR1.6 Transmit F–Bit Pass Through. (see note below)
TCPT TCR1.5 Transmit CRC Pass Through. (see note below)
RBSE TCR1.4 Robbed Bit Signaling Enable. (see note below)
GB7S TCR1.3 Global Bit 7 Stuffing. (see note below)
TFDLS TCR1.2 TFDL Register Select. (see note below)
TBL TCR1.1 Transmit Blue Alarm. (see note below)
TYEL TCR1.0 Transmit Y ellow Alarm. (see note below)
TFPT TCPT RBSE GB7S TFDLS TBL TYEL
side formatter should switch to the ever present RCLKO if the TCLK input
should fail to transition (see Figure 1–1 for details).
0 = do not switch to RCLKO if TCLK stops
1 = switch to RCLKO if TCLK stops
0 = F bits sourced internally
1 = F bits sampled at TSER
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F–bit time
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels (the TTR registers can be used to
block insertion on a channel by channel basis)
0 = allow the TTR registers to determine which channels containing all
zeros are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how the TTR
registers are programmed
0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC controller or the
TLINK pin
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOSO and TNEGO
0 = do not transmit yellow alarm
1 = transmit yellow alarm
NOTE:
For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 15–11.
031897 18/79
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB) (LSB)
TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM TB7ZS
SYMBOL POSITION NAME AND DESCRIPTION
TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3–1.
TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3–1.
TZBTSI TCR2.5 Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSDW TCR2.4 TSYNC Double–Wide. (note: this bit must be set to zero when TCR2.3=1
or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSM TCR2.3 TSYNC Mode Select.
0 = frame mode (see the timing in Section 15)
1 = multiframe mode (see the timing in Section 15)
TSIO TCR2.2 TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TD4YM TCR2.1 Transmit Side D4 Y ellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
TB7ZS TCR2.0 Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a one in channels with all zeros
DS2152
OUTPUT PIN TEST MODES Table 3–1
TEST1TEST
0
0 0
0 1
1 0
1 1
operate normally
force all output pins 3–state (including all I/O pins and parallel port pins)
force all output pins low (including all I/O pins except parallel port pins)
force all output pins high (including all I/O pins except parallel port pins)
EFFECT ON OUTPUT PINS
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
TESE ODF RSAO TSCLKM RSCLKM RESE PLB FLB
SYMBOL POSITION NAME AND DESCRIPTION
TESE CCR1.7 Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
031897 19/79
DS2152
ODF CCR1.6 Output Data Format.
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
RSAO CCR1.5 Receive Signaling All One’ s. This bit should not be enabled if hardware
signaling is being utilized. See Section 7 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKM CCR1.4 TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSCLKM CCR1.3 RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESE CCR1.2 Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLB CCR1.1 Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLB CCR1.0 Framer Loopback.
0 = loopback disabled
1 = loopback enabled
Payload Loopback
When CCR1.1 is set to a one, the DS2152 will be forced
into Payload LoopBack (PLB). Normally, this loopback
is only enabled when ESF framing is being performed
but can be enabled also in D4 framing applications. In a
PLB situation, the DS2152 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped
back, they are reinserted by the DS2152. When PLB is
5. the TLCLK signal will become synchronous with
RCLK instead of TCLK.
Framer Loopback
When CCR1.0 is set to a one, the DS2152 will enter a
Framer LoopBack (FLB) mode. This loopback is useful
in testing and debugging applications. In FLB, the
DS2152 will loop data from the transmit side back to the
receive side. When FLB is enabled, the following will
occur:
enabled, the following will occur:
1. an unframed all one’s code will be transmitted at
1. data will be transmitted from the TPOSO and
TNEGO pins synchronous with RCLK instead of
TCLK
2. all of the receive side signals will continue to operate normally
3. the TCHCLK and TCHBLK signals are forced low
4. data at the TSER, TDATA, and TSIG pins is
TPOSO and TNEGO
2. data at RPOSI and RNEGI will be ignored
3. all receive side signals will take on timing synchronous with TCLK instead of RCLKI.
Please note that it is not acceptable to have RCLK tied
to TCLK during this loopback because this will cause an
unstable condition.
ignored
031897 20/79
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB) (LSB)
TFM TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL
SYMBOL POSITION NAME AND DESCRIPTION
TFM CCR2.7 Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZS CCR2.6 Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
TSLC96 CCR2.5 T ransmit SLC–96 / Fs–Bit Insertion Enable. Only set this bit to a one in
D4 framing applications. Must be set to one to source the Fs pattern. See
Section 11 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
TFDL CCR2.4 Transmit FDL Zero Stuffer Enable. Set this bit to zero if using the internal
HDLC/BOC controller instead of the legacy support for the FDL. See Section 11 for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
RFM CCR2.3 Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZS CCR2.2 Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
RSLC96 CCR2.1 Receive SLC–96 Enable. Only set this bit to a one in D4/SLC–96 framing
applications. See Section 11 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
RFDL CCR2.0 Receive FDL Zero Destuffer Enable. Set this bit to zero if using the inter-
nal HDLC/BOC controller instead of the legacy support for the FDL. See
Section 11 for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
DS2152
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB) (LSB)
ESMDM ESR RLOSF RSMS PDE ECUS TLOOP –
SYMBOL POSITION NAME AND DESCRIPTION
ESMDM CCR3.7 Elastic Store Minimum Delay Mode. See Section 10.3 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
031897 21/79
DS2152
ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elas-
tic stores to a known depth. Should be toggled after RSYSCLK and
TSYSCLK have been applied and are stable. Must be cleared and set
again for a subsequent reset.
RLOSF CCR3.5 Function of the RLOS/LOTC Output.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions
from D4 to ESF . This function is not available when the receive side elastic
store is enabled.
0 = RSYNC will output a pulse at every multfirame
1 = RSYNC will output a pulse at every other multiframe
note: for this bit to have any affect, the RSYNC must be set to output multiframe pulses (RCR2.4=1 and RCR2.3=0).
PDE CCR3.3 Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
ECUS CCR3.2 Error Counter Update Select. See Section 5 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOP CCR3.1 Transmit Loop Code Enable. See Section 12 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as defined in TCD
register
– CCR3.0 Not Assigned. Must be set to zero when written.
Pulse Density Enforcer
The SCT always examines both the transmit and
receive data streams for violations of the following rules
which are required by ANSI T1.403:
When the CCR3.3 is set to one, the DS2152 will force
the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running
B8ZS, the CCR3.3 bit should be set to zero since B8ZS
encoded data streams cannot violate the pulse density
– no more than 15 consecutive zeros
requirements.
– at least N ones in each and every time window
of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are
reported in the RIR2.0 and RIR2.1 bits respectively .
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB) (LSB)
RSRE RPCSI RFSA1 RFE RFF TSRE TPCSI TIRFS
SYMBOL POSITION NAME AND DESCRIPTION
RSRE CCR4.7 Receive Side Signaling Re–Insertion Enable. See Section 7.2 for
031897 22/79
details.
0 = do not re–insert signaling bits into the data stream presented at the
RSER pin
1 = re–insert the signaling bits into data stream presented at the RSER pin
DS2152
RPCSI CCR4.6 Receive Per–Channel Signaling Insert. See Section 7.2 for more details.
0 = do not use RCHBLK to determine which channels should have signaling re–inserted
1 = use RCHBLK to determine which channels should have signaling re–inserted
RFSA1 CCR4.5 Receive Force Signaling All Ones. See Section 7.2 for more details.
0 = do not force extracted robbed–bit signaling bit positions to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFE CCR4.4 Receive Freeze Enable. See Section 7.2 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if CCR4.7
= 1).
RFF CCR4.3 Receive Force Freeze. Freezes receive side signaling at RSIG (and
RSER if CCR4.7=1); will override Receive Freeze Enable (RFE). See Section 7.2 for details.
0 = do not force a freeze event
1 = force a freeze event
TSRE CCR4.2 Transmit Side Signaling Re–Insertion Enable. See Section 7.2 for
details.
0 = do not re–insert signaling bits into the data stream presented at the
TSER pin
1 = re–insert the signaling bits into data stream presented at the TSER pin
TPCSI CCR4.1 Transmit Per–Channel Signaling Insert. See Section 7.2 for details.
0 = do not use TCHBLK to determine which channels should have signaling
re–inserted
1 = use TCHBLK to determine which channels should have signaling re–inserted
TIRFS CCR4.0 Transmit Idle Registers (TIR) Function Select. See Section 8 for timing
details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e.,
Per=Channel Loopback function)
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB) (LSB)
TJC LLB LIAIS TCM4 TCM3 TCM2 TCM1 TCM0
SYMBOL POSITION NAME AND DESCRIPTION
TJC CCR5.7 Transmit Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
LLB CCR5.6 Local Loopback.
0 = loopback disabled
1 = loopback enabled
LIAIS CCR5.5 Line Interface AIS Generation Enable. See Figure 1–1 for details.
0 = allow normal data from TPOSI/TNEGI to be transmitted at TTIP and
TRING
1 = force unframed all ones to be transmitted at TTIP and TRING
031897 23/79
DS2152
TCM4 CCR5.4 Transmit Channel Monitor Bit 4. MSB of a channel decode that deter-
mines which transmit channel data will appear in the TDS0M register. See
Section 6 for details.
TCM3 CCR5.3 Transmit Channel Monitor Bit 3.
TCM2 CCR5.2 Transmit Channel Monitor Bit 2.
TCM1 CCR5.1 Transmit Channel Monitor Bit 1.
TCM0 CCR5.0 Transmit Channel Monitor Bit 0. LSB of the channel decode.
Local Loopback
When CCR5.6 is set to a one, the DS2152 will be forced
into Local LoopBack (LLB). In this loopback, data will
continue to be transmitted as normal through the transmit side of the DS2152 (unless LIAIS = 1). Data being
received at RTIP and RRING will be replaced with the
through the jitter attenuator . Please see Figure 1–1 for
more details. Please note that it is not acceptable to
have RCLKO tied to TCLKI during this loopback
because this will cause an unstable condition. Also it is
recommended that the jitter attenuator be placed on the
transmit side during this loopback.
data being transmitted. Data in this loopback will pass
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB) (LSB)
RJC
SYMBOL POSITION NAME AND DESCRIPTION
RJC CCR6.7 Receive Japanese CRC6 Enable.
– CCR6.6 Not Assigned. Should be set to zero when written.
– CCR6.5 Not Assigned. Should be set to zero when written.
RCM4 CCR6.4 Receive Channel Monitor Bit 4. MSB of a channel decode that deter-
RCM3 CCR6.3 Receive Channel Monitor Bit 3.
RCM2 CCR6.2 Receive Channel Monitor Bit 2.
RCM1 CCR6.1 Receive Channel Monitor Bit 1.
RCM0 CCR6.0 Receive Channel Monitor Bit 0. LSB of the channel decode.
– – RCM4 RCM3 RCM2 RCM1 RCM0
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
mines which receive channel data will appear in the RDS0M register. See
Section 6 for details.
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB) (LSB)
LIRST RLB – – – – – –
SYMBOL POSITION NAME AND DESCRIPTION
LIRST CCR7.7 Line Interface reset. Setting this bit from a zero to a one will initiate an
031897 24/79
internal reset that affects the clock recovery state machine and jitter attenu-
ator. Normally this bit is only toggled on power–up. Must be cleared and set
again for a subsequent reset.
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