Rainbow Electronics DS2151Q User Manual

DS2151Q

DS2151Q

T1 Single–Chip Transceiver

FEATURES

• Complete DS1/ISDN–PRI transceiver functionality

• Line interface can handle both long and short haul

trunks

• 32–bit or 128–bit jitter attenuator

• Generates DSX–1 and CSU line build outs

• Frames to D4, ESF, and SLC–96

R

formats

• Dual onboard two–frame elastic store slip buffers that

connect to backplanes up to 8.192 MHz

• 8–bit parallel control port that can be used on either

multiplexed or non–multiplexed buses

• Extracts and inserts Robbed–Bit signaling

• Detects and generates yellow and blue alarms

• Programmable output clocks for Fractional T1

• Fully independent transmit and receive functionality

• Onboard FDL support circuitry

• Generates and detects CSU loop codes

• Contains ANSI one’s density monitor and enforcer

• Large path and line error counters including BPV , CV ,

CRC6, and framing bit errors

• Pin compatible with DS2153Q E1 Single–Chip Trans-

ceiver

• 5V supply; low power CMOS

• Industrial grade version (–40°C to +85°C) available

(DS2151QN)

DESCRIPTION

The DS2151Q T1 Single–Chip Transceiver (SCT) con­tains all of the necessary functions for connection to T1
lines whether they be DS–1 long haul or DSX–1 short
haul. The clock recovery circuitry automatically adjusts

PIN ASSIGNMENT

Functional Blocks

FRAMER

ELASTIC STORES

LINE INTERFACE

LONG & SHORT HAUL

PARALLEL CONTROL

PORT

DALLAS

DS2151Q

T1 SCT

ALE

WR

RLINK

RLCLK

DVSS
RCLK

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

to T1 lines from 0 feet to over 6000 feet in length. The
device can generate both DSX–1 line build outs as well
as CSU build outs of –7.5 dB, –15 dB, and –22.5 dB.
The onboard jitter attenuator (selectable to either 32 bits

Actual Size of

44–pin PLCC

CSRDAD7

AD6

AD5

AD4

AD3

AD2

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

ACLKI

RCHBLK

BTS

RTIP

1

RVDD

RRING

4443424140

RVSS

XTAL1

AD1

XTAL2

AD0

39
38
37
36
35
34
33
32
31
30
29

INT1

TCHCLK

TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP

INT2

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

022697 1/46

DS2151Q

or 128 bits) can be placed in either the transmit or
receive data paths. The framer locates the frame and
multiframe boundaries and monitors the data stream for
alarms. It is also used for extracting and inserting
Robbed–Bit signaling data and FDL data. The device
contains a set of 64 eight bit internal registers which the
user can access and control the operation of the unit.
Quick access via the parallel control port allows a single
micro to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI
T1.403–199X, A T&T TR 62411 (12–90), and ITU G.703,
G.704, G.706, G.823, and I.431.

TABLE OF CONTENTS

1. Introduction

2. Parallel Control Port

3. Control Registers

4. Status and Information Registers

5. Error Count Registers

6. FDL/Fs Extraction/Insertion

7. Signaling Operation

8. Transmit Transparency and Idle Registers

9. Clock Blocking Registers

10. Elastic Stores Operation

11. Receive Mark Registers

12. Line Interface Functions

13. Timing Diagrams and Transmit Flow Diagram

14. DC and AC Characteristics

1.0 INTRODUCTION

The analog AMI waveform off of the T1 line is trans­former coupled into the RRING and RTIP pins of the
DS2151Q. The device recovers clock and data from the
analog signal and passes it through the jitter attenuation
mux to the receive side framer where the digital serial
stream is analyzed to locate the framing pattern. If
needed, the receive side elastic store can be enabled in
order to absorb the phase and frequency differences
between the recovered T1 data stream and an asynch­ronous backplane clock which is provided at the
SYSCLK input.

The transmit side of the DS2151Q is totally independent
from the receive side in both the clock requirements and
characteristics. Data can be either provided directly to
the transmit formatter or via an elastic store. The trans­mit formatter will provide the necessary data overhead
for T1 transmission. Once the data stream has been
prepared for transmission, it is sent via the jitter attenua­tion mux to the waveshaping and line driver functions.
The DS2151Q will drive the T1 line from the TTIP and
TRING pins via a coupling transformer.

022697 2/46

DS2151Q BLOCK DIAGRAM Figure 1–1

RLINK

RLCLK

RCHBLK

RCLK

RCHCLK

FDL

EXTRACTION

SIGNALING EXTRACTION

ONE’S DENSITY MONITOR

CRC/FRAME ERROR COUNT

FRAMER

RECEIVE SIDE

LOOP CODE DETECTOR

RLOS

RSER

SYSCLK

TIMING

CONTROL

CHANNEL MARKING

ALARM DETECTION

SYNCHRONIZER

BPV COUNTER

B8ZS DECODER

STORE

ELASTIC

RSYNC

PAYLOAD LOOPBACK

STORE

ELASTIC

IDLE CODE INSERTION
SIGNALING INSERTION

CLEAR CHANNEL

LOOP CODE GEN.

ONE’S DENSITY ENCODER

F–BIT INSERTION

CRC GEN.

FDL INSERTION

YELLOW ALARM GEN.

TRANSMIT SIDE FORMATTER

B8ZS ENCODE

AIS GEN.

TSER

DETECT

LOSS OF TCLK

MUX

TCLK

TCHBLK

TIMING

TSYNC

TCHCLK

CONTROL

TLINK

FDL

INSERT

DS2151Q

TLCLK

LOGIC

ACLKI XTAL1 XTAL2

XTAL/VCO/PLL

24.7 MHz

FRAMER LOOPBACK

REMOTE LOOKPACK

JITTER ATTENUA TION MUX

(CAN BE PLACED IN EITHER THE TRANSMIT

RRING

DATA

CLOCK/

RECOVERY

PEAK

DETECT

FILTER

RTIP

OR RECEIVE PATHS)

LOCAL LOOPBACK

TRING

WAVE

SHAPING

CSU

FILTERS

LINE

DRIVERS

TTIP

(ROUTED TO ALL BLOCKS)

PARALLEL CONTROL PORT

BTS CS WR(R/W) RD(DS) ALE(AS) AD0–AD7 INT1/INT2

022697 3/46

DS2151Q

PIN DESCRIPTION Table 1–1

PIN SYMBOL TYPE DESCRIPTION

1
2
3
4

5 RD(DS) I Read Input (Data Strobe).
6 CS I Chip Select. Must be low to read or write the port.
7 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to

8 WR(R/W) I Write Input (Read/Write).
9 RLINK O Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or

10 RLCLK O Receive Link Clock. 4 KHz or 2 KHz (ZBTSI) demand clock for the RLINK

11 DVSS – Digital Signal Ground. 0.0 volts. Should be tied to local ground plane.
12 RCLK O Receive Clock. Recovered 1.544 MHz clock.
13 RCHCLK O Receive Channel Clock. 192 KHz clock which pulses high during the LSB

14 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges

15 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which

16 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.

17 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic

18 RCHBLK O Receive Channel Block. A user programmable output that can be forced

19 ACLKI I Alternate Clock Input. Upon a receive carrier loss, the clock applied at this

AD4
AD5
AD6
AD7

I/O Address/Data Bus. An 8–bit multiplexed address/data bus.

demultiplex the bus.

Z bits (ZBTSI) one RCLK before the start of a frame. See Section 13 for tim­ing details.

output. See Section 13 for timing details.

of each channel. Useful for parallel to serial conversion of channel data,
locating Robbed–Bit signaling bits, and for blocking clocks in DDS applica­tions. See Section 13 for timing details.

of RCLK or SYSCLK.

identifies either frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If
set to output frame boundaries, then via RCR2.5, RSYNC can also be set to
output double–wide pulses on signaling frames. If the elastic store is enabled
via the CCR1.2, then this pin can be enabled to be an input via RCR2.3 at
which a frame boundary pulse is applied. See Section 13 for timing details.

If CCR3.5=0, will toggle high when the synchronizer is searching for the T1
frame and multiframe; if CCR3.5=1, will toggle high if the TCLK pin has not
toggled for 5us.

store functions are enabled via either CCR1.7 or CCR1.2. Should be tied low
in applications that do not use the elastic store. If tied high for more than
100us, will force all output pins (including the parallel port) to 3–state.

high or low during any of the 24 T1 channels. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1 channels
are used such as Fractional T1, 384K bps service, 768K bps, or ISDN–PRI.
Also useful for locating individual channels in drop–and–insert applications.
See Section 13 for timing details.

pin (normally 1.544 MHz) will be routed to the RCLK pin. If no clock is routed
to this pin, then it should be tied to DVSS.

022697 4/46

DS2151Q

PIN DESCRIPTIONTYPESYMBOL

20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD
ALE(AS), and WR

(R/W) pins. If BTS=1, then these pins assume the function

(DS),

listed in parenthesis ().

21
22

RTIP

RRING

– Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects

to a 1:1 transformer (see Section 12 for details).

23 RVDD – Receive Analog Positive Supply . 5.0 volts. Should be tied to DVDD and

TVDD pins.
24 RVSS – Receive Signal Ground. 0.0 volts. Should be tied to local ground plane
25

26

XTAL1
XTAL2

– Crystal Connections. A pullable 6.176 MHz crystal must be applied to

these pins. See Section 12 for crystal specifications.
27 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions

defined in Status Register 1. Active low, open drain output.
28 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined

in Status Register 2. Active low, open drain output.
29 TTIP – Transmit Tip. Analog line driver output; connects to a step–up transformer

(see Section 12 for details).
30 TVSS – Transmit Signal Ground. 0.0 volts. Should be tied to local ground plane.
31 TVDD – Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD and

RVDD pins.
32 TRING – Transmit Ring. Analog line driver outputs; connects to a step–up trans-

former (see Section 12 for details).
33 TCHBLK O Transmit Channel Block. A user programmable output that can be forced

high or low during any of the 24 T1 channels. Useful for blocking clocks to

a serial UART or LAPD controller in applications where not all T1 channels

are used such as Fractional T1, 384K bps service, 768K bps, or ISDN–PRI.

Also useful for locating individual channels in drop–and–insert applications.

See Section 13 for timing details.
34 TLCLK O T ransmit Link Clock. 4 KHz or 2 KHz (ZBTSI) demand clock for the TLINK

input. See Section 13 for timing details.
35 TLINK I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during

the F–bit time on the falling edge of TCLK for data insertion into either the FDL

stream (ESF) or the Fs bit position (D4) or the Z–bit position (ZBTSI). See

Section 13 for timing details.
36 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe

boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be pro-

grammed to output either a frame or multiframe pulse at this pin. If this pin

is set to output pulses at frame boundaries, it can also be set via TCR2.4 to

output double–wide pulses at signaling frames. See Section 13 for timing

details.
37 DVDD – Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD pins.
38 TCLK I Transmit Clock. 1.544 MHz primary clock.
39 TSER I Transmit Serial Data. T ransmit NRZ serial data, sampled on the falling edge

of TCLK.

022697 5/46

DS2151Q

PIN DESCRIPTIONTYPESYMBOL

40 TCHCLK O T ransmit Channel Clock. 192 KHz clock which pulses high during the LSB

of each channel. Useful for parallel to serial conversion of channel data,
locating Robbed–Bit signaling bits, and for blocking clocks in DDS applica­tions. See Section 13 for timing details.

41
42
43
44

AD0
AD1
AD2
AD3

I/O Address/Data Bus. A 8–bit multiplexed address/data bus.

DS2151Q REGISTER MAP

ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME

20 R/W Status Register 1. 30 R/W Common Control Register 3.
21 R/W Status Register 2. 31 R/W Receive Information Register 2.
22 R/W Receive Information Register 1. 32 R/W Transmit Channel Blocking Reg-

23 R Line code Violation Count Regis-

33 R/W Transmit Channel Blocking Reg-

ter 1.

24 R Line code Violation Count Regis-

34 R/W Transmit Channel Blocking Reg-

ter 2.

25 R Path Code Violation Count Reg-

35 R/W Transmit Control Register 1.

ister 1. (1)

26 R Path Code Violation Count Reg-

36 R/W Transmit Control Register 2.

ister 2.

27 R Multiframe Out of Sync Count

37 R/W Common Control Register 1.

Register 2.
28 R Receive FDL Register 38 R/W Common Control Register 2.
29 R/W Receive FDL Match Register 1. 39 R/W Transmit Transparency Register

2A R/W Receive FDL Match Register 2. 3A R/W Transmit Transparency Register

2B R/W Receive Control Register 1. 3B R/W Transmit Transparency Register

2C R/W Receive Control Register 2. 3C R/W T ransmit Idle Register 1.
2D R/W Receive Mark Register 1. 3D R/W Transmit Idle Register 2.
2E R/W Receive Mark Register 2. 3E R/W Transmit Idle Register 3.
2F R/W Receive Mark Register 3. 3F R/W Transmit Idle Definition Register.

ister 1.

ister 2.

ister 3.

1.

2.

3.

60 R Receive Signaling Register 1. 70 R/W Transmit Signaling Register 1.
61 R Receive Signaling Register 2. 71 R/W Transmit Signaling Register 2.
62 R Receive Signaling Register 3. 72 R/W Transmit Signaling Register 3.

022697 6/46

DS2151Q

63 R Receive Signaling Register 4. 73 R/W Transmit Signaling Register 4.
64 R Receive Signaling Register 5. 74 R/W Transmit Signaling Register 5.
65 R Receive Signaling Register 6. 75 R/W Transmit Signaling Register 6.
66 R Receive Signaling Register 7. 76 R/W Transmit Signaling Register 7.
67 R Receive Signaling Register 8. 77 R/W Transmit Signaling Register 8.
68 R Receive Signaling Register 9. 78 R/W Transmit Signaling Register 9.
69 R Receive Signaling Register 10. 79 R/W Transmit Signaling Register 10.
6A R Receive Signaling Register 11. 7A R/W Transmit Signaling Register 11.
6B R Receive Signaling Register 12. 7B R/W Transmit Signaling Register 12.

6C R/W Receive Channel Blocking Reg-

7C R/W Line Interface Control Register.

ister 1.

6D R/W Receive Channel Blocking Reg-

7D R/W Test Register. (2)

ister 2.

6E R/W Receive Channel Blocking Reg-

7E R/W Transmit FDL Register.

ister 3.

6F R/W Interrupt Mask Register 2. 7F R/W Interrupt Mask Register 1.

NOTES:

1. Address 25 also contains Multiframe Out of Sync Count Register 1.

2. The T est Register is used only by the factory; this register must be cleared (set to all zeros) on power–up initializa­tion to insure proper operation.

2.0 PARALLEL PORT

The DS2151Q is controlled via a multiplexed bidirec­tional address/data bus by an external microcontroller
or microprocessor. The DS2151Q can operate with
either Intel or Motorola bus timing configurations. If the
BTS pin is tied low, Intel timing will be selected; if tied
high, Motorola timing will be selected. All Motorola bus
signals are listed in parenthesis (). See the timing dia­grams in the A.C. Electrical Characteristics for more
details. The multiplexed bus on the DS2151Q saves
pins because the address information and data informa­tion share the same signal paths. The addresses are
presented to the pins in the first portion of the bus cycle
and data will be transferred on the pins during second
portion of the bus cycle. Addresses must be valid prior
to the falling edge of ALE(AS), at which time the
DS2151Q latches the address from the AD0 to AD7
pins. Valid write data must be present and held stable
during the later portion of the DS or WR
cycle, the DS2151Q outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is

pulses. In a read

terminated and the bus returns to a high impedance
state as RD

transitions high in Intel timing or as DS tran­sitions low in Motorola timing. The DS2151Q can also
be easily connected to non–multiplexed buses. Please
see the separate Application Note for a detailed discus­sion of this topic.

3.0 CONTROL REGISTERS

The operation of the DS2151Q is configured via a set of
eight registers. Typically, the control registers are only
accessed when the system is first powered up. Once
the DS2151Q has been initialized, the control registers
will only need to be accessed when there is a change in
the system configuration. There are two Receive Con­trol Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), a Line Interface Control
Register (LICR), and three Common Control Registers
(CCR1, CCR2, and CCR3). Seven of the eight registers
are described below. The LICR is described in
Section 12.

022697 7/46

DS2151Q

RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)

(MSB) (LSB)

LCVCRF ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

LCVCRF RCR1.7 Line Code Violation Count Register Function Select.

ARC RCR1.6 Auto Resync Criteria.

OOF1 RCR1.5 Out Of Frame Select 1.

OOF2 RCR1.4 Out Of Frame Select 2.

SYNCC RCR1.3 Sync Criteria.

SYNCT RCR1.2 Sync Time.

SYNCE RCR1.1 Sync Enable.

RESYNC RCR1.0 Resync. When toggled from low to high, a resynchronization of the receive

0=do not count excessive zeros
1=count excessive zeros

0=Resync on OOF or RCL event
1=Resync on OOF only

0=2/4 frame bits in error
1=2/5 frame bits in error

0=follow RCR1.5
1=2/6 frame bits in error

In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern
1=cross couple Ft and Fs pattern
In ESF Framing Mode
0=search for FPS pattern only
1=search for FPS and verify with CRC6

0=qualify 10 bits
1=qualify 24 bits

0=auto resync enabled
1=auto resync disabled

side framer is initiated. Must be cleared and set again for a subsequent
resync.

RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)

(MSB) (LSB)

RCS RZBTSI RSDW RSM RSIO RD4YM FSBE MOSCRF

SYMBOL POSITION NAME AND DESCRIPTION

RCS RCR2.7 Receive Code Select.

RZBTSI RCR2.6 Receive Side ZBTSI Enable.

022697 8/46

0=idle code (7F Hex)
1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)

0=ZBTSI disabled
1=ZBTSI enabled

DS2151Q

RSDW RCR2.5 RSYNC Double–Wide.

0=do not pulse double–wide in signaling frames
1=do pulse double–wide in signaling frames (note: this bit must be set to
zero when RCR2.4=1 or when RCR2.3=1)

RSM RCR2.4 RSYNC Mode Select.

0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)

RSIO RCR2.3 RSYNC I/O Select.

0=RSYNC is an output
1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must
be set to zero when CCR1.2=0)

RD4YM RCR2.2 Receive Side D4 Yellow Alarm Select.

0=zeros in bit 2 of all channels
1=a one in the S–bit position of frame 12

FSBE RCR2.1 PCVCR Fs Bit Error Report Enable.

0=do not report bit errors in Fs bit position; only Ft bit position
1=report bit errors in Fs bit position as well as Ft bit position

MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select.

0=count errors in the framing bit position
1=count the number of multiframes out of sync

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)

(MSB) (LSB)

LOTCMC TFPT TCPT RBSE GB7S TLINK TBL TYEL

SYMBOL POSITION NAME AND DESCRIPTION

LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control. Determines whether the transmit

side formatter should switch to the ever present RCLK if the TCLK input
should fail to transition (see Figure 1–1 for more details).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops

TFPT TCR1.6 Transmit Framing Pass Through. (see note below)

0=Ft or FPS bits sourced internally
1=Ft or FPS bits sampled at TSER during F–bit time

TCPT TCR1.5 Transmit CRC Pass Through. (see note below)

0=source CRC6 bits internally
1=CRC6 bits sampled at TSER during F–bit time

RBSE TCR1.4 Robbed–Bit Signaling Enable. (see note below)

0=no signaling is inserted in any channel
1=signaling is inserted in all channels (the TTR registers can be used to
block insertion on a channel by channel basis)

GB7S TCR1.3 Global Bit 7 Stuffing. (see note below)

0=allow the TTR registers to determine which channels containing all zeros
are to be Bit 7 stuffed
1=force Bit 7 stuffing in all zero byte channels regardless of how the TTR
registers are programmed

022697 9/46

DS2151Q

TLINK TCR1.2 TLINK Select. (see note below)

0=source FDL or Fs bits from TFDL register
1=source FDL or Fs bits from the TLINK pin

TBL TCR1.1 Transmit Blue Alarm. (see note below)

0=transmit data normally
1=transmit an unframed all one’s code at TPOS and TNEG

TYEL TCR1.0 Transmit Yellow Alarm. (see note below)

0=do not transmit yellow alarm
1=transmit yellow alarm

Note: for a detailed description of how the bits in TCR1 affect the transmit side formatter of the DS2151Q, please see
Figure 13–9.

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)

(MSB) (LSB)

TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM B7ZS

SYMBOL POSITION NAME AND DESCRIPTION

TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3–1.
TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3–1.

TZBTSI TCR2.5 Transmit Side ZBTSI Enable.

TSDW TCR2.4 TSYNC Double–Wide. (note: this bit must be set to zero when TCR2.3=1

TSM TCR2.3 TSYNC Mode Select.

TSIO TCR2.2 TSYNC I/O Select.

TD4YM TCR2.1 Transmit Side D4 Yellow Alarm Select.

B7ZS TCR2.0 Bit 7 Zero Suppression Enable.

0=ZBTSI disabled
1=ZBTSI enabled

or when TCR2.2=0)
0=do not pulse double–wide in signaling frames
1=do pulse double–wide in signaling frames

0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)

0=TSYNC is an input
1=TSYNC is an output

0=zeros in bit 2 of all channels
1=a one in the S–bit position of frame 12

0=no stuffing occurs
1=Bit 7 force to a one in channels with all zeros

OUTPUT PIN TEST MODES Table 3–1

TEST1 TEST0 EFFECT ON OUTPUT PINS

0 0 operate normally
0 1 force all output pins 3–state (including all I/O pins and parallel port pins)
1 0 force all output pins low (including all I/O pins except parallel port pins)
1 1 force all output pins high (including all I/O pins except parallel port pins)

022697 10/46

CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)

(MSB) (LSB)

TESE LLB RSAO RLB SCLKM RESE PLB FLB

SYMBOL POSITION NAME AND DESCRIPTION

TESE CCR1.7 Transmit Elastic Store Enable.

LLB CCR1.6 Local Loopback.

RSAO CCR1.5 Receive Signaling All One’s.

RLB CCR1.4 Remote Loopback.

SCLKM CCR1.3 SYSCLK Mode Select.

RESE CCR1.2 Receive Elastic Store Enable.

PLB CCR1.1 Payload Loopback.

FLB CCR1.0 Framer Loopback.

LOCAL LOOPBACK

When CCR1.6 is set to a one, the DS2151Q will be
forced into Local LoopBack (LLB). In this loopback,
data will continue to be transmitted as normal through
the transmit side of the SCT. Data being received at
RTIP and RRING will be replaced with the data being
transmitted. Data in this loopback will pass through the
jitter attenuator and the jitter attenuator should be pro­grammed to be in the transmit path. LLB is primarily
used in debug and test applications. Please see the
DS2151Q Block Diagram in Section 1 for more details.

REMOTE LOOPBACK

When CCR1.4 is set to a one, the DS2151Q will be
forced into Remote LoopBack (RLB). In this loopback,
data recovered off the T1 line from the RTIP and RRING
pins will be transmitted back onto the T1 line (with any
BPVs that might have occurred intact) via the TTIP and

0=elastic store is bypassed
1=elastic store is enabled

0=loopback disabled
1=loopback enabled

0=allow robbed signaling bits to appear at RSER
1=force all robbed signaling bits at RSER to one

0=loopback disabled
1=loopback enabled

0=if SYSCLK is 1.544 MHz
1=if SYSCLK is 2.048 MHz

0=elastic store is bypassed
1=elastic store is enabled

0=loopback disabled
1=loopback enabled

0=loopback disabled
1=loopback enabled

TRING pins. Data will continue to pass through the
receive side of the DS2151Q as it would normally and
the data at the TSER input will be ignored. Data in this
loopback will pass through the jitter attenuator. RLB is
used to place the DS2151Q into “line” loopback which is
a requirement of both ANSI T1.403 and AT&T TR6241 1.
Please see the DS2151Q Block Diagram in Section 1 for
more details.

PAYLOAD LOOPBACK

When CCR1.1 is set to a one, the DS2151Q will be
forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being
performed. In a PLB situation, the DS2151Q will loop
the 192 bits of payload data (with BPVs corrected) from
the receive section back to the transmit section. The
FPS framing pattern, CRC6 calculation, and the FDL
bits are not looped back, they are reinserted by the

DS2151Q

022697 11/46

DS2151Q

DS2151Q. When PLB is enabled, the following will
occur:

in testing and debugging applications. In FLB, the
DS2151Q will loop data from the transmit side back to
the receive side. When FLB is enabled, the following

1. data will be transmitted from the TTIP and TRING

will occur:

pins synchronous with RCLK instead of TCLK

2. all of the receive side signals will continue to operate
normally

3. the TCHCLK and TCHBLK signals are forced low

4. data at the TSER pin is ignored

5. the TLCLK signal will become synchronous with
RCLK instead of TCLK.

1. unless the RLB is active, an unframed all one’s code
will be transmitted at TTIP and TRING

2. data off the T1 line at RTIP and RRING will be
ignored

3. the RCLK output will be replaced with the TCLK
input.

FRAMER LOOPBACK

When CCR1.0 is set to a one, the DS2151Q will enter a
Framer LoopBack (FLB) mode. This loopback is useful

CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)

(MSB) (LSB)

TFM

SYMBOL POSITION NAME AND DESCRIPTION

TFM CCR2.7 Transmit Frame Mode Select.

TB8ZS CCR2.6 Transmit B8ZS Enable.

TSLC96 CCR2.5 Transmit SLC–96/Fs Bit Insertion Enable.

TFDL CCR2.4 Transmit Zero Stuffer Enable.

RFM CCR2.3 Receive Frame Mode Select.

RB8ZS CCR2.2 Receive B8ZS Enable.

RSLC96 CCR2.1 Receive SLC–96 Enable.

RFDL CCR2.0 Receive Zero Destuffer Enable.

TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL

0=D4 framing mode
1=ESF framing mode

0=B8ZS disabled
1=B8ZS enabled

0=SLC–96 disabled
1=SLC–96 enabled

0=zero stuffer disabled
1=zero stuffer enabled

0=D4 framing mode
1=ESF framing mode

0=B8ZS disabled
1=B8ZS enabled

0=SLC–96 disabled
1=SLC–96 enabled

0=zero destuffer disabled
1=zero destuffer enabled

022697 12/46

CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)

(MSB) (LSB)

ESMDM ESR P16F RSMS PDE TLD TLU LIRST

SYMBOL POSITION NAME AND DESCRIPTION

ESMDM CCR3.7 Elastic Store Minimum Delay Mode. See Section 10.3 for details.

0=elastic stores operate at full two frame depth
1=elastic stores operate at 32–bit depth

ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elas-

tic stores to a known depth. Should be toggled after SYSCLK has been
applied and is stable. Must be cleared and set again for a subsequent
reset.

P16F CCR3.5 Function of Pin 16.

0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).

RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions

from D4 to ESF.
0=RSYNC will output a pulse at every multiframe
1=RSYNC will output a pulse at every other multiframe note: for this bit to
have any affect, the RSYNC must be set to output multiframe pulses
(RCR2.4=1 and RCR2.3=0).

PDE CCR3.3 Pulse Density Enforcer Enable.

0=disable transmit pulse density enforcer
1=enable transmit pulse density enforcer

TLD CCR3.2 Transmit Loop Down Code (001).

0=transmit data normally
1=replace normal transmitted data with loop down code

TLU CCR3.1 Transmit Loop Up Code (00001).

0=transmit data normally
1=replace normal transmitted data with loop up code

LIRST CCR3.0 Line Interface Reset. Setting this bit from a zero to a one will initiate an

internal reset that affects the slicer , AGC, clock recovery state machine and
jitter attenuator. Normally this bit is only toggled on power–up. Must be
cleared and set again for a subsequent reset.

DS2151Q

LOOP CODE GENERATION

When either the CCR3.1 or CCR3.2 bits are set to one,
the DS2151Q will replace the normal transmitted pay­load with either the Loop Up or Loop Down code respec­tively. The DS2151Q will overwrite the repeating loop
code pattern with the framing bits. The SCT will con­tinue to transmit the loop codes as long as either bit is
set. It is an illegal state to have both CCR3.1 and
CCR3.2 set to one at the same time.

PULSE DENSITY ENFORCER

The SCT always examines both the transmit and
receive data streams for violations of the following rules
which are required by ANSI T1.403–199X:

– no more than 15 consecutive zeros
– at least N ones in each and every time window

of 8 x (N +1) bits where N=1 through 23.

Violations for the transmit and receive data streams are
reported in the RIR2.2 and RIR2.1 bits respectively .

022697 13/46

DS2151Q

When the CCR3.3 is set to one, the DS2151Q will force
the transmitted stream to meet this requirement no mat­ter the content of the transmitted stream. When running
B8ZS, the CCR3.3 bit should be set to zero since B8ZS
encoded data streams cannot violate the pulse density
requirements.

POWER–UP SEQUENCE

On power–up, after the supplies are stable, the
DS2151Q should be configured for operation by writing
to all of the internal registers (this includes setting the
Test Register to 00Hex) since the contents of the inter­nal registers cannot be predicted on power–up. Next,
the LIRST bit should be toggled from zero to one to reset
the line interface (it will take the DS2151Q about 40ms
to recover from the LIRST being toggled). Finally, after
the SYSCLK input is stable, the ESR bit should be
toggled from a zero to a one (this step can be skipped if
the elastic stores are disabled).

4.0 STATUS AND INFORMATION
REGISTERS

There is a set of four registers that contain information
on the current real time status of the DS2151Q, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Register 1 (RIR1), and Receive Information
Register 2 (RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of
these four registers will be set to a one. All of the bits in
these registers operate in a latched fashion. This
means that if an event occurs and a bit is set to a one in
any of the registers, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will

not be set again until the event has occurred again or if
the alarm(s) is still present.

The user will always precede a read of these registers
with a write. The byte written to the register will inform
the DS2151Q which bits the user wishes to read and
have cleared. The user will write a byte to one of these
four registers, with a one in the bit positions he or she
wishes to read and a zero in the bit positions he or she
does not wish to obtain the latest information on. When
a one is written to a bit location, the read register will be
updated with current value and the previous value will
be cleared. When a zero is written to a bit position, the
read register will not be updated and the previous value
will be held. A write to the status and information regis­ters will be immediately followed by a read of the same
register. The read result should be logically AND’ed
with the mask byte that was just written and this value
should be written back into the same register to insure
that the bit does indeed clear . This second write is nec­essary because the alarms and events in the status reg­isters occur asynchronously in respect to their access
via the parallel port. The write–read–write scheme is
unique to the four status registers and it allows an exter­nal microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the regis­ter. This operation is key in controlling the DS2151Q
with higher–order software languages.

The SR1 and SR2 registers have the unique ability to
initiate a hardware interrupt via the INT1
respectively. Each of the alarms and events in the SR1
and SR2 can be either masked or unmasked from the
interrupt pins via the Interrupt Mask Register 1 (IMR1)
and Interrupt Mask Register 2 (IMR2) respectively.

and INT2 pins

RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)

(MSB) (LSB)

COFA 8ZD 16ZD RESF RESE SEFE B8ZS FBE

SYMBOL POSITION NAME AND DESCRIPTION

COFA RIR1.7 Change of Frame Alignment. Set when the last resync resulted in a

8ZD RIR1.6 Eight Zero Detect. Set when a string of eight consecutive zeros have been

16ZD RIR1.5 Sixteen Zero Detect. Set when a string of sixteen consecutive zeros have

RESF RIR1.4 Receive Elastic Store Full. Set when the receive elastic store buffer fills

022697 14/46

change of frame or multiframe alignment.

received at RPOS and RNEG.

been received at RPOS and RNEG.

and a frame is deleted.