Rainbow Electronics DS2151Q User Manual

DS2151Q

DS2151Q

T1 Single–Chip Transceiver

FEATURES

• Complete DS1/ISDN–PRI transceiver functionality

• Line interface can handle both long and short haul

trunks

• 32–bit or 128–bit jitter attenuator

• Generates DSX–1 and CSU line build outs

• Frames to D4, ESF, and SLC–96

R

formats

• Dual onboard two–frame elastic store slip buffers that

connect to backplanes up to 8.192 MHz

• 8–bit parallel control port that can be used on either

multiplexed or non–multiplexed buses

• Extracts and inserts Robbed–Bit signaling

• Detects and generates yellow and blue alarms

• Programmable output clocks for Fractional T1

• Fully independent transmit and receive functionality

• Onboard FDL support circuitry

• Generates and detects CSU loop codes

• Contains ANSI one’s density monitor and enforcer

• Large path and line error counters including BPV , CV ,

CRC6, and framing bit errors

• Pin compatible with DS2153Q E1 Single–Chip Trans-

ceiver

• 5V supply; low power CMOS

• Industrial grade version (–40°C to +85°C) available

(DS2151QN)

DESCRIPTION

The DS2151Q T1 Single–Chip Transceiver (SCT) con­tains all of the necessary functions for connection to T1
lines whether they be DS–1 long haul or DSX–1 short
haul. The clock recovery circuitry automatically adjusts

PIN ASSIGNMENT

Functional Blocks

FRAMER

ELASTIC STORES

LINE INTERFACE

LONG & SHORT HAUL

PARALLEL CONTROL

PORT

DALLAS

DS2151Q

T1 SCT

ALE

WR

RLINK

RLCLK

DVSS
RCLK

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

to T1 lines from 0 feet to over 6000 feet in length. The
device can generate both DSX–1 line build outs as well
as CSU build outs of –7.5 dB, –15 dB, and –22.5 dB.
The onboard jitter attenuator (selectable to either 32 bits

Actual Size of

44–pin PLCC

CSRDAD7

AD6

AD5

AD4

AD3

AD2

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

ACLKI

RCHBLK

BTS

RTIP

1

RVDD

RRING

4443424140

RVSS

XTAL1

AD1

XTAL2

AD0

39
38
37
36
35
34
33
32
31
30
29

INT1

TCHCLK

TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP

INT2

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

022697 1/46

DS2151Q

or 128 bits) can be placed in either the transmit or
receive data paths. The framer locates the frame and
multiframe boundaries and monitors the data stream for
alarms. It is also used for extracting and inserting
Robbed–Bit signaling data and FDL data. The device
contains a set of 64 eight bit internal registers which the
user can access and control the operation of the unit.
Quick access via the parallel control port allows a single
micro to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI
T1.403–199X, A T&T TR 62411 (12–90), and ITU G.703,
G.704, G.706, G.823, and I.431.

TABLE OF CONTENTS

1. Introduction

2. Parallel Control Port

3. Control Registers

4. Status and Information Registers

5. Error Count Registers

6. FDL/Fs Extraction/Insertion

7. Signaling Operation

8. Transmit Transparency and Idle Registers

9. Clock Blocking Registers

10. Elastic Stores Operation

11. Receive Mark Registers

12. Line Interface Functions

13. Timing Diagrams and Transmit Flow Diagram

14. DC and AC Characteristics

1.0 INTRODUCTION

The analog AMI waveform off of the T1 line is trans­former coupled into the RRING and RTIP pins of the
DS2151Q. The device recovers clock and data from the
analog signal and passes it through the jitter attenuation
mux to the receive side framer where the digital serial
stream is analyzed to locate the framing pattern. If
needed, the receive side elastic store can be enabled in
order to absorb the phase and frequency differences
between the recovered T1 data stream and an asynch­ronous backplane clock which is provided at the
SYSCLK input.

The transmit side of the DS2151Q is totally independent
from the receive side in both the clock requirements and
characteristics. Data can be either provided directly to
the transmit formatter or via an elastic store. The trans­mit formatter will provide the necessary data overhead
for T1 transmission. Once the data stream has been
prepared for transmission, it is sent via the jitter attenua­tion mux to the waveshaping and line driver functions.
The DS2151Q will drive the T1 line from the TTIP and
TRING pins via a coupling transformer.

022697 2/46

DS2151Q BLOCK DIAGRAM Figure 1–1

RLINK

RLCLK

RCHBLK

RCLK

RCHCLK

FDL

EXTRACTION

SIGNALING EXTRACTION

ONE’S DENSITY MONITOR

CRC/FRAME ERROR COUNT

FRAMER

RECEIVE SIDE

LOOP CODE DETECTOR

RLOS

RSER

SYSCLK

TIMING

CONTROL

CHANNEL MARKING

ALARM DETECTION

SYNCHRONIZER

BPV COUNTER

B8ZS DECODER

STORE

ELASTIC

RSYNC

PAYLOAD LOOPBACK

STORE

ELASTIC

IDLE CODE INSERTION
SIGNALING INSERTION

CLEAR CHANNEL

LOOP CODE GEN.

ONE’S DENSITY ENCODER

F–BIT INSERTION

CRC GEN.

FDL INSERTION

YELLOW ALARM GEN.

TRANSMIT SIDE FORMATTER

B8ZS ENCODE

AIS GEN.

TSER

DETECT

LOSS OF TCLK

MUX

TCLK

TCHBLK

TIMING

TSYNC

TCHCLK

CONTROL

TLINK

FDL

INSERT

DS2151Q

TLCLK

LOGIC

ACLKI XTAL1 XTAL2

XTAL/VCO/PLL

24.7 MHz

FRAMER LOOPBACK

REMOTE LOOKPACK

JITTER ATTENUA TION MUX

(CAN BE PLACED IN EITHER THE TRANSMIT

RRING

DATA

CLOCK/

RECOVERY

PEAK

DETECT

FILTER

RTIP

OR RECEIVE PATHS)

LOCAL LOOPBACK

TRING

WAVE

SHAPING

CSU

FILTERS

LINE

DRIVERS

TTIP

(ROUTED TO ALL BLOCKS)

PARALLEL CONTROL PORT

BTS CS WR(R/W) RD(DS) ALE(AS) AD0–AD7 INT1/INT2

022697 3/46

DS2151Q

PIN DESCRIPTION Table 1–1

PIN SYMBOL TYPE DESCRIPTION

1
2
3
4

5 RD(DS) I Read Input (Data Strobe).
6 CS I Chip Select. Must be low to read or write the port.
7 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to

8 WR(R/W) I Write Input (Read/Write).
9 RLINK O Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or

10 RLCLK O Receive Link Clock. 4 KHz or 2 KHz (ZBTSI) demand clock for the RLINK

11 DVSS – Digital Signal Ground. 0.0 volts. Should be tied to local ground plane.
12 RCLK O Receive Clock. Recovered 1.544 MHz clock.
13 RCHCLK O Receive Channel Clock. 192 KHz clock which pulses high during the LSB

14 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges

15 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which

16 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.

17 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic

18 RCHBLK O Receive Channel Block. A user programmable output that can be forced

19 ACLKI I Alternate Clock Input. Upon a receive carrier loss, the clock applied at this

AD4
AD5
AD6
AD7

I/O Address/Data Bus. An 8–bit multiplexed address/data bus.

demultiplex the bus.

Z bits (ZBTSI) one RCLK before the start of a frame. See Section 13 for tim­ing details.

output. See Section 13 for timing details.

of each channel. Useful for parallel to serial conversion of channel data,
locating Robbed–Bit signaling bits, and for blocking clocks in DDS applica­tions. See Section 13 for timing details.

of RCLK or SYSCLK.

identifies either frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If
set to output frame boundaries, then via RCR2.5, RSYNC can also be set to
output double–wide pulses on signaling frames. If the elastic store is enabled
via the CCR1.2, then this pin can be enabled to be an input via RCR2.3 at
which a frame boundary pulse is applied. See Section 13 for timing details.

If CCR3.5=0, will toggle high when the synchronizer is searching for the T1
frame and multiframe; if CCR3.5=1, will toggle high if the TCLK pin has not
toggled for 5us.

store functions are enabled via either CCR1.7 or CCR1.2. Should be tied low
in applications that do not use the elastic store. If tied high for more than
100us, will force all output pins (including the parallel port) to 3–state.

high or low during any of the 24 T1 channels. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1 channels
are used such as Fractional T1, 384K bps service, 768K bps, or ISDN–PRI.
Also useful for locating individual channels in drop–and–insert applications.
See Section 13 for timing details.

pin (normally 1.544 MHz) will be routed to the RCLK pin. If no clock is routed
to this pin, then it should be tied to DVSS.

022697 4/46

DS2151Q

PIN DESCRIPTIONTYPESYMBOL

20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD
ALE(AS), and WR

(R/W) pins. If BTS=1, then these pins assume the function

(DS),

listed in parenthesis ().

21
22

RTIP

RRING

– Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects

to a 1:1 transformer (see Section 12 for details).

23 RVDD – Receive Analog Positive Supply . 5.0 volts. Should be tied to DVDD and

TVDD pins.
24 RVSS – Receive Signal Ground. 0.0 volts. Should be tied to local ground plane
25

26

XTAL1
XTAL2

– Crystal Connections. A pullable 6.176 MHz crystal must be applied to

these pins. See Section 12 for crystal specifications.
27 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions

defined in Status Register 1. Active low, open drain output.
28 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined

in Status Register 2. Active low, open drain output.
29 TTIP – Transmit Tip. Analog line driver output; connects to a step–up transformer

(see Section 12 for details).
30 TVSS – Transmit Signal Ground. 0.0 volts. Should be tied to local ground plane.
31 TVDD – Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD and

RVDD pins.
32 TRING – Transmit Ring. Analog line driver outputs; connects to a step–up trans-

former (see Section 12 for details).
33 TCHBLK O Transmit Channel Block. A user programmable output that can be forced

high or low during any of the 24 T1 channels. Useful for blocking clocks to

a serial UART or LAPD controller in applications where not all T1 channels

are used such as Fractional T1, 384K bps service, 768K bps, or ISDN–PRI.

Also useful for locating individual channels in drop–and–insert applications.

See Section 13 for timing details.
34 TLCLK O T ransmit Link Clock. 4 KHz or 2 KHz (ZBTSI) demand clock for the TLINK

input. See Section 13 for timing details.
35 TLINK I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during

the F–bit time on the falling edge of TCLK for data insertion into either the FDL

stream (ESF) or the Fs bit position (D4) or the Z–bit position (ZBTSI). See

Section 13 for timing details.
36 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe

boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be pro-

grammed to output either a frame or multiframe pulse at this pin. If this pin

is set to output pulses at frame boundaries, it can also be set via TCR2.4 to

output double–wide pulses at signaling frames. See Section 13 for timing

details.
37 DVDD – Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD pins.
38 TCLK I Transmit Clock. 1.544 MHz primary clock.
39 TSER I Transmit Serial Data. T ransmit NRZ serial data, sampled on the falling edge

of TCLK.

022697 5/46

DS2151Q

PIN DESCRIPTIONTYPESYMBOL

40 TCHCLK O T ransmit Channel Clock. 192 KHz clock which pulses high during the LSB

of each channel. Useful for parallel to serial conversion of channel data,
locating Robbed–Bit signaling bits, and for blocking clocks in DDS applica­tions. See Section 13 for timing details.

41
42
43
44

AD0
AD1
AD2
AD3

I/O Address/Data Bus. A 8–bit multiplexed address/data bus.

DS2151Q REGISTER MAP

ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME

20 R/W Status Register 1. 30 R/W Common Control Register 3.
21 R/W Status Register 2. 31 R/W Receive Information Register 2.
22 R/W Receive Information Register 1. 32 R/W Transmit Channel Blocking Reg-

23 R Line code Violation Count Regis-

33 R/W Transmit Channel Blocking Reg-

ter 1.

24 R Line code Violation Count Regis-

34 R/W Transmit Channel Blocking Reg-

ter 2.

25 R Path Code Violation Count Reg-

35 R/W Transmit Control Register 1.

ister 1. (1)

26 R Path Code Violation Count Reg-

36 R/W Transmit Control Register 2.

ister 2.

27 R Multiframe Out of Sync Count

37 R/W Common Control Register 1.

Register 2.
28 R Receive FDL Register 38 R/W Common Control Register 2.
29 R/W Receive FDL Match Register 1. 39 R/W Transmit Transparency Register

2A R/W Receive FDL Match Register 2. 3A R/W Transmit Transparency Register

2B R/W Receive Control Register 1. 3B R/W Transmit Transparency Register

2C R/W Receive Control Register 2. 3C R/W T ransmit Idle Register 1.
2D R/W Receive Mark Register 1. 3D R/W Transmit Idle Register 2.
2E R/W Receive Mark Register 2. 3E R/W Transmit Idle Register 3.
2F R/W Receive Mark Register 3. 3F R/W Transmit Idle Definition Register.

ister 1.

ister 2.

ister 3.

1.

2.

3.

60 R Receive Signaling Register 1. 70 R/W Transmit Signaling Register 1.
61 R Receive Signaling Register 2. 71 R/W Transmit Signaling Register 2.
62 R Receive Signaling Register 3. 72 R/W Transmit Signaling Register 3.

022697 6/46

DS2151Q

63 R Receive Signaling Register 4. 73 R/W Transmit Signaling Register 4.
64 R Receive Signaling Register 5. 74 R/W Transmit Signaling Register 5.
65 R Receive Signaling Register 6. 75 R/W Transmit Signaling Register 6.
66 R Receive Signaling Register 7. 76 R/W Transmit Signaling Register 7.
67 R Receive Signaling Register 8. 77 R/W Transmit Signaling Register 8.
68 R Receive Signaling Register 9. 78 R/W Transmit Signaling Register 9.
69 R Receive Signaling Register 10. 79 R/W Transmit Signaling Register 10.
6A R Receive Signaling Register 11. 7A R/W Transmit Signaling Register 11.
6B R Receive Signaling Register 12. 7B R/W Transmit Signaling Register 12.

6C R/W Receive Channel Blocking Reg-

7C R/W Line Interface Control Register.

ister 1.

6D R/W Receive Channel Blocking Reg-

7D R/W Test Register. (2)

ister 2.

6E R/W Receive Channel Blocking Reg-

7E R/W Transmit FDL Register.

ister 3.

6F R/W Interrupt Mask Register 2. 7F R/W Interrupt Mask Register 1.

NOTES:

1. Address 25 also contains Multiframe Out of Sync Count Register 1.

2. The T est Register is used only by the factory; this register must be cleared (set to all zeros) on power–up initializa­tion to insure proper operation.

2.0 PARALLEL PORT

The DS2151Q is controlled via a multiplexed bidirec­tional address/data bus by an external microcontroller
or microprocessor. The DS2151Q can operate with
either Intel or Motorola bus timing configurations. If the
BTS pin is tied low, Intel timing will be selected; if tied
high, Motorola timing will be selected. All Motorola bus
signals are listed in parenthesis (). See the timing dia­grams in the A.C. Electrical Characteristics for more
details. The multiplexed bus on the DS2151Q saves
pins because the address information and data informa­tion share the same signal paths. The addresses are
presented to the pins in the first portion of the bus cycle
and data will be transferred on the pins during second
portion of the bus cycle. Addresses must be valid prior
to the falling edge of ALE(AS), at which time the
DS2151Q latches the address from the AD0 to AD7
pins. Valid write data must be present and held stable
during the later portion of the DS or WR
cycle, the DS2151Q outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is

pulses. In a read

terminated and the bus returns to a high impedance
state as RD

transitions high in Intel timing or as DS tran­sitions low in Motorola timing. The DS2151Q can also
be easily connected to non–multiplexed buses. Please
see the separate Application Note for a detailed discus­sion of this topic.

3.0 CONTROL REGISTERS

The operation of the DS2151Q is configured via a set of
eight registers. Typically, the control registers are only
accessed when the system is first powered up. Once
the DS2151Q has been initialized, the control registers
will only need to be accessed when there is a change in
the system configuration. There are two Receive Con­trol Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), a Line Interface Control
Register (LICR), and three Common Control Registers
(CCR1, CCR2, and CCR3). Seven of the eight registers
are described below. The LICR is described in
Section 12.

022697 7/46

DS2151Q

RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)

(MSB) (LSB)

LCVCRF ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

LCVCRF RCR1.7 Line Code Violation Count Register Function Select.

ARC RCR1.6 Auto Resync Criteria.

OOF1 RCR1.5 Out Of Frame Select 1.

OOF2 RCR1.4 Out Of Frame Select 2.

SYNCC RCR1.3 Sync Criteria.

SYNCT RCR1.2 Sync Time.

SYNCE RCR1.1 Sync Enable.

RESYNC RCR1.0 Resync. When toggled from low to high, a resynchronization of the receive

0=do not count excessive zeros
1=count excessive zeros

0=Resync on OOF or RCL event
1=Resync on OOF only

0=2/4 frame bits in error
1=2/5 frame bits in error

0=follow RCR1.5
1=2/6 frame bits in error

In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern
1=cross couple Ft and Fs pattern
In ESF Framing Mode
0=search for FPS pattern only
1=search for FPS and verify with CRC6

0=qualify 10 bits
1=qualify 24 bits

0=auto resync enabled
1=auto resync disabled

side framer is initiated. Must be cleared and set again for a subsequent
resync.

RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)

(MSB) (LSB)

RCS RZBTSI RSDW RSM RSIO RD4YM FSBE MOSCRF

SYMBOL POSITION NAME AND DESCRIPTION

RCS RCR2.7 Receive Code Select.

RZBTSI RCR2.6 Receive Side ZBTSI Enable.

022697 8/46

0=idle code (7F Hex)
1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)

0=ZBTSI disabled
1=ZBTSI enabled

DS2151Q

RSDW RCR2.5 RSYNC Double–Wide.

0=do not pulse double–wide in signaling frames
1=do pulse double–wide in signaling frames (note: this bit must be set to
zero when RCR2.4=1 or when RCR2.3=1)

RSM RCR2.4 RSYNC Mode Select.

0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)

RSIO RCR2.3 RSYNC I/O Select.

0=RSYNC is an output
1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must
be set to zero when CCR1.2=0)

RD4YM RCR2.2 Receive Side D4 Yellow Alarm Select.

0=zeros in bit 2 of all channels
1=a one in the S–bit position of frame 12

FSBE RCR2.1 PCVCR Fs Bit Error Report Enable.

0=do not report bit errors in Fs bit position; only Ft bit position
1=report bit errors in Fs bit position as well as Ft bit position

MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select.

0=count errors in the framing bit position
1=count the number of multiframes out of sync

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)

(MSB) (LSB)

LOTCMC TFPT TCPT RBSE GB7S TLINK TBL TYEL

SYMBOL POSITION NAME AND DESCRIPTION

LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control. Determines whether the transmit

side formatter should switch to the ever present RCLK if the TCLK input
should fail to transition (see Figure 1–1 for more details).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops

TFPT TCR1.6 Transmit Framing Pass Through. (see note below)

0=Ft or FPS bits sourced internally
1=Ft or FPS bits sampled at TSER during F–bit time

TCPT TCR1.5 Transmit CRC Pass Through. (see note below)

0=source CRC6 bits internally
1=CRC6 bits sampled at TSER during F–bit time

RBSE TCR1.4 Robbed–Bit Signaling Enable. (see note below)

0=no signaling is inserted in any channel
1=signaling is inserted in all channels (the TTR registers can be used to
block insertion on a channel by channel basis)

GB7S TCR1.3 Global Bit 7 Stuffing. (see note below)

0=allow the TTR registers to determine which channels containing all zeros
are to be Bit 7 stuffed
1=force Bit 7 stuffing in all zero byte channels regardless of how the TTR
registers are programmed

022697 9/46

DS2151Q

TLINK TCR1.2 TLINK Select. (see note below)

0=source FDL or Fs bits from TFDL register
1=source FDL or Fs bits from the TLINK pin

TBL TCR1.1 Transmit Blue Alarm. (see note below)

0=transmit data normally
1=transmit an unframed all one’s code at TPOS and TNEG

TYEL TCR1.0 Transmit Yellow Alarm. (see note below)

0=do not transmit yellow alarm
1=transmit yellow alarm

Note: for a detailed description of how the bits in TCR1 affect the transmit side formatter of the DS2151Q, please see
Figure 13–9.

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)

(MSB) (LSB)

TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM B7ZS

SYMBOL POSITION NAME AND DESCRIPTION

TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3–1.
TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3–1.

TZBTSI TCR2.5 Transmit Side ZBTSI Enable.

TSDW TCR2.4 TSYNC Double–Wide. (note: this bit must be set to zero when TCR2.3=1

TSM TCR2.3 TSYNC Mode Select.

TSIO TCR2.2 TSYNC I/O Select.

TD4YM TCR2.1 Transmit Side D4 Yellow Alarm Select.

B7ZS TCR2.0 Bit 7 Zero Suppression Enable.

0=ZBTSI disabled
1=ZBTSI enabled

or when TCR2.2=0)
0=do not pulse double–wide in signaling frames
1=do pulse double–wide in signaling frames

0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)

0=TSYNC is an input
1=TSYNC is an output

0=zeros in bit 2 of all channels
1=a one in the S–bit position of frame 12

0=no stuffing occurs
1=Bit 7 force to a one in channels with all zeros

OUTPUT PIN TEST MODES Table 3–1

TEST1 TEST0 EFFECT ON OUTPUT PINS

0 0 operate normally
0 1 force all output pins 3–state (including all I/O pins and parallel port pins)
1 0 force all output pins low (including all I/O pins except parallel port pins)
1 1 force all output pins high (including all I/O pins except parallel port pins)

022697 10/46

CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)

(MSB) (LSB)

TESE LLB RSAO RLB SCLKM RESE PLB FLB

SYMBOL POSITION NAME AND DESCRIPTION

TESE CCR1.7 Transmit Elastic Store Enable.

LLB CCR1.6 Local Loopback.

RSAO CCR1.5 Receive Signaling All One’s.

RLB CCR1.4 Remote Loopback.

SCLKM CCR1.3 SYSCLK Mode Select.

RESE CCR1.2 Receive Elastic Store Enable.

PLB CCR1.1 Payload Loopback.

FLB CCR1.0 Framer Loopback.

LOCAL LOOPBACK

When CCR1.6 is set to a one, the DS2151Q will be
forced into Local LoopBack (LLB). In this loopback,
data will continue to be transmitted as normal through
the transmit side of the SCT. Data being received at
RTIP and RRING will be replaced with the data being
transmitted. Data in this loopback will pass through the
jitter attenuator and the jitter attenuator should be pro­grammed to be in the transmit path. LLB is primarily
used in debug and test applications. Please see the
DS2151Q Block Diagram in Section 1 for more details.

REMOTE LOOPBACK

When CCR1.4 is set to a one, the DS2151Q will be
forced into Remote LoopBack (RLB). In this loopback,
data recovered off the T1 line from the RTIP and RRING
pins will be transmitted back onto the T1 line (with any
BPVs that might have occurred intact) via the TTIP and

0=elastic store is bypassed
1=elastic store is enabled

0=loopback disabled
1=loopback enabled

0=allow robbed signaling bits to appear at RSER
1=force all robbed signaling bits at RSER to one

0=loopback disabled
1=loopback enabled

0=if SYSCLK is 1.544 MHz
1=if SYSCLK is 2.048 MHz

0=elastic store is bypassed
1=elastic store is enabled

0=loopback disabled
1=loopback enabled

0=loopback disabled
1=loopback enabled

TRING pins. Data will continue to pass through the
receive side of the DS2151Q as it would normally and
the data at the TSER input will be ignored. Data in this
loopback will pass through the jitter attenuator. RLB is
used to place the DS2151Q into “line” loopback which is
a requirement of both ANSI T1.403 and AT&T TR6241 1.
Please see the DS2151Q Block Diagram in Section 1 for
more details.

PAYLOAD LOOPBACK

When CCR1.1 is set to a one, the DS2151Q will be
forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being
performed. In a PLB situation, the DS2151Q will loop
the 192 bits of payload data (with BPVs corrected) from
the receive section back to the transmit section. The
FPS framing pattern, CRC6 calculation, and the FDL
bits are not looped back, they are reinserted by the

DS2151Q

022697 11/46

DS2151Q

DS2151Q. When PLB is enabled, the following will
occur:

in testing and debugging applications. In FLB, the
DS2151Q will loop data from the transmit side back to
the receive side. When FLB is enabled, the following

1. data will be transmitted from the TTIP and TRING

will occur:

pins synchronous with RCLK instead of TCLK

2. all of the receive side signals will continue to operate
normally

3. the TCHCLK and TCHBLK signals are forced low

4. data at the TSER pin is ignored

5. the TLCLK signal will become synchronous with
RCLK instead of TCLK.

1. unless the RLB is active, an unframed all one’s code
will be transmitted at TTIP and TRING

2. data off the T1 line at RTIP and RRING will be
ignored

3. the RCLK output will be replaced with the TCLK
input.

FRAMER LOOPBACK

When CCR1.0 is set to a one, the DS2151Q will enter a
Framer LoopBack (FLB) mode. This loopback is useful

CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)

(MSB) (LSB)

TFM

SYMBOL POSITION NAME AND DESCRIPTION

TFM CCR2.7 Transmit Frame Mode Select.

TB8ZS CCR2.6 Transmit B8ZS Enable.

TSLC96 CCR2.5 Transmit SLC–96/Fs Bit Insertion Enable.

TFDL CCR2.4 Transmit Zero Stuffer Enable.

RFM CCR2.3 Receive Frame Mode Select.

RB8ZS CCR2.2 Receive B8ZS Enable.

RSLC96 CCR2.1 Receive SLC–96 Enable.

RFDL CCR2.0 Receive Zero Destuffer Enable.

TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL

0=D4 framing mode
1=ESF framing mode

0=B8ZS disabled
1=B8ZS enabled

0=SLC–96 disabled
1=SLC–96 enabled

0=zero stuffer disabled
1=zero stuffer enabled

0=D4 framing mode
1=ESF framing mode

0=B8ZS disabled
1=B8ZS enabled

0=SLC–96 disabled
1=SLC–96 enabled

0=zero destuffer disabled
1=zero destuffer enabled

022697 12/46

CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)

(MSB) (LSB)

ESMDM ESR P16F RSMS PDE TLD TLU LIRST

SYMBOL POSITION NAME AND DESCRIPTION

ESMDM CCR3.7 Elastic Store Minimum Delay Mode. See Section 10.3 for details.

0=elastic stores operate at full two frame depth
1=elastic stores operate at 32–bit depth

ESR CCR3.6 Elastic Store Reset. Setting this bit from a zero to a one will force the elas-

tic stores to a known depth. Should be toggled after SYSCLK has been
applied and is stable. Must be cleared and set again for a subsequent
reset.

P16F CCR3.5 Function of Pin 16.

0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).

RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions

from D4 to ESF.
0=RSYNC will output a pulse at every multiframe
1=RSYNC will output a pulse at every other multiframe note: for this bit to
have any affect, the RSYNC must be set to output multiframe pulses
(RCR2.4=1 and RCR2.3=0).

PDE CCR3.3 Pulse Density Enforcer Enable.

0=disable transmit pulse density enforcer
1=enable transmit pulse density enforcer

TLD CCR3.2 Transmit Loop Down Code (001).

0=transmit data normally
1=replace normal transmitted data with loop down code

TLU CCR3.1 Transmit Loop Up Code (00001).

0=transmit data normally
1=replace normal transmitted data with loop up code

LIRST CCR3.0 Line Interface Reset. Setting this bit from a zero to a one will initiate an

internal reset that affects the slicer , AGC, clock recovery state machine and
jitter attenuator. Normally this bit is only toggled on power–up. Must be
cleared and set again for a subsequent reset.

DS2151Q

LOOP CODE GENERATION

When either the CCR3.1 or CCR3.2 bits are set to one,
the DS2151Q will replace the normal transmitted pay­load with either the Loop Up or Loop Down code respec­tively. The DS2151Q will overwrite the repeating loop
code pattern with the framing bits. The SCT will con­tinue to transmit the loop codes as long as either bit is
set. It is an illegal state to have both CCR3.1 and
CCR3.2 set to one at the same time.

PULSE DENSITY ENFORCER

The SCT always examines both the transmit and
receive data streams for violations of the following rules
which are required by ANSI T1.403–199X:

– no more than 15 consecutive zeros
– at least N ones in each and every time window

of 8 x (N +1) bits where N=1 through 23.

Violations for the transmit and receive data streams are
reported in the RIR2.2 and RIR2.1 bits respectively .

022697 13/46

DS2151Q

When the CCR3.3 is set to one, the DS2151Q will force
the transmitted stream to meet this requirement no mat­ter the content of the transmitted stream. When running
B8ZS, the CCR3.3 bit should be set to zero since B8ZS
encoded data streams cannot violate the pulse density
requirements.

POWER–UP SEQUENCE

On power–up, after the supplies are stable, the
DS2151Q should be configured for operation by writing
to all of the internal registers (this includes setting the
Test Register to 00Hex) since the contents of the inter­nal registers cannot be predicted on power–up. Next,
the LIRST bit should be toggled from zero to one to reset
the line interface (it will take the DS2151Q about 40ms
to recover from the LIRST being toggled). Finally, after
the SYSCLK input is stable, the ESR bit should be
toggled from a zero to a one (this step can be skipped if
the elastic stores are disabled).

4.0 STATUS AND INFORMATION
REGISTERS

There is a set of four registers that contain information
on the current real time status of the DS2151Q, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Register 1 (RIR1), and Receive Information
Register 2 (RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of
these four registers will be set to a one. All of the bits in
these registers operate in a latched fashion. This
means that if an event occurs and a bit is set to a one in
any of the registers, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will

not be set again until the event has occurred again or if
the alarm(s) is still present.

The user will always precede a read of these registers
with a write. The byte written to the register will inform
the DS2151Q which bits the user wishes to read and
have cleared. The user will write a byte to one of these
four registers, with a one in the bit positions he or she
wishes to read and a zero in the bit positions he or she
does not wish to obtain the latest information on. When
a one is written to a bit location, the read register will be
updated with current value and the previous value will
be cleared. When a zero is written to a bit position, the
read register will not be updated and the previous value
will be held. A write to the status and information regis­ters will be immediately followed by a read of the same
register. The read result should be logically AND’ed
with the mask byte that was just written and this value
should be written back into the same register to insure
that the bit does indeed clear . This second write is nec­essary because the alarms and events in the status reg­isters occur asynchronously in respect to their access
via the parallel port. The write–read–write scheme is
unique to the four status registers and it allows an exter­nal microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the regis­ter. This operation is key in controlling the DS2151Q
with higher–order software languages.

The SR1 and SR2 registers have the unique ability to
initiate a hardware interrupt via the INT1
respectively. Each of the alarms and events in the SR1
and SR2 can be either masked or unmasked from the
interrupt pins via the Interrupt Mask Register 1 (IMR1)
and Interrupt Mask Register 2 (IMR2) respectively.

and INT2 pins

RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)

(MSB) (LSB)

COFA 8ZD 16ZD RESF RESE SEFE B8ZS FBE

SYMBOL POSITION NAME AND DESCRIPTION

COFA RIR1.7 Change of Frame Alignment. Set when the last resync resulted in a

8ZD RIR1.6 Eight Zero Detect. Set when a string of eight consecutive zeros have been

16ZD RIR1.5 Sixteen Zero Detect. Set when a string of sixteen consecutive zeros have

RESF RIR1.4 Receive Elastic Store Full. Set when the receive elastic store buffer fills

022697 14/46

change of frame or multiframe alignment.

received at RPOS and RNEG.

been received at RPOS and RNEG.

and a frame is deleted.

DS2151Q

RESE RIR1.3 Receive Elastic Store Empty. Set when the receive elastic store buffer

empties and a frame is repeated.

SEFE RIR1.2 Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or

FPS) are received in error.

B8ZS RIR1.1 B8ZS Code Word Detect. Set when a B8ZS code word is detected at

RPOS and RNEG independent of whether the B8ZS mode is selected or
not via CCR2.6.

FBE RIR1.0 Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in

error.

RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)

(MSB) (LSB)

RL1 RL0 TESF TESE TSLIP JALT RPDV TPDV

SYMBOL POSITION NAME AND DESCRIPTION

RL1 RIR2.7 Receive Level Bit 1. See Table 4–1.
RL0 RIR2.6 Receive Level Bit 0. See Table 4–1.

TESF RIR2.5 Transmit Elastic Store Full. Set when the transmit elastic store buffer fills

TESE RIR2.4 Transmit Elastic Store Empty . Set when the transmit elastic store buffer

TSLIP RIR2.3 Transmit Elastic Store Slip Occurrence. Set when the transmit elastic

JALT RIR2.2 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches

RPDV RIR2.1 Receive Pulse Density V iolation. Set when the receive data stream does

TPDV RIR2.0 Transmit Pulse Density Violation. Set when the transmit data stream

and a frame is deleted.

empties and a frame is repeated.

store has either repeated or deleted a frame.

to within 4–bits of it’s limit; useful for debugging jitter attenuation operation.

not meet the ANSI T1.403 requirements for pulse density.

does not meet the ANSI T1.403 requirements for pulse density.

DS2151Q RECEIVE T1 LEVEL INDICATION Table 4–1

RL1 RL0 TYPICAL LEVEL RECEIVED

0 0 +2 dB to –7.5 dB
0 1 –7.5 dB to –15 dB
1 0 –15 dB to –22.5 dB
1 1 less than –22.5 dB

022697 15/46

DS2151Q

SR1: STATUS REGISTER 1 (Address=20 Hex)

(MSB) (LSB)

LUP LDN LOTC RSLIP RBL RYEL RCL RLOS

SYMBOL POSITION NAME AND DESCRIPTION

LUP SR1.7 Loop Up Code Detected. Set when the repeating ...00001... loop up code

LDN SR1.6 Loop Down Code Detected. Set when the repeating ...001... loop down

LOTC SR1.5 Loss of Transmit Clock. Set when the TCLK pin has not transitioned for

RSLIP SR1.4 Receive Elastic Store Slip Occurrence. Set when the receive elastic

RBL SR1.3 Receive Blue Alarm. Set when a blue alarm is received at RTIP and

RYEL SR1.2 Receive Yellow Alarm. Set when a yellow alarm is received at RTIP and

RCL SR1.1 Receive Carrier Loss. Set when 192 consecutive zeros have been

RLOS SR1.0 Receive Loss of Sync. Set when the device is not synchronized to the

is being received.

code is being received.

one channel time (or 5.2us). Will force pin 16 high if enabled via CCR1.6.
Based on RCLK.

store has either repeated or deleted a frame.

RRING. See note below.

RRING.

detected at RTIP and RRING.

receive T1 stream.

DS2151Q ALARM SET AND CLEAR CRITERIA Table 4–2

ALARM SET CRITERIA CLEAR CRITERIA

Blue Alarm (AIS) (see note 1

below)
Yellow Alarm

1. D4 bit 2 mode (RCR2.2=0)

2. D4 12th F–bit mode
(RCR2.2=1; this mode is also
referred to as the “Japanese

when over a 3 ms window, five or
less zeros are received

when bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences

when the 12th framing bit is set to
one for two consecutive occur­rences

when over a 3 ms window, six or
more zeros are received

when bit 2 of 256 consecutive
channels is set to zero for less
than 254 occurrences

when the 12th framing bit is set to
zero for two consecutive occur­rences

Y ellow Alarm”)

3. ESF Mode when 16 consecutive patterns of

00FF hex appear in the FDL

when 14 or less patterns of 00FF
hex out of 16 possible appear in
the FDL

Red Alarm (RCL) (this alarm is
also referred to as Loss of Signal)

when 192 consecutive zeros are
received

when 14 or more ones out of 112
possible bit positions are received
starting with the first one received

NOTE:

1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all ones signal. Blue alarm detectors
should be able to operate properly in the presence of a 10–3 error rate and they should not falsely trigger on a
framed all ones signal. The blue alarm criteria in the DS2151Q has been set to achieve this performance. It is
recommended that the RBL bit be qualified with the RLOS status bit in detecting a blue alarm.

022697 16/46

DS2151Q

LOOP UP/DOWN CODE DETECTION

Bits SR1.7 and SR1.6 will indicate when either the stan­dard “loop up” or “loop down” codes are being received
by the DS2151Q. When a loop up code has been
received for 5 seconds, the CPE is expected to loop the
recovered data (without correcting BPVs) back to the
source. The loop down code indicates that the loopback
should be discontinued. See the AT&T publication TR
62411 for more details. The DS2151Q will detect the
loop up/down codes in both framed and unframed cir-

cumstances with bit error rates as high as 10**–2. The
loop code detector has a nominal integration period of
48 ms. Hence, after about 48 ms of receiving either
code, the proper status bit will be set to a one. After this
initial indication, it is recommended that the software
poll the DS2151Q every 100 ms to 500 ms until
5 seconds has elapsed to insure that the code is contin­uously present. Once 5 seconds has passed, the
DS2151Q should be taken into or out of loopback via the
Remote Loopback (RLB) bit in CCR1.

SR2: STATUS REGISTER 2 (Address=21 Hex)

(MSB) (LSB)

RMF TMF SEC RFDL TFDL RMTCH RAF –

SYMBOL POSITION NAME AND DESCRIPTION

RMF SR2.7 Receive Multiframe. Set on receive multiframe boundaries.

TMF SR2.6 Transmit Multiframe. Set on transmit multiframe boundaries.

SEC SR2.5 One Second Timer . Set on increments of one second based on RCLK; will

RFDL SR2.4 Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to

TFDL SR2.3 Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TFDL)

RMTCH SR2.2 Receive FDL Match Occurrence. Set when the RFDL matches either

RAF SR2.1 Receive FDL Abort. Set when eight consecutive one’s are received in the

– SR2.0 Not Assigned. Should be set to zero when written.

be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds.

capacity (8–bits).

empties.

RFDLM1 or RFDLM2.

FDL.

IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)

(MSB) (LSB)

LUP

SYMBOL POSITION NAME AND DESCRIPTION

LUP IMR1.7 Loop Up Code Detected.

LDN IMR1.6 Loop Down Code Detected.

LOTC IMR1.5 Loss of Transmit Clock.

LDN LOTC SLIP RBL RYEL RCL RLOS

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

022697 17/46

DS2151Q

SLIP IMR1.4 Elastic Store Slip Occurrence.

0=interrupt masked
1=interrupt enabled

RBL IMR1.3 Receive Blue Alarm.

0=interrupt masked
1=interrupt enabled

RYEL IMR1.2 Receive Yellow Alarm.

0=interrupt masked
1=interrupt enabled

RCL IMR1.1 Receive Carrier Loss.

0=interrupt masked
1=interrupt enabled

RLOS IMR1.0 Receive Loss of Sync.

0=interrupt masked
1=interrupt enabled

IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)

(MSB) (LSB)

RMF TMF SEC RFDL TFDL RMTCH RAF –

SYMBOL POSITION NAME AND DESCRIPTION

RMF IMR2.7 Receive Multiframe.

TMF IMR2.6 Transmit Multiframe.

SEC IMR2.5 One Second Timer .

RFDL IMR2.4 Receive FDL Buffer Full.

TFDL IMR2.3 Transmit FDL Buffer Empty.

RMTCH IMR2.2 Receive FDL Match Occurrence.

RAF IMR2.1 Receive FDL Abort.

– IMR2.0 Not Assigned. Should be set to zero when written to.

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

0=interrupt masked
1=interrupt enabled

022697 18/46

DS2151Q

5.0 ERROR COUNT REGISTERS

There are a set of three counters in the DS2151Q that
record bipolar violations, excessive zeros, errors in the
CRC6 code words, framing bit errors, and number of
multiframes that the device is out of receive synchro­nization. Each of these three counters are automatically
updated on one second boundaries as determined by
the one second timer in Status Register 2 (SR2.5).
Hence, these registers contain performance data from
the previous second. The user can use the interrupt
from the one second timer to determine when to read
these registers. The user has a full second to read the
counters before the data is lost. All three counters will
saturate at their respective maximum counts and they

will not rollover (note: only the Line Code Violation
Count Register has the potential to overflow).

5.1 Line Code Violation Count Register
(LCVCR)

Line Code Violation Count Register 1 (LCVCR1) is the
most significant word and LCVCR2 is the least signifi­cant word of a 16–bit counter that records code viola­tions (CVs). CVs are defined as Bipolar Violations
(BPVs) or excessive zeros. See T able 5–1 for details of
exactly what the LCVCRs count. If the B8ZS mode is
set for the receive side via CCR2.2, then B8ZS code
words are not counted. This counter is always enabled;
it is not disabled during receive loss of synchronization
(RLOS=1) conditions.

LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address=23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address=24 Hex)

(MSB) (LSB)

LCV15 LCV14 LCV13 LCV12 LCV11 LCV10 LCV9 LCV8

LCV7 LCV6 LCV5 LCV4 LCV3 LCV2 LCV1 LCV0

SYMBOL POSITION NAME AND DESCRIPTION

LCV15 LCVCR1.7 MSB of the 16–Bit code violation count

LCV0 LCVCR2.0 LSB of the 16–Bit code violation count

LCVCR1
LCVCR2

LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5–1

COUNT EXCESSIVE

ZEROS?

(RCR1.7)

no no BPVs

yes no BPVs + 16 consecutive zeros

no yes BPVs (B8ZS code words not counted)

yes yes BPVs + 8 consecutive zeros

5.2 Path Code Violation Count Register
(PCVCR)

When the receive side of the DS2151Q is set to operate
in the ESF framing mode (CCR2.3=1), PCVCR will
automatically be set as a 12–bit counter that will record
errors in the CRC6 code words. When set to operate in
the D4 framing mode (CCR2.3=0), PCVCR will auto-

B8ZS ENABLED?

(CCR2.2)

WHAT IS COUNTED IN THE LCVCRs

matically count errors in the Ft framing bit position. Via
the RCR2.1 bit, the DS2151Q can be programmed to
also report errors in the Fs framing bit position. The
PCVCR will be disabled during receive loss of synchro­nization (RLOS=1) conditions. See Table 5–2 for a
detailed description of exactly what errors the PCVCR
counts.

022697 19/46

DS2151Q

PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address=25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address=26 Hex)

(MSB) (LSB)

(note 1) (note 1) (note 1) (note 1) CRC/FB1 1 CRC/FB10 CRC/FB9 CRC/FB8

CRC/FB7 CRC/FB6 CRC/FB5 CRC/FB4 CRC/FB3 CRC/FB2 CRC/FB1 CRC/FB0

SYMBOL POSITION NAME AND DESCRIPTION

CRC/FB11 PCVCR1.3 MSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note 2)

CRC/FB0 PCVCR2.0 LSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note 2)

PCVCR1
PCVCR2

NOTES:

1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register.

2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in the fram­ing bit position (in the D4 framing mode; CCR2.3=0).

PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 5–2

FRAMING MODE

(CCR2.3)

D4 no errors in the Ft pattern
D4 yes errors in both the Ft and Fs patterns

ESF don’t care errors in the CRC6 code words

COUNT FS

ERRORS? (RCR2.1)

WHAT IS COUNTED IN THE PCVCRs

5.3 Multiframes Out of Sync Count Register

(MOSCR)

Normally the MOSCR is used to count the number of
multiframes that the receive synchronizer is out of sync
(RCR2.0=1). This number is useful in ESF applications
needing to measure the parameters Loss Of Frame
Count (LOFC) and ESF Error Events as described in
AT&T publication TR54016. When the MOSCR is oper­ated in this mode, it is not disabled during receive loss of

synchronization (RLOS=1) conditions. The MOSCR
has alternate operating mode whereby it will count
either errors in the Ft framing pattern (in the D4 mode) or
errors in the FPS framing pattern (in the ESF mode).
When the MOSCR is operated in this mode, it is dis­abled during receive loss of synchronization (RLOS=1)
conditions. See Table 5–3 for a detailed description of
what the MOSCR is capable of counting.

MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address=25 Hex)
MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address=27 Hex)

(MSB) (LSB)

MOS/FB11 MOS/FB10 MOS/FB9 MOS/FB8 (note 1) (note 1) (note 1) (note 1)

MOS/FB7 MOS/FB6 MOS/FB5 MOS/FB4 MOS/FB3 MOS/FB2 MOS/FB1 MOS/FB0

SYMBOL POSITION NAME AND DESCRIPTION

MOS/FB11 MOSCR1.7 MSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note 2)

MOS/FB0 MOSCR2.0 LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note 2)

022697 20/46

MOSCR1
MOSCR2

DS2151Q

NOTES:

1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.

2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync
(RCR2.0=1).

MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 5–3

COUNT MOS OR

FRAMING MODE

(CCR2.3)

D4 MOS number of multiframes out of sync

D4 F–Bit errors in the Ft pattern
ESF MOS number of multiframes out of sync
ESF F–Bit errors in the FPS pattern

F–BIT ERRORS?

(RCR2.0)

WHAT IS COUNTED IN THE MOSCRs

6.0 FDL/FS EXTRACTION AND INSERTION

The DS2151Q has the ability to extract/insert data from/
into the Facility Data Link (FDL) in the ESF framing
mode and from/into Fs bit position in the D4 framing
mode. Since SLC–96 utilizes the Fs bit position, this
capability can also be used in SLC–96 applications.
The operation of the receive and transmit sections will
be discussed separately.

6.1 Receive Section

In the receive section, the recovered FDL bits or Fs bits
are shifted bit–by–bit into the Receive FDL register
(RFDL). Since the RFDL is 8 bits in length, it will fill up
every 2 ms (8 times 250 us). The DS2151Q will signal
an external microcontroller that the buffer has filled via
the SR2.4 bit. If enabled via IMR2.4, the INT2
toggle low indicating that the buffer has filled and needs
to be read. The user has 2 ms to read this data before it
is lost. If the byte in the RFDL matches either of the
bytes programmed into the RFDLM1 or RFDLM2 regis­ters, then the SR2.2 bit will be set to a one and the INT2

pin will

pin will be toggled low if enabled via IMR2.2. This fea­ture allows an external microcontroller to ignore the FDL
or Fs pattern until an important event occurs.

The DS2151Q also contains a zero destuffer which is
controlled via the CCR2.0 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset
of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that
the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled via
CCR2.0, the DS2151Q will automatically look for 5 ones
in a row, followed by a zero. If it finds such a pattern, it
will automatically remove the zero. If the zero destuffer
sees six or more ones in a row followed by a zero, the
zero is not removed. The CCR2.0 bit should always be
set to a one when the DS2151Q is extracting the FDL.
More on how to use the DS2151Q in FDL and SLC–96
applications is covered in a separate Application Note.

Also, contact the factory for C code software that
implements both ANSI T1.403 and AT&T TR54016.

RFDL: RECEIVE FDL REGISTER (Address=28 Hex)

(MSB) (LSB)

RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0

SYMBOL POSITION NAME AND DESCRIPTION

RFDL7 RFDL.7 MSB of the Received FDL Code
RFDL0 RFDL.0 LSB of the Received FDL Code

The Receive FDL Register (RFDL) reports the incoming
Facility Data Link (FDL) or the incoming Fs bits. The
LSB is received first.

022697 21/46

DS2151Q

RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)

(MSB) (LSB)

RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0

SYMBOL POSITION NAME AND DESCRIPTION

RFDL7 RFDL.7 MSB of the FDL Match Code
RFDL0 RFDL.0 LSB of the FDL Match Code

When the byte in the Receive FDL Register matches
either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), SR2.2 will be set to a one and the
INT2

will go active if enabled via IMR2.2.

6.2 Transmit Section

The transmit section will shift out into the T1 data
stream, either the FDL (in the ESF framing mode) or the
Fs bits (in the D4 framing mode) contained in the Trans­mit FDL register (TFDL). When a new value is written to
the TFDL, it will be multiplexed serially (LSB first) into
the proper position in the outgoing T1 data stream. After
the full eight bits has been shifted out, the DS2151Q will
signal the host microcontroller that the buffer is empty
and that more data is needed by setting the SR2.3 bit to
a one. The INT2
IMR2.3. The user has 2 ms to update the TFDL with a

will also toggle low if enabled via

new value. If the TFDL is not updated, the old value in
the TFDL will be transmitted once again.

The DS2151Q also contains a zero stuffer which is con­trolled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset
of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that
the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled via
CCR2.4, the DS2151Q will automatically look for 5 ones
in a row. If it finds such a pattern, it will automatically
insert a zero after the five ones. The CCR2.4 bit should
always be set to a one when the DS2151Q is inserting
the FDL. More on how to use the DS2151Q in FDL and
SLC–96 applications is covered in a separate Applica­tion Note.

TFDL: TRANSMIT FDL REGISTER (Address=7E Hex)

(MSB) (LSB)

TFDL7

SYMBOL POSITION NAME AND DESCRIPTION

TFDL7 TFDL.7 MSB of the FDL code to be transmitted
TFDL0 TFDL.0 LSB of the FDL code to be transmitted

TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0

The Transmit FDL Register (TFDL) contains the Facility
Data Link (FDL) information that is to be inserted on a

022697 22/46

byte basis into the outgoing T1 data stream. The LSB is
transmitted first.

DS2151Q

7.0 SIGNALING OPERATION

The Robbed–Bit signaling bits embedded in the T1
stream can be extracted from the receive stream and
inserted into the transmit stream by the DS2151Q.
There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to

CCR1.5 bit is used to control the robbed signaling bits
as they appear at RSER. If CCR1.5 is set to zero, then
the robbed signaling bits will appear at RSER in their
proper position as they are received. If CCR1.5 is set to
a one, then the robbed signaling bit positions will be
forced to a one at RSER.

TS12). The signaling registers are detailed below. The

RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)

(MSB) (LSB)

A(8) A(7) A(6) A(5) A(4) A(3) A(2) A(1)
A(16) A(15) A(14) A(13) A(12) A(11) A(10) A(9)
A(24) A(23) A(22) A(21) A(20) A(19) A(18) A(17)

B(8) B(7) B(6) B(5) B(4) B(3) B(2) B(1)
B(16) B(15) B(14) B(13) B(12) B(11) B(10) B(9)
B(24) B(23) B(22) B(21) B(20) B(19) B(18) B(17)

A/C(8) A/C(7) A/C(6) A/C(5) A/C(4) A/C(3) A/C(2) A/C(1)
A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)
A/C(24) A/C(23) A/C(22) A/C(1) A/C(20) A/C(19) A/C(18) A/C(17)

B/D(8) B/D(7) B/D(6) B/D(5) B/D(4) B/D(3) B/D(2) B/D(1)
B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9)
B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17)

RS1 (60)

RS1 (60)

RS1 (60)

RS1 (60)

RS1 (60)

RS1 (60)

RS1 (60)

RS1 (60)
RS2 (61)

RS2 (61)

RS2 (61)

RS2 (61)

RS2 (61)

RS2 (61)

RS2 (61)

RS2 (61)
RS3 (62)

RS3 (62)

RS3 (62)

RS3 (62)

RS3 (62)

RS3 (62)

RS3 (62)

RS3 (62)
RS4 (63)

RS4 (63)

RS4 (63)

RS4 (63)

RS4 (63)

RS4 (63)

RS4 (63)

RS4 (63)
RS5 (64)

RS5 (64)

RS5 (64)

RS5 (64)

RS5 (64)

RS5 (64)

RS5 (64)

RS5 (64)
RS6 (65)

RS6 (65)

RS6 (65)

RS6 (65)

RS6 (65)

RS6 (65)

RS6 (65)

RS6 (65)
RS7 (66)

RS7 (66)

RS7 (66)

RS7 (66)

RS7 (66)

RS7 (66)

RS7 (66)

RS7 (66)
RS8 (67)

RS8 (67)

RS8 (67)

RS8 (67)

RS8 (67)

RS8 (67)

RS8 (67)

RS8 (67)
RS9 (68)

RS9 (68)

RS9 (68)

RS9 (68)

RS9 (68)

RS9 (68)

RS9 (68)

RS9 (68)
RS10 (69)

RS10 (69)

RS10 (69)

RS10 (69)

RS10 (69)

RS10 (69)

RS10 (69)

RS10 (69)
RS11 (6A)

RS11 (6A)

RS11 (6A)

RS11 (6A)

RS11 (6A)

RS11 (6A)

RS11 (6A)

RS11 (6A)
RS12 (6B)

RS12 (6B)

RS12 (6B)

RS12 (6B)

RS12 (6B)

RS12 (6B)

RS12 (6B)

RS12 (6B)

SYMBOL POSITION NAME AND DESCRIPTION

D(24) RS12.7 Signaling Bit D in Channel 24

A(1) RS1.0 Signaling Bit A in Channel 1

Each Receive Signaling Register (RS1 to RS12) reports
the incoming Robbed–Bit signaling from eight DS0
channels. In the ESF framing mode, there can be up to
four signaling bits per channel (A, B, C, and D). In the D4
framing mode, there are only two framing bits per chan­nel (A and B). In the D4 framing mode, the DS2151Q will
replace the C and D signaling bit positions with the A and
B signaling bits from the previous multiframe. Hence,
whether the DS2151Q is operated in either framing

mode, the user needs only to retrieve the signaling bits
every 3ms. The bits in the Receive Signaling Registers
are updated on multiframe boundaries so the user can
utilize the Receive Multiframe Interrupt in the Receive
Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The Receive Signaling Registers are fro­zen and not updated during a loss of sync condition
(SR1.0=1). They will contain the most recent signaling
information before the “OOF” occurred.

022697 23/46

DS2151Q

TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)

(MSB) (LSB)

A(8)
A(16) A(15) A(14) A(13) A(12) A(11) A(10) A(9)
A(24) A(23) A(22) A(21) A(20) A(19) A(18) A(17)

B(8) B(7) B(6) B(5) B(4) B(3) B(2) B(1)
B(16) B(15) B(14) B(13) B(12) B(11) B(10) B(9)
B(24) B(23) B(22) B(21) B(20) B(19) B(18) B(17)

A/C(8) A/C(7) A/C(6) A/C(5) A/C(4) A/C(3) A/C(2) A/C(1)
A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)
A/C(24) A/C(23) A/C(22) A/C(1) A/C(20) A/C(19) A/C(18) A/C(17)

B/D(8) B/D(7) B/D(6) B/D(5) B/D(4) B/D(3) B/D(2) B/D(1)
B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9)
B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17)

SYMBOL POSITION NAME AND DESCRIPTION

D(24) TS12.7 Signaling Bit D in Channel 24

A(7) A(6) A(5) A(4) A(3) A(2) A(1)

A(1) TS1.0 Signaling Bit A in Channel 1

TS1 (70)
TS2 (71)
TS3 (72)
TS4 (73)
TS5 (74)
TS6 (75)
TS7 (76)
TS8 (77)
TS9 (78)
TS10 (79)
TS11 (7A)
TS12 (7B)

Each Transmit Signaling Register (TS1 to TS12) con­tains the Robbed–Bit signaling for eight DS0 channels
that will be inserted into the outgoing stream if enabled
to do so via TCR1.4. In the ESF framing mode, there
can be up to four signaling bits per channel (A, B, C, and
D). On multiframe boundaries, the DS2151Q will load
the values present in the Transmit Signaling Register
into an outgoing signaling shift register that is internal to
the device. The user can utilize the Transmit Multiframe
Interrupt in Status Register 2 (SR2.6) to know when to
update the signaling bits. In the ESF framing mode, the
interrupt will come every 3 ms and the user has a full 3
ms to update the TSRs. In the D4 framing mode, there
are only two framing bits per channel (A and B). How­ever in the D4 framing mode, the DS2151Q uses the C

022697 24/46

and D bit positions as the A and B bit positions for the
next multiframe. The DS2151Q will load the values in
the TSRs into the outgoing shift register every other D4
multiframe.

8.0 SPECIAL TRANSMIT SIDE REGISTERS

There is a set of seven registers in the DS2151Q that
can be used to custom tailor the data that is to be trans­mitted onto the T1 line, on a channel by channel basis.
Each of the 24 T1 channels can be either forced to be
transparent or to have a user defined idle code inserted
into them. Each of these special registers is defined
below.

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address=39 to 3B Hex)

(MSB) (LSB)

CH8

CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

SYMBOL POSITION NAME AND DESCRIPTION

CH24 TTR3.7 Transmit Transparency Registers.

0=this DS0 channel is not transparent

CH1 TTR1.0 1=this DS0 channel is transparent

Each of the bit positions in the Transmit Transparency
Registers (TTR1/TTR2/TTR3) represent a DS0 chan­nel in the outgoing frame. When these bits are set to a
one, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no Robbed–
Bit signaling will be inserted nor will the channel have Bit
7 stuffing performed. However, in the D4 framing mode,
bit 2 will be overwritten by a zero when a Y ellow Alarm is

TTR registers from determining which channels are to
have Bit 7 stuffing performed. If the TCR2.0 and
TCR1.3 bits are set to one, then all 24 T1 channels will
have Bit 7 stuffing performed on them regardless of how
the TTR registers are programmed. In this manner, the
TTR registers are only affecting which channels are to
have Robbed–Bit signaling inserted into them. Please
see Figure 13–9 for more details.

transmitted. Also the user has the option to prevent the

TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)

(MSB) (LSB)

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

DS2151Q

TTR1 (39)
TTR2 (3A)
TTR3 (3B)

TIR1 (3C)
TIR2 (3D)
TIR3 (3E)

SYMBOL POSITION NAME AND DESCRIPTION

CH24 TIR3.7 Transmit Idle Registers.

0=do not insert the Idle Code into this DS0 channel

CH1 TIR1.0 1=insert the Idle Code into this channel

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)

(MSB) (LSB)

TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0

SYMBOL POSITION NAME AND DESCRIPTION

TIDR7 TIDR.7 MSB of the Idle Code
TIDR0 TIDR.0 LSB of the Idle Code

Each of the bit positions in the Transmit Idle Registers
(TIR1/TIR2/TIR3) represent a DS0 channel in the out­going frame. When these bits are set to a one, the corre­sponding channel will transmit the Idle Code contained

in the Transmit Idle Definition Register (TIDR).
Robbed–Bit signaling and Bit 7 stuffing will occur over
the programmed Idle Code unless the DS0 channel is

022697 25/46

DS2151Q

made transparent by the Transmit T ransparency Regis­ters.

9.0 CLOCK BLOCKING REGISTERS

The Receive Channel Blocking Registers
(RCBR1/RCBR2/RCBR3) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3) control
the RCHBLK and TCHBLK pins respectively. The

RCHBLK and TCHCLK pins are user programmable
outputs that can be forced either high or low during indi­vidual channels. These outputs can be used to block
clocks to a UART or LAPD controller in Fractional T1 or
ISDN–PRI applications. When the appropriate bits are
set t o a one, the RCHBLK and TCHCLK pins will be held
high during the entire corresponding channel time. See
the timing in Section 13 for an example.

RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex)

(MSB) (LSB)

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

SYMBOL POSITION NAME AND DESCRIPTION

CH24 RCBR3.7 Receive Channel Blocking Registers.

0=force the RCHBLK pin to remain low during this channel time

CH1 RCBR1.0 1=force the RCHBLK pin high during this channel time

RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)

TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex)

(MSB) (LSB)

CH8
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

CH7 CH6 CH5 CH4 CH3 CH2 CH1

TCBR1 (32)
TCBR2 (33)
TCBR3 (34)

SYMBOL POSITION NAME AND DESCRIPTION

CH24 TCBR3.7 Transmit Channel Blocking Registers.

CH1 TCBR1.0 1=force the TCHBLK pin high during this channel time

10.0 ELASTIC STORES OPERATION

The DS2151Q has two onboard two–frame (386 bits)
elastic stores. These elastic stores have two main pur­poses. First, they can be used to rate convert the T1
data stream to 2.048 Mbps (or a multiple of 2.048 Mbps)
which is the E1 rate. Secondly, they can be used to
absorb the differences in frequency and phase between
the T1 data stream and an asynchronous (i.e., not fre­quency locked) backplane clock. Both elastic stores
contain full controlled slip capability which is necessary
for this second purpose. The receive side elastic store
can be enabled via CCR1.2 and the transmit side elastic
store is enabled via CCR1.7. The elastic stores can be

022697 26/46

0=force the TCHBLK pin to remain low during this channel time

forced to a known depth via the Elastic Store Reset bit
(CCR3.6).

10.1 Receive Side

If the receive side elastic store is enabled (CCR1.2=1),
then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the
SYSCLK pin. The user has the option of either providing
a frame sync at the RFSYNC pin (RCR2.3=1) or having
the RFSYNC pin provide a pulse on frame boundaries
(RCR2.3=0). If the user wishes to obtain pulses at the
frame boundary , then RCR2.4 must be set to zero and if
the user wishes to have pulses occur at the multiframe

DS2151Q

boundary , then RCR2.4 must be set to one. If the user
selects to apply a 2.048 MHz clock to the SYSCLK pin,
then the data output at RSER will be forced to all ones
every fourth channel and the F–bit will be deleted.
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots
0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a one.
Also, in 2.048 MHz applications, the RCHBLK output
will be forced high during the same channels as the
RSER pin. See Section 13 for more details. This is use­ful in T1 to CEPT (E1) conversion applications. If the
386–bit elastic buffer either fills or empties, a controlled
slip will occur. If the buffer empties, then a full frame of
data (193 bits) will be repeated at RSER and the SR1.4
and RIR1.3 bits will be set to a one. If the buffer fills, then
a full frame of data will be deleted and the SR1.4 and
RIR1.4 bits will be set to a one.

10.2 Transmit Side

The transmit side elastic store can only be used if the
receive side elastic store is enabled. The operation of
the transmit elastic store is very similar to the receive
side; both have controlled slip operation and both can
operate with either a 1.544 MHz or a 2.048 MHz
SYSCLK. When the transmit elastic store is enabled,
both the SYSCLK and RSYNC signals are shared by
both the elastic stores. Hence, they will have the same
backplane PCM frame and data structure. Controlled
slips in the transmit elastic store are reported in the
RIR2.5 bit and the direction of the slip is reported in the
RIR2.3 and RIR2.4 bits.

T1 clock (i.e., the RCLK output), the full two frame depth
of the onboard elastic stores is really not needed. In
fact, in some delay sensitive applications, the normal
two frame depth may be excessive. If the CCR3.7 bit is
set to one, then the receive elastic store (and also the
transmit elastic store if it is enabled) will be forced to a
maximum depth of 32 bits instead of the normal 386 bits.
In this mode, the SYSCLK must be frequency locked to
RCLK and all of the slip contention logic in the DS2151Q
is disabled (since slips cannot occur). Also, since the
buffer depth is no longer two frames deep, the DS2151Q
must be set up to source either a frame or multiframe
pulse at the RSYNC pin. On power–up after the
SYSCLK has locked to the RCLK signal, the elastic
store reset bit (CCR3.6) should be toggled from a zero
to a one to insure proper operation.

11.0 RECEIVE MARK REGISTERS

The DS2151Q has the ability to replace the incoming
data, on a channel–by–channel basis with either an idle
code (7F Hex) or the digital milliwatt code which is an
eight byte repeating pattern that represents a 1 KHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7
bit will determine which code is used. Each bit in the
RMRs, represents a particular channel. If a bit is set to a
one, then the receive data in that channel will be
replaced with one of the two codes. If a bit is set to zero,
no replacement occurs.

10.3 Minimum Delay Synchronous SYSCLK
Mode

In applications where the DS2151Q is connected to
backplanes that are frequency locked to the recovered

RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)

(MSB) (LSB)

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

SYMBOL POSITION NAME AND DESCRIPTION

CH24 RMR3.7 Receive Channel Blocking Registers.

0=do not affect the receive data associated with this channel

CH1 RMR1.0 1=replace the receive data associated with this channel with either the idle

code or the digital milliwatt code (depends on the RCR2.7 bit)

RMR1 (2D)
RMR2 (2E)
RMR3 (2F)

022697 27/46

DS2151Q

12.0 LINE INTERFACE FUNCTIONS

The line interface function in the DS2151Q contains
three sections; (1) the receiver which handles clock and

and drives the T1 line, and (3) the jitter attenuator. Each
of the these three sections is controlled by the Line Inter­face Control Register (LICR) which is described below.

data recovery, (2) the transmitter which waveshapes

LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)

(MSB) (LSB)

L2 L1 L0 EGL JAS JABDS DJA TPD

SYMBOL POSITION NAME AND DESCRIPTION

L2 LICR.7 Line Build Out Select Bit 2 . Sets the transmitter build out; see the Table

L1 LICR.6 Line Build Out Select Bit 1. Sets the transmitter build out; see the Table 12–2
L0 LICR.5 Line Build Out Select Bit 0. Sets the transmitter build out; see the Table 12–2

EGL LICR.4 Receive Equalizer Gain Limit.

JAS LICR.3 Jitter Attenuator Select.

JABDS LICR.2 Jitter Attenuator Buffer Depth Select .

DJA LICR.1 Disable Jitter Attenuator.

TPD LICR.0 Transmit Power Down.

12–2

0= –36 dB
1= –30 dB

0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side

0=128 bits
1=32 bits (use for delay sensitive applications)

0=jitter attenuator enabled
1=jitter attenuator disabled

0=normal transmitter operation
1=powers down the transmitter and 3–states the TTIP and TRING pins

LICR

12.1 Receive Clock and Data Recovery

The DS2151Q contains a digital clock recovery system.
See the DS2151Q Block Diagram in Section 1 and Fig­ure 12–1 for more details. The DS2151Q couples to the
receive T1 twisted pair via a 1:1 transformer. See Table
12–3 for transformer details. The DS2151Q automati­cally adjusts to the T1 signal being received at the RTIP
and RRING pins and can handle T1 lines from 0 feet to
over 6000 feet in length. The crystal attached at the
XTAL1 and XT AL2 pins is multiplied by four via an inter­nal PLL and fed to the clock recovery system. The clock
recovery system uses both edges of the clock from the
PLL circuit to form a 32 times oversampler which is used
to recover the clock and data. This oversampling tech­nique offers outstanding jitter tolerance (see Figure
12–2). The EGL bit in the Line Interface Control Regis­ter is used to limit the sensitivity of the receiver in the

022697 28/46

DS2151Q. For most CPE applications, a receiver sen­sitivity of –30 dB is wholly sufficient and hence the EGL
bit should be set to one. In some applications, more
sensitivity than –30 dB may be required and the
DS2151Q will allow the receiver to go as low as –36 dB if
the EGL bit is set to zero. However when the EGL bit is
set to zero, the DS2151Q will be more susceptible to
crosstalk and its jitter tolerance will suffer.

Normally, the clock that is output at the RCLK pin is the
recovered clock from the T1 AMI waveform presented
at the RTIP and RRING inputs. When no AMI signal is
present at RTIP and RRING, a Receive Carrier Loss
(RCL) condition will occur and the RCLK can be sourced
from either the ACLKI pin or from the crystal attached to
the XTAL1 and XTAL2 pins. The DS2151Q will sense
the ACLKI pin to determine if a clock is present. If no

DS2151Q

clock is applied to the ACLKI pin, then it should be tied to
RVSS to prevent the device from falsely sensing a
clock. See Table 12–1. If the jitter attenuator is either
placed in the transmit path or is disabled, the RCLK out­put can exhibit short high cycles of the clock. This is due
to the highly oversampled digital clock recovery cir-

SOURCE OF RCLK UPON RCL Table 12–1

ACLKI PRESENT? RECEIVE SIDE JITTER

ATTENUATOR

Yes ACLKI via the jitter attenuator ACLKI

No centered crystal TCLK via the jitter attenuator

12.2 Transmit Waveshaping and Line Driving

The DS2151Q uses a set of laser–trimmed delay lines
along with a precision Digital–to–Analog Converter
(DAC) to create the waveforms that are transmitted onto
the T1 line. The waveforms created by the DS2151Q

LBO SELECT IN LICR Table 12–2

L2 L1 L0 LINE BUILD OUT APPLICATION

0 0 0 0 to 133 feet/0 dB DSX–1/CSU
0 0 1 133 to 266 feet DSX–1
0 1 0 266 to 399 feet DSX–1
0 1 1 399 to 533 feet DSX–1
1 0 0 533 to 655 feet DSX–1
1 0 1 –7.5 dB CSU
1 1 0 –15 dB CSU
1 1 1 –22.5 dB CSU

cuitry. If the jitter attenuator is placed in the receive path
(as is the case in most applications), the jitter attenuator
restores the RCLK to being close to 50% duty cycle.
Please see the Receive AC Timing Characteristics in
Section 14 for more details.

TRANSMIT SIDE JITTER

ATTENUATOR

meet the latest ANSI, AT&T, and CCITT specifications.
See Figure 12–3. The user will select which waveform
is to be generated by properly programming the L0 to L2
bits in the Line Interface Control Register (LICR).

Due to the nature of the design of the transmitter in the
DS2151Q, very little jitter (less then 0.005 UIpp broad­Band from 10Hz to 100 KHz) is added to the jitter pres­ent on TCLK. Also, the waveforms that they create are
independent of the duty cycle of TCLK. The transmitter

in the DS2151Q couples to the T1 transmit twisted pair
via a 1:1.15 or 1:1.36 step up transformer as shown in
Figure 12–1. In order for the devices to create the
proper wavefroms, the transformer used must meet the
specifications listed in Table 12–3.

022697 29/46

DS2151Q

TRANSFORMER SPECIFICATIONS Table 12–3

SPECIFICATION RECOMMENDED VALUE

Turns Ratio 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%
Primary Inductance 600 µH minimum
Leakage Inductance 1.0 µH maximum
Interwinding Capacitance 40 pF maximum
DC Resistance 1.2 ohms maximum

12.3 JITTER ATTENUATOR

The DS2151Q contains an onboard jitter attenuator that
can be set to a depth of either 32 or 128 bits via the
JABDS bit in the Line Interface Control Register (LICR).
The 128–bit mode is used in applications where large
excursions of wander are expected. The 32–bit mode is
used in delay sensitive applications. The characteris­tics of the attenuation are shown in Figure 12–4. The jit­ter attenuator can be placed in either the receive path or
t he transmit path by appropriately setting or clearing the
JAS bit in the LICR. Also, the jitter attenuator can be dis­abled (in effect, removed) by setting the DJA–bit in the
LICR. In order for the jitter attenuator to operate prop-

The jitter attenuator divides the clock provided by the

6.176 MHz crystal at the XTAL1 and XTAL2 pins to
create an output clock that contains very little jitter.
Onboard circuitry will pull the crystal (by switching in or
out load capacitance) to keep it long term averaged to
the same frequency as the incoming T1 signal. If the
incoming jitter exceeds either 120UIpp (buffer depth is
128 bits) or 28 UIpp (buffer depth is 32 bits), then the
DS2151Q will divide the attached crystal by either 3.5 or

4.5 instead of the normal 4 to keep the buffer from over­flowing. When the device divides by either 3.5 or 4.5, it
also sets the Jitter Attenuator Limit Trip (JAL T) bit in the

Receive Information Register 2 (RIR2.2).
erly, a crystal with the specifications listed in Table 12–4
below must be connected to the XTAL1 and XT AL2 pins.

CRYSTAL SELECTION GUIDELINES Table 12–4

PARAMETER SPECIFICATION

Parallel Resonant Frequency 6.176 MHz
Mode Fundamental
Load Capacitance 18 pF to 20 pF (18.5 pF nominal)
Tolerance ±50 ppm
Pullability CL=10 pF, delta frequency=+175 to +250 ppm

Effective Series Resistance 40 ohms maximum
Crystal Cut AT

CL=45 pF, delta frequency=–175 to –250 ppm

022697 30/46

DS2151Q EXTERNAL ANALOG CONNECTIONS Figure 12–1

0.47 µF

T1 TRANSMIT

PAIR

1.15:1 (Rt=0 ohms) or

1.36:1 (Rt=4.7 ohms)

(NON–POLARIZED)

Rt

Rt

DS2151Q

TTIP

TRING

DVDD

DVSS

RVDD

RVSS

0.01 µF

0.1 µF

+5V

DS2151Q

+

68 µF0.1 µF

T1 RECEIVE

PAIR

NOTE: KEEP THE LINES TO RTIP AND
RRING AS SHORT AS POSSIBLE AND
ROUTE THEM VIA THE EXACT SAME
PATH.

1:1

R1 R2

0.1 µF

R1=R2=50 OHMS (+1%)

RTIP

RRING

TVDD

TVSS

XTAL1

XTAL2

NOTE:

See the separate Application Note for details on how to construct a protected interface.

DS2151Q JITTER TOLERANCE Figure 12–2

1K

100

10

DS2151Q

TOLERANCE

0.1 µF

6.176 MHz

UNIT INTERVALS (Ulpp)

0.1

MINIMUM TOLERANCE

LEVEL AS PER

1

TR 62411 (DEC. 90)

10 100 1K 10K 100K1

FREQUENCY (Hz)

022697 31/46

DS2151Q

DS2151Q TRANSMIT WAVEFORM TEMPLATE Figure 12–3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

NORMALIZED AMPLITUDE

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

NOTE: The template shown fits inside
the templates of T1.403/89 and
T1E1.2/93.

T1.102/87, T1X1.4/93,

CB 119 (Oct. 79), &

I.431 T emplate

–0.77
–0.39
–0.27
–0.27
–0.12

MAXIMUM CURVE

UI Time Amp.

–500

0.05

–255

0.05

–175

0.80

–175

1.15

–75
175

225
600
750

1.15

0

1.05

1.05

–0.07

0.05

0.05

0.00

0.27

0.35

0.93

1.16

MINIMUM CURVE

UI Time Amp.

–0.77

–500

–0.23

–150

–0.23

–150

–0.15

–100

0.00

0

0.15

100

0.23

150

0.23

150

0.46

300

0.66

430

0.93

600

1.16

750

–0.05
–0.05

0.50

0.95

0.95

0.90

0.50
–0.45
–0.45
–0.20
–0.05
–0.05

–500 –400 –300 –200 –100 0 100 200 300 400 500 600 700

DS2151Q JITTER ATTENUATION Figure 12–4

0 dB

–20 dB

–40 dB

JITTER ATTENUA TION (dB)

–60 dB

1 10 100 1K 10K 100K

022697 32/46

TIME (ns)

FREQUENCY (Hz)

TR 62411 (DEC. 90)

PROHIBITED

AREA

13.0 TIMING DIAGRAMS
RECEIVE SIDE D4 TIMING Figure 13–1

FRAME#

RSYNC

RSYNC

RSYNC

RLCLK

RLINK

1

2

3

4

12 345 67891011121 23 45

NOTES:

1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0).

2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1).

3. RSYNC in the multiframe mode (RCR2.4=1).

4. RLINK data (S–bit) is updated one bit prior to even frames and held for two frames.

RECEIVE SIDE ESF TIMING Figure 13–2

FRAME#

1 2 3 4 5 6 7 8 91011121314151617

18 19 20 21 22 23 24

DS2151Q

1

RSYNC

2

RSYNC

3

RSYNC

4

RLCLK

5

RLINK

6

RLCLK

7

RLINK

NOTES:

1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0).

2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1).

3. RSYNC in the multiframe mode (RCR2.4=1).

4. ZBTSI mode disabled (RCR2.6=0).

5. RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames.

6. ZBTSI mode is enabled (RCR2.6=1).

7. RLINK data (Z bits) is updated one bit time before odd frame and held for four frames.

022697 33/46

DS2151Q

RECEIVE SIDE BOUNDARY TIMING WITH ELASTIC STORE(S) DISABLED Figure 13–3

RCLK

CHANNEL 23 CHANNEL 24 CHANNEL 1

RSER

RSYNC

RCHCLK

RCHBLK

RLCLK

RLINK

1

LSB MSB LSB MSBF

NOTES:

1. RCHBLK is programmed to block channel 24.

2. An ESF boundary is shown.

022697 34/46

1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–4

SYSCLK

TSER/
RSER

RSYNC

RSYNC

RCHCLK

RCHBLK

LSB MSB LSB MSBF

1

2

3

CHANNEL 24 CHANNEL 1CHANNEL 23

NOTES:

1. RSYNC is in the output mode (RCR2.3=0).

2. RSYNC is in the input mode (RCR2.3=1).

3. RCHBLK is programmed to block channel 24.

2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–5

DS2151Q

SYSCLK

TSER/

1

RSER

RSYNC

RSYNC

RCHCLK

RCHBLK

LSB MSB LSB

2

3

4

CHANNEL 32 CHANNEL 1CHANNEL 31

NOTES:

1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1; TSER ignored during these channels.

2. RSYNC is in the output mode (RCR2.3=0).

3. RSYNC is in the input mode (RCR2.3=1).

4. RCHBLK is forced to 1 in the same channels as RSER (see Note 1).

022697 35/46

DS2151Q

TRANSMIT SIDE D4 TIMING Figure 13–6

FRAME#

TSYNC

TSYNC

TSYNC

TLCLK

4

TLINK

1

2

3

1 234 56 7891011121 234 5

NOTES:

1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).

2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).

3. TSYNC in the multiframe mode (TCR2.3=1).

4. TLINK data (S–bit) is sampled during the F–bit position of even frames for insertion into the outgoing T1
stream when enabled via TCR1.2.

TRANSMIT SIDE ESF TIMING Figure 13–7

FRAME#

1 2 3 4 5 6 7 8 9 101112131415161718192021222324

1

TSYNC

2

TSYNC

3

TSYNC

4

TLCLK

5

TLINK

6

TLCLK

7

TLINK

NOTES:

1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).

2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).

3. TSYNC in the multiframe mode (TCR2.4=1).

4. ZBTSI mode disabled (TCR2.5=0).

022697 36/46

DS2151Q

5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if
enabled via TCR1.2.

6. ZBTSI mode is enabled (TCR2.5=1).

7. TLINK data (Z bits) is sampled during the F-bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into the outgoing
stream if enabled via TCR1.2.

TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED) Figure 13–8

TCLK

1

TSER

TSYNC

TSYNC

TCHCLK

TCHBLK

CHANNEL 1

LSB MSBLSB MSBF

1

2

3

CHANNEL 2

LSB MSB

TLCLK

TLINK

Don’t Care

NOTES:

1. TSYNC is in the input mode (TCR2.2=0).

2. TSYNC is in the output mode (TCR2.2=1).

3. TCHBLK is programmed to block channel 1.

4. See Figures 13–4 and 13–5 for details on timing with the transmit side elastic store enabled.

022697 37/46

DS2151Q

DS2151Q TRANSMIT DATA FLOW Figure 13–9

TIR1 TO TIR3

TIDR

IDLE CODE MUX

TSER

01

TS1 TO TS12

ROBBED BIT SIGNALING ENABLE (TCR1.4)

TTR1 TO TTR3

TTR1 TO TTR3

GLOBAL BIT 7 STUFFING (TCR1.3)

BIT 7 ZERO SUPPRESSION ENABLE (TCR2.0)

TRANSMIT LOOP UP CODE (CCR3.1)

TRANSMIT LOOP DOWN CODE (CCR3.2)

FRAME MODE SELECT (CCR2.7)

D4 YELLOW ALARM SELECT (TCR2.1)

TRANSMIT YELLOW (TCR1.0)

FPS PATTERN

Ft PATTERN

FRAME MODE SELECT (CCR2.7)

FRAMING PASS THROUGH (TCR1.6)

FRAME MODE SELECT (CCR2.7)

CRC PASS THROUGH (TCR1.5)

TFDL

TLINK

10

SIGNALING MUX

BIT 7 STUFFING

LOOP CODE GENERATION

D4 BIT 2 YELLOW

ALARM INSERTION

1

0

FPS/Ft MUX

CRC CALCULATION

0

MUX

1

FDL/Fs

10

10

CRC MUX

022697 38/46

KEY

= REGISTER
= DEVICE PIN

= SELECTOR

TLINK SELECT (TCR1.2)

FRAME MODE SELECT (CCR2.7)

D4 YELLOW ALARM SELECT (TCR2.1)

TRANSMIT YELLOW (TCR1.0)

FRAME MODE SELECT (CCR2.7)

TRANSMIT YELLOW (TCR1.0

PULSE DENSITY ENFORCER ENABLE (CCR3.3)

PULSE DENSITY VIOLATION (RIR2.0)

TRANSMIT BLUE (TCR1.1)

B8ZS ENABLE (CCR2.6)

D4 12th Fs BIT

YELLOW ALARM GEN.

ESF YELLOW ALARM GEN.

(00FF HEX IN THE FDL)

ONE’S DENSITY MONITOR

AMI OR B8ZS CONVERTER/

BLUE ALARM GEN.

TO WAVESHAPING, FILTERS, AND

LINE DRIVERS

DS2151Q

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –1.0V to +7.0V
Operating Temperature 0°C to +70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

(–40°C to +85°C for DS2151QN)

RECOMMENDED DC OPERATION CONDITIONS (0°C to 70°C)

(–40°C to +85°C for DS2151QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 V
Logic 0 V
Supply V

IH

DD

2.0 V

IL

–0.3 +0.8 V

4.75 5.25 V 1

+0.3 V

DD

CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
Output Capacitance C

IN

OUT

5 pF
7 pF

DC CHARACTERISTICS (0°C to 70°C; VDD=5V + 5%)

(–40°C to +85°C for DS2151QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Current @ 5V I
Input Leakage I
Output Leakage I
Output Current (2.4V) I
Output Current (0.4V) I

DD

LO

OH

OL

IL

–1.0 +1.0 µA 3

–1.0 mA

+4.0 mA

65 mA 2

1.0 µA 4

NOTES:

1. Applies to RVDD, TVDD, and DVDD.

2. TCLK=1.544 MHz.

3. 0.0V < V

4. Applies to INT1

< VDD.

IN

and INT2 when 3–stated.

022697 39/46

DS2151Q

AC CHARACTERISTICS - PARALLEL PORT (0°C to 70°C; VDD=5V + 5%)

(–40°C to +85°C for DS2151QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Cycle Time t

CYC

Pulse Width, DS Low or RD High PW
Pulse Width, DS High or RD Low PW
Input Rise/Fall Times tR, t
R/W Hold Time t
R/W Setup Time Before DS High t
CS Setup Time Before DS, WR or

active

RD
CS Hold Time t
Read Data Hold Time t
Write Data Hold Time t
Muxed Address Valid to AS or

ALE fall
Muxed Address Hold Time t
Delay Time DS, WR or RD to AS

or ALE Rise

RWH
RWS

t

CS

CH
DHR
DHW

t

ASL

AHL

t

ASD

Pulse Width AS or ALE High PW
Delay Time, AS or ALE to DS,

or RD

WR
Output Data Delay Time from DS

or RD
Data Setup Time t

t

ASED

t

DDR

DSW

EL
EH

F

ASH

250 ns
150 ns
100 ns

30 ns
10 ns
50 ns
20 ns

0 ns

10 50 ns

0 ns

20 ns

10 ns
25 ns

40 ns
20 ns

20 100 ns

80 ns

INTEL BUS READ AC TIMING

ALE

t

ASD

WR

t

ASD

RD

CS

AD0-AD7

022697 40/46

PW

EL

t

ASL

PW

ASH

t

t

AHL

t

ASED

CS

t

CYC

t

DDR

PW

EH

t

CH

t

DHR

INTEL BUS WRITE AC TIMING

ALE

t

ASD

PW

ASH

t

DS2151Q

CYC

RD

t

WR

CS

AD0-AD7

MOTOROLA BUS AC TIMING

AS

DS

R/W

t

ASD

ASD

PW

t

ASL

PW

PW

t

ASED

PW

PW

EH

t

CH

t

DHW

t

DSW

EH

t

RWH

EL

t

CS

t

AHL

ASH

t

ASED

EL

t

RWS

t

CYC

AD0-AD7

(READ)

CS

AD0-AD7

(WRITE)

t

ASL

t

ASL

t

t

AHL

AHL

t

DDR

t

CS

t

DSW

t

DHR

t

CH

t

DHW

022697 41/46

DS2151Q

AC CHARACTERISTICS – RECEIVE SIDE (0° C to 70°C; VDD=5V ± 5%)

(–40°C to +85°C for DS2151QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

ACLKI/RCLK Period t
RCLK Pulse Width t

RCLK Pulse Width t

SYSCLK Period t

SYSCLK Pulse Width t

RSYNC Set Up to SYSCLK Fal­ling

RSYNC Pulse Width t

t

t

t

t
t

CP
CH

CL

CH

CL
SP

SP

SH

SL

SU

PW

SYSCLK Rise/Fall Times tR, t
Delay RCLK or SYSCLK to RSER

Valid
Delay RCLK or SYSCLK to

RCHCLK
Delay RCLK or SYSCLK to

RCHBLK
Delay RCLK or SYSCLK to

RSYNC
Delay RCLK to RLCLK t
Delay RCLK to RLINK Valid t

t

t

t

t

DD

D1

D2

D3

D4
D5

230
230

115
115

75
75

25 tSH–5 ns

50 ns

F

10 80 ns

10 90 ns

10 90 ns

10 80 ns

10 80 ns
10 110 ns

648 ns
324

324

ns
ns

ns
ns

648
488

ns
ns

ns

25 ns

1

2

3
4

NOTES:

1. Jitter attenuator enabled in the receive side path.

2. Jitter attenuator disabled or enabled in the transmit path.

3. SYSCLK=1.544 MHz

4. SYSCLK=2.048 MHz

022697 42/46

RECEIVE SIDE AC TIMING

RCLK

t

R

SYSCLK

RSER

RCHCLK

DS2151Q

t

CP

t

CL

t

t

F

t

DD

F–BIT OR MSB

OF CHANNEL 1

t

D1

SL

t

CH

t

SH

t

SP

RCHBLK

RSYNC

RSYNC

t

D3

1

t

t

SU

2

t

D4

PW

t

D2

RLCLK

t

D5

RLINK

NOTES:

1. RSYNC is in the output mode (RCR2.3=0).

2. RSYNC is in the input mode (RCR2.3=1).

3. RLCLK and RLINK only have a timing relationship to RCLK.

4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.

022697 43/46

DS2151Q

AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD=5V + 5%)

(–40°C to +85°C for DS2151QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

TCLK Period t
TCLK Pulse Width t

TSER and TLINK Set Up to TCLK
Falling

TSER and TLINK Hold from
TCLK Falling

TSYNC Setup to TCLK Falling t
TSYNC Pulse Width t

t
t

t

CH

CL

SU

HD

SU
PW

TCLK Rise/Fall Times tR, t
Delay TCLK to TCHCLK t
Delay TCLK to TCHBLK t
Delay TCLK to TSYNC t
Delay TCLK to TLCLK t

D1
D2
D3
D4

P

75
75

25 ns 1

25 ns 1

25 tCH–5
50

F

10 60 ns
10 70 ns
10 60 ns
10 60 ns

648 ns

ns
ns

25 ns

NOTE:

1. If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and the parame­ters tSU and tHD still apply.

022697 44/46

DS2151Q

TRANSMIT SIDE AC TIMING

t

R

TCLK

3

TSER

TCHCLK

TCHBLK

1

TSYNC

2

TSYNC

TLCLK

TLINK

t

P

t

t

F

CL

t

CH

F–BIT

t

t

D1

t

D3

t

SU

t

D4

t

SU

HD

t

SU

t

D2

t

PW

t

HD

NOTES:

1. TSYNC is in the output mode (TCR2.2=1).

2. TSYNC is in the input mode (TCR2.2=0).

3. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.

022697 45/46

DS2151Q

DS2151Q T1 CONTROLLER 44–PIN PLCC

E

E1

B

N

1

.075 MAX

D1

D

NOTE 1

CH1

.150

MAX

e1

E2

NOTE1: PIN 1 IDENTIFIER TO BE LOCA TED IN ZONE INDICATED.

INCHES

DIM MIN MAX

A 0.165 0.180
A1 0.090 0.120
A2 0.020 –

B 0.026 0.033
B1 0.013 0.021

C 0.009 0.012

CH1 0.042 0.048

D 0.685 0.695
D1 0.650 0.656
D2 0.590 0.630

E 0.685 0.695
E1 0.650 0.656
E2 0.590 0.630
e1 0.050 BSC

N 44 –

D2

C

A1A2

B1

A

022697 46/46