Rainbow Electronics DS2143Q User Manual

DS2143/DS2143Q

E1 Controller

FEATURES

• E1/ISDN–PRI framing transceiver

• Frames to CAS, CCS, and CRC4 formats

• Parallel Control Port

• Onboard two frame elastic store slip buffer

• Extracts and inserts CAS signaling bits

• Programmable output clocks for fractional E1 links,

DS0 loopbacks, and Drop and Insert applications

• Onboard Sa data link support circuitry

• FEBE E–Bit Detection, Counting and Generation

• Pin compatible with DS2141A T1 Controller

• 5V supply; low power (50 mW) CMOS

• Available in 40–pin DIP and 44–pin PLCC (DS2143Q)

DESCRIPTION

The DS2143 is a comprehensive, software–driven E1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to handle many E1 lines. The DS2143 is very flexible and can be configured into numerous orientations via software. The software orientation of the device allows the user to modify their design to conform to future E1 specification changes. The controller contains a set of 69 eight–bit internal registers which the user can access. These internal registers are used to configure the device and obtain information from the E1 link. The device fully meets al l of the latest E1 specifications including CCITT G.704, G.706, and G.732.

PIN ASSIGNMENT

TCLK

TSER

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BTS

RD (DS)

TCHCLK

ALE(AS)

TPOS

4 5

TNEG

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

BTS

(DS)

17 18

(R/W)

RLINK

20 21

VSS

40–PIN DIP (600 MIL)

TNEG

TPOS

TCHCLK

7 8 9 10 11 12

44–PIN PLCC

13 14 15 16 17

1819 202122 2324

ALE(AS)

TSER

TCLK

VDD

123456 44 43 42 41 40

VSS

RLINK

WR(R/W)

40 39

38 37 36

35 34

33 32 31 30 29 28 27 26 25 24 23 22

TSYNC

TLINK

TLCLK

25 262728

RCLK

RLCLK

RCHCLK

VDD TSYNC TLINK TLCLK INT1 INT2 RLOS/LOTC TCHBLK

RCHBLK LI_CS LI_CLK LI_SDI SYSCLK RNEG

RPOS RSYNC

RSER RCHCLK RCLK RLCLK

INT1

INT2

RLOS/LOTC

TCHBLK

RCHBLK

LI_CS

LI_CLK

LI_SDI

SYSCLK

RNEG

RPOS

RSER

RSYNC

Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

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DS2143/DS2143Q

1.0 INTRODUCTION

The DS2143 E1 Controller has four main sections: the receive side, the transmit side, the line interface controller, and the parallel control port. See the Block Diagram. On the receive side, the device will clock in the serial E1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and multiframe patterns and establish their respective positions. This information will be used by the rest of the receive side circuitry.

The DS2143 is an “off–line” framer , which means that all of the E1 serial stream that goes into the device, will come out of it, unchanged. Once the E1 data has been framed to, the signaling data can be extracted. The two–frame elastic store can either be enabled or bypassed.

The transmit side clocks in the unframed E1 stream at TSER and adds in the framing pattern and the signaling. The line Interface control port will update line interface devices that contain a serial port. The parallel control port contains a multiplexed address and data structure which can be connected to either a microcontroller or microprocessor.

Reader’s Note:

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 eight–bit timeslots in an E1 systems which are number 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:

DS2143 FEATURES

• Parallel control port

• Onboard two–frame elastic store

• CAS signaling bit extraction and insertion

• Fully independent transmit and receive sections

• Full alarm detection

• Full access to Si and Sa bits

• Loss of transmit clock detection

• HDB3 coder/decoder

• Full transmit transparency

• Large error counters

• Individual bit–by–bit Sa data link support circuitry

• Programmable output clocks

• Frame sync generation

• Local loopback capability

• Automatic CRC4 E–bit support

• Loss of receive clock detection

• G.802 E1 to T1 mapping support

FAS Frame Alignment Signal CRC4 Cyclical Redundancy Check CAS Channel Associated Signaling CCS Common Channel Signaling MF Multiframe Sa Additional bits Si International bits E–bit CRC4 Error bits

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DS2143 BLOCK DIAGRAM

RPOS

RCLK

RNEG

LOCAL LOOPBACK

TPOS

TNEG

LI_SDI

LI_SCLK

LI_CS

LINE INTERFACE

CONTROL PORT

RLOS

RECEIVE SIDE

FRAMER

BPV COUNTER

HDB3 DECODER

SYNCHRONIZER

TRANSMIT SIDE FORMATTER

AIS GENERATION

E–BIT COUNT

ALARM DETECTION

CRC4 ERROR COUNT

SIGNALING EXTRACTION

HDB3 ENCODE

CRC4 GENERATION

IDLE CODE INSERTION

SIGNALING INSERTION

Sa BIT INSERTION

E–BIT INSERTION

Si BIT INSERTION

FAS WORD INSERTION

TIMING CONTROL/

Sa EXTRACTION

ELASTIC

STORE

TIMING

CONTROL

INTERT

LOGIC

DS2143/DS2143Q

RLINK RLCLK RCHBLK RCHCLK

RSER SYSCLK RSYNC

TCLK

TSER

TSYNC TCHCLK TCHBLK

TLINK TLCLK

PARALLEL CONTROL PORT (ROUTED TO ALL BLOCKS)

BTS CS WR(R/W)RD(DS) ALE(AS) AD0–AD7 INT1/INT2

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DS2143/DS2143Q

45TPOS

Transmit Bipolar Data. Updated on rising edge of TCLK.

2627RPOS

Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.

PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1 TCLK I Transmit Clock. 2.048 MHz primary clock. A clock must be applied at the

2 TSER I Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge

3 TCHCLK O T ransmit Channel Clock. 256 KHz clock which pulses high during the LSB

4 TPOS O Transmit Bipolar Data. Updated on rising edge of TCLK.

TNEG

6–13 AD0–AD7 I/O Address/Data Bus. A 8–bit multiplexed address/data bus.

14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to

15 RD(DS) I Read Input (Data Strobe). 16 CS I Chip Select. Must be low to read or write the port. 17 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to

18 WR(R/W) I Write Input (Read/Write). 19 RLINK O Receive Link Data. Outputs Sa bits. See Section 13 for timing details. 20 V

21 RLCLK O Receive Link Clock. 4 KHz to 20 KHz demand clock for the RLINK output.

22 RCLK I Receive Clock. 2.048 MHz primary clock. A clock must be applied at the

23 RCHCLK O Receive Channel Clock. 256 KHz clock which pulses high during the LSB

24 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges

25 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin

26 RPOS I Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.

RNEG

28 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic

29 LI_SDI O Serial Port Data for the Line Interface. Connects directly to the SDI input

TCLK pin for the parallel port to operate properly.

of TCLK.

of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details.

For optical links, can be programmed to output NRZ data.

select Intel bus timing. This pin controls the function of the RD ALE(AS), and WR

(R/W)pins. If BTS=1, then these pins assume the function

listed in parenthesis ().

demultiplex the bus.

– Signal Ground. 0.0 volts.

Controlled by RCR2. See Section 13 for timing details.

RCLK pin for the parallel port to operate properly.

of each channel. Useful for serial to parallel conversion of channel data. See Section 13 for timing details.

of RCLK.

which indentifies either frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If the elastic store is enabled via the RCR2.1, then this pin can be enabled to be an input via RCR1.5 at which a frame boundary pulse is applied. See Section 13 for timing details.

Tie together to receive NRZ data and disable BPV monitoring circuitry.

store function is enabled via the RCR2.1. Should be tied low in applications that do not use the elastic store.

pin on the line interface. See Sections 12 and 13 for timing details.

(DS),

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DS2143/DS2143Q

PIN DESCRIPTIONTYPESYMBOL

30 LI_CLK O Serial Port Clock for the Line Interface. Connects directly to the SCLK

input pin on the line interface. See Sections 12 and 13 for timing details.

31 LI_CS O Serial Port Chip Select for the Line Interface. Connects directly to the CS

input pin on the line interface. See Sections 12 and 13 for timing details.

32 33

RCHBLK TCHBLK

O Receive/Transmit Channel Block. A user programmable output that can

be forced high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1 or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications. See Sections 9 and 13 for details.

34 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.

If TCR2.0=0, then this pin will toggle high when the synchronizer is searching for the E1 frame and multiframe. If TCR2.0=1, then this pin will toggle high if the TCLK pin has not toggled for 5 µs.

35 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined

in Status Register 2. Active low, open drain output.

36 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions

defined in Status Register 1. Active low, open drain output.

37 TLCLK O Transmit Link Clock. 4 KHz to 20 KHz demand clock for the TLINK input.

Controlled by TCR2. See Section 13 for timing details.

38 TLINK I T ransmit Link Data. If enabled, this pin will be sampled on the falling edge

of TCLK to insert Sa bits. See Section 13 for timing details.

39 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or CAS multi-

frame boundaries for the DS2143. Via TCR1.1, the DS2143 can be programmed to output either a frame or multiframe pulse at this pin. See Section 13 for timing details.

40 VDD – Positive Supply. 5.0 volts.

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DS2143/DS2143Q

DS2143 REGISTER MAP

ADDRESS

A7 to A0

00000000 00 R Bipolar Violation Count

00000001 01 R Bipolar Violation Count

00000010 02 R CRC4 Count Register 1. 00000011 03 R CRC4 Count Register 2. 00000100 04 R E–Bit Count Register 1. 00000101 05 R E–Bit Count Register 2. 000001 10 06 R/W Status Register 1. 000001 11 07 R/W Status Register 2. 00001000 08 R/W Receive Information

0001 11 10 1E R Synchronizer Status

000101 10 16 R/W Interrupt Mask

000101 11 17 R/W Interrupt Mask

00010000 10 R/W Receive Control

00010001 11 R/W Receive Control

00010010 12 R/W Transmit Control

0001001 1 13 R/W Transmit Control

00010100 14 R/W Common Control

00010101 15 R/W Test Register. 0001 1000 18 W LI Control Register Byte

0001 1001 19 W LI Control Register Byte

00100000 20 R/W Transmit Align Frame

00100001 21 R/W Transmit Non–Align

00101 111 2F R Receive Align Frame

0001 1111 1F R Receive Non–Align

00100010 22 R/W Transmit Channel Block-

HEX R/W REGISTER NAME

Frame Register.

ing Register 1.

ADDRESS

HEX R/W REGISTER NAME

A7 to A0

00100011 23 R/W Transmit Channel Block-

ing Register 2.

00100100 24 R/W Transmit Channel Block-

ing Register 3.

00100101 25 R/W Transmit Channel Block-

ing Register 4. 001001 10 26 R/W Transmit Idle Register 1. 001001 11 27 R/W Transmit Idle Register 2. 00101000 28 R/W Transmit Idle Register 3. 00101001 29 R/W Transmit Idle Register 4. 00101010 2A R/W Transmit Idle Definition

ing Register 1. 00101 100 2C R/W Receive Channel Block-

ing Register 2. 00101 101 2D R/W Receive Channel Block-

ing Register 3. 00101 110 2E R/W Receive Channel Block-

ing Register 4. 00110000 30 R Receive Signaling

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DS2143/DS2143Q

ADDRESS

HEX R/W REGISTER NAME

A7 to A0

00111011 3B R Receive Signaling

00111100 3C R Receive Signaling

00111101 3D R Receive Signaling

00111110 3E R Receive Signaling

00111111 3F R Receive Signaling

01000000 40 R/W Transmit Signaling

01000001 41 R/W Transmit Signaling

01000010 42 R/W Transmit Signaling

0100001 1 43 R/W Transmit Signaling

01000100 44 R/W Transmit Signaling

01000101 45 R/W Transmit Signaling

010001 10 46 R/W Transmit Signaling

010001 11 47 R/W Transmit Signaling

01001000 48 R/W Transmit Signaling

01001001 49 R/W Transmit Signaling

01001010 4A R/W Transmit Signaling

0100101 1 4B R/W Transmit Signaling

01001 100 4C R/W Transmit Signaling

01001 101 4D R/W Transmit Signaling

01001 110 4E R/W Transmit Signaling

01001 111 4F R/W Transmit Signaling

2.0 PARALLEL PORT

The DS2143 is controlled via a mutliplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2143 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details. The mutliplexed bus on the DS2143 saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2143 latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or WR

pulses. In a read cycle, the DS2143 outputs a byte of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.

3.0 CONTROL AND TEST REGISTERS

The operation of the DS2143 is configured via a set of five registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2143 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and a Common Control Register (CCR). Each of the five registers are described in this section.

The T est Register at address 15 hex is used by the factory in testing the DS2143. On power–up, the T est Register should be set to 00 hex in order for the DS2143 to operate properly .

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DS2143/DS2143Q

RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)

(MSB) (LSB)

RSMF RSM RSIO – – FRC SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is pro-

RSM RCR1.6 RSYNC Mode Select.

RSIO RCR1.5 RSYNC I/O Select.

– RCR1.4 Not Assigned. Should be set to zero when written to. – RCR1.3 Not Assigned. Should be set to zero when written to.

FRC RCR1.2 Frame Resync Criteria.

SYNCE RCR1.1 Sync Enable.

RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated. Must be

grammed in the multiframe mode (RCR1.6=1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries

0 = frame mode (see the timing in Section 13) 1 = multiframe mode (see the timing in Section 13)

0 = RSYNC is an output (depends on RCR1.6) 1 = RSYNC is an input (only valid if elastic store enabled) (note: this bit must be set to zero when RCR2.1=0)

0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non–F AS is received in error 3 consecutive times

0 = auto resync enabled 1 = auto resync disabled

cleared and set again for a subsequent resync.

SYNC/RESYNC CRITERIA Table 2

FRAME OR

MULTIFRAME

LEVEL

FAS FAS present in frames N and N +

CRC4 Two valid MF alignment words

CAS Valid MF alignment word found

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SYNC CRITERIA RESYNC CRITERIA ITU SPEC.

2, and FAS not present in frame N + 1.

found within 8 ms.

and previous time slot 16 contains code other than all zeros.

Three consecutive incorrect FAS received.

Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non–FAS received.

915 or more CRC4 code words out of 1000 received in error.

Two consecutive MF alignment words received in error.

G.706

4.1.1

4.1.2

G.706

4.2

4.3.2 G.732

5.2

DS2143/DS2143Q

RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S SCLKM ESE –

SYMBOL POSITION NAME AND DESCRIPTION

Sa8S RCR2.7 Sa8 Bit Select. Set to one to report the Sa8 bit at the RLINK pin; set to zero

Sa7S RCR2.6 Sa7 Bit Select. Set to one to report the Sa7 bit at the RLINK pin; set to zero

Sa6S RCR2.5 Sa6 Bit Select. Set to one to report the Sa6 bit at the RLINK pin; set to zero

Sa5S RCR2.4 Sa5 Bit Select. Set to one to report the Sa5 bit at the RLINK pin; set to zero

Sa4S RCR2.3 Sa4 Bit Select. Set to one to report the Sa4 bit at the RLINK pin; set to zero

SCLKM RCR2.2 SYSCLK Mode Select.

ESE RCR2.1 Elastic Store Enable.

– RCR2.0 Not Assigned. Should be set to zero when written to.

to not report the Sa8 bit.

to not report the Sa7 bit.

to not report the Sa6 bit.

to not report the Sa5 bit.

to not report the Sa4 bit.

0 = if SYSCLK is 1.544 MHz 1 = if SYSCLK is 2.048 MHz

0 = elastic store is bypassed 1 = elastic store is enabled

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)

(MSB) (LSB)

ODF

SYMBOL POSITION NAME AND DESCRIPTION

ODF TCR1.7 Output Data Format.

TFPT TCR1.6 Transmit Timeslot 0 Pass Through.

T16S TCR1.5 Transmit Timeslot 16 Data Select.

TUA1 TCR1.4 Transmit Unframed All Ones.

TSiS TCR1.3 Transmit International Bit Select.

TFPT T16S TUA1 TSiS TSA1 TSM TSIO

0 = bipolar data at TPOS and TNEG 1 = NRZ data at TPOS; TNEG=0

0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

0 = sample timeslot 16 at TSER pin 1 = source timeslot 16 from TS1 to TS16 registers

0 = transmit data normally 1 = transmit an unframed all one’s code at TPOS and TNEG

0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0)

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DS2143/DS2143Q

TSA1 TCR1.2 Transmit Signaling All Ones.

0 = normal operation 1 = force timeslot 16 in every frame to all ones

TSM TCR1.1 TSYNC Mode Select.

0 = frame mode (see the timing in Section 13) 1 = CAS and CRC4 multiframe mode (see the timing in Section 13)

TSIO TCR1.0 TSYNC I/O Select.

0 = TSYNC is an input 1 = TSYNC is an output

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)

(MSB) (LSB)

Sa8S

SYMBOL POSITION NAME AND DESCRIPTION

Sa8S TCR2.7 Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set to

Sa7S TCR2.6 Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK pin; set to

Sa6S TCR2.5 Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK pin; set to

Sa5S TCR2.4 Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK pin; set to

Sa4S TCR2.3 Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK pin; set to

– TCR2.2 Not Assigned. Should be set to zero when written to.

AEBE TCR2.1 Automatic E–Bit Enable.

P34F TCR2.0 Function of Pin 34.

Sa7S Sa6S Sa5S Sa4S – AEBE P34F

zero to not source the Sa8 bit.

zero to not source the Sa7 bit.

zero to not source the Sa6 bit.

zero to not source the Sa5 bit.

zero to not source the Sa4 bit.

0 = E–bits not automatically set in the transmit direction 1 = E–bits automatically set in the transmit direction

0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC)

CCR: COMMON CONTROL REGISTER (Address=14 Hex)

(MSB) (LSB)

LLB

SYMBOL POSITION NAME AND DESCRIPTION

LLB CCR.7 Local Loopback.

THDB3 CCR.6 Transmit HDB3 Enable.

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THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4

0 = loopback disabled 1 = loopback enabled

0 = HDB3 disabled 1 = HDB3 enabled

DS2143/DS2143Q

TG802 CCR.5 T ransmit G.802 Enable. See Section 13 for details.

0 = do not force TCHBLK high during bit 1 of timeslot 26 1 = force TCHBLK high during bit 1 of timeslot 26

TCRC4 CCR.4 Transmit CRC4 Enable.

0 = CRC4 disabled 1 = CRC4 enabled

RSM CCR.3 Receive Signaling Mode Select.

0 = CAS signaling mode 1 = CCS signaling mode

RHDB3 CCR.2 Receive HDB3 Enable.

0 = HDB3 disabled 1 = HDB3 enabled

RG802 CCR.1 Receive G.802 Enable. See Section 13 for details.

0 = do not force RCHBLK high during bit 1 of timeslot 26 1 = force RCHBLK high during bit 1 of timeslot 26

RCRC4 CCR.0 Receive CRC4 Enable.

0 = CRC4 disabled 1 = CRC4 enabled

LOCAL LOOPBACK

When CCR.7 is set to a one, the DS2143 will enter a Local LoopBack (LLB) mode. This loopback is useful in testing and debugging applications. In LLB, the DS2143 will loop data from the transmit side back to the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK signal, and the RPOS/ RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following will occur;

The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS2143 which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with current value and it will be cleared. When a zero is written to a bit position,

1. data at RPOS and RNEG will be ignored

2. all receive side signals will take on timing synchronous with TCLK instead of RCLK

3. all functions are available.

4.0 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real time status of the DS2143, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. All of the bits in these registers operate in a latched fashion (except for the SSR). This means that if an event occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again or if the alarm(s) is still present.

the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND’ed with the mask byte that was just written and this value should be written back into the same register to insure that the bit does indeed clear. This second write is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2143 with higher order software languages.

The SSR register operates differently than the other three. It is a read only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this registers with a write.

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DS2143/DS2143Q

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1

and INT2 pins

respectively. Each of the alarms and events in the SR1

and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.

RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)

(MSB) (LSB)

–

– – ESF ESE – FASRC CASRC

SYMBOL POSITION NAME AND DESCRIPTION

– RIR.7 Not Assigned. Could be any value when read. – RIR.6 Not Assigned. Could be any value when read. – RIR.5 Not Assigned. Could be any value when read.

ESF RIR.4 Elastic Store Full. Set when the elastic store buffer fills and a frame is

deleted.

ESE RIR.3 Elastic Store Empty. Set when the elastic store buffer empties and a

frame is repeated.

– RIR.2 Not Assigned. Could be any value when read.

FASRC RIR.1 FAS Resync Criteria Met. Set when three consecutive FAS words are

received in error.

CASRC RIR.0 CAS Resync Criteria Met. Set when two consecutive CAS MF alignment

words are received in error.

SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)

(MSB) (LSB)

CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA

SYMBOL POSITION NAME AND DESCRIPTION

CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6–bit counter. CSC4 SSR.6 CRC4 Sync Counter Bit 4. CSC3 SSR.5 CRC4 Sync Counter Bit 3. CSC2 SSR.4 CRC4 Sync Counter Bit 2. CSC1 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB is not

accessible.

FASSA SSR.2 F AS Sync Active. Set while the synchronizer is searching for alignment at

the FAS level.

CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching for the CAS

MF alignment word.

CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching for the

CRC4 MF alignment word.

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