Rainbow Electronics DS2132A-Q User Manual
DS2132A/Q
DS2132A/Q
Digital Answering Machine Processor
FEATURES
• Two high quality speech compression algorithms per-
mit either 7 or 14 minutes of speech storage in a single
4 Mbit DRAM or ARAM
• Economical three-wire data/control/status port frees
up microcontroller port pins
• Detects and generates the 12 standard DTMF tones
plus the A/B/C/D tones
• Detects CCITT T.30 FAX calling tone (1100 Hz)
• Generates musical tones which allow “melodies-on-
hold” or customizable prompts
• Echo cancellation for improved DTMF receiver per-
formance
• Precise signal level detection capability
• Record/Playback gain control
• 28-pin DIP or PLCC (DS2132AQ) packages
There is a series of Application Notes
that accompany this data sheet.
DESCRIPTION
The DS2132A Digital Answering Machine Processor is
a Digital Signal Processor (DSP) optimized for the compression/expansion of PCM coded voice to/from an extremely low bit rate. The DS2132A contains two advanced speech compression algorithms that offer
outstanding fidelity . The Standard Record/Playback algorithm compresses speech to 9.8Kbps and the Extended Record/Playback algorithm compresses
speech to 4.9Kbps.
The DS2132A is ideal for embedded applications such
as digital answering machines, voice mail, voice annunciators, and any other device that needs to maximize
speech storage in a limited memory space. A simple
PIN ASSIGNMENT
600 MIL
RSTNCVCC
GND
1
GND
MCLK
PLCC
PD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
272826
CDIN
VCC
PCMIN
CLK
FS
PCMOUT
TRI_IN
GND
GND
CDOUT
TRI_OUT
FS
CLK
CDIN
PCMINCLK
CLK
25
24
23
22
21
20
19
FS
FS
PCMOUT
TRI_IN
GND
GND
CDOUT
TRI_OUT
PD
1
RST
2
GND
3
GND
4
PD
5
6
VCC
7
VCC
8
VCC
9
VCC
10
VCC
11
VCC
12
GND
13
MCLK
14
GND NC
DS2132A 28-PIN DIP
GND
PD
432
5
6
VCC
7
VCC
8
VCC
9
VCC
VCC
10
VCC
11
12 1314 15 16 1718
GND
DS2132AQ 28-PIN
three wire interface to the embedded microcontroller
frees up valuable controller port pins for other uses and
simplifies the software needed to transfer speech data,
issue commands, and receive DTMF/energy level/status information. The DS2132A detects and generates
all 16 DTMF tones and can also generate a wide variety
of call progress tones. In addition, the DS2132A provides CCITT Rec. T .30 FAX calling tone detection which
enables the answering machine to determine if the incoming call is a voice or FAX transmission. The energy
level detector allows the microcontroller to perform call
progress detection and automatic gain control functions.
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041295 1/17
DS2132A/Q
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
3,4,12,14,21,22 GND - Ground. Tie to system ground.
6,7,8,9,10,11,28 VCC - Positive Supply. Tie to system +5 volt supply.
1 PD O Power-Down Active Low. Will toggle low during Power-
5 PD O Power-Down Active High. Will toggle high during Power-
15 NC - No Connect. Do not connect any signal to this pin.
2 RST I Reset. When this pin is low, the internal DSP algorithm is
13 MCLK I Master Processing Clock. The clock used for the internal
16 CDIN I Compressed Data Port Input. Serial input for com-
17,26 CLK I Clock. This clock is used to sample data at CDIN and
18,25 FS I Frame Sync. This input must be an 8 KHz clock with a
19 TRI_OUT O CDOUT Tri-state Control Out. This output should be tied
20 CDOUT O Compressed Data Port Output. Serial output for com-
23 TRI_IN I CDOUT Tri-state Control In. This input should be tied to
24 PCMOUT O PCM Port Output. Output for expanded data which is in
27 PCMIN I PCM Port Input. Input for the 8-bit serial µ-law PCM data
Down mode.
Down mode.
in a reset state. On power-up, this pin should be held low
for at least 100 ms after MCLK is stable.
DSP engine. Should be in the range of 12 to 16 MHz.
MCLK can be asynchronous to any other clock signal on
the DS2132A. The duty cycle should be 50% (±5%).
pressed audio data or DS2132A commands. Samples on
the falling edges of CLK. The compressed data is expanded to 8-bit PCM which is output on PCMOUT.
PCMIN and output data at CDOUT and PCMOUT. CLK
must be synchronous with FS. See Figure 3.
pulse width high time of one to nine CLK cycles for proper
operation. See Figure 3.
to the TRI_IN pin (pin 23) for proper operation; will be low
when CDOUT is active.
pressed audio data or status information, updated on the
rising edge of CLK.
the TRI_OUT pin (pin 19) for proper operation. If this pin is
forced high, CDOUT will not go active.
the standard 8-bit µ-law format. Data is updated on the
rising edges of CLK.
which would normally be supplied by a codec/filter device.
Data is sampled on the falling edges of CLK.
FUNCTIONAL DESCRIPTION
A typical digital answering machine using the DS2132A
is shown in Figure 1. The system consists of a standard
telephone CODEC (COder-DECoder) device, the
DS2132A, a microcontroller , and a bank of DRAM. The
implementation shown is with a Hitachi CODEC and a
8051-type microcontroller but a wide variety of
041295 2/17
CODECs and microcontrollers can be used with the
DS2132A. It is only important that the CODEC have serial digital I/O and have µ-law (“Mu” law) companding.
Table 2 lists some CODECs that will work with the
DS2132A. There is a separate Application Note that explains how to connect these CODECs to the DS2132A.
TYPICAL DIGITAL ANSWERING SYSTEM Figure 1
CODEC/FILTER
To 2- to 4–wire
converter and phone line
interface
GA1
GA2
AIN
AOUT
DGND
AGND
PD
Note:
HD44238P is a Hitachi CODEC
12 MHz to 16 MHz
VSS
VDD
PCMOUT
PCMIN
TXCLK
RXCLK
TXSYNC
RXSYNC
-5V
+5V
TXD
8051-Type
Microcontroller
P1.1
+5V
P1.0
+5V
RXD
DS2132A
PCMIN
PCMOUT
CLK
CLK
FS
FS
CDOUT
CDIN
PD
MCLK
RST
TRI_OUT
TRI_IN
VCC
GND
DRAM Array
DS2132A/Q
POR
+5V
RECOMMENDED DS2132A CODECS Table 2
Vendor Model(s)
Texas Instruments TCM29CXX
National Semiconductor TP3054X
Motorola MC1455XX
SGS–Thomson ETC505X
Hitachi HD44238C
As shown in Figure 1, the microcontroller creates the
clock (CLK) and frame sync (FS) that is sent to both the
CODEC and the DS2132A. In this manner, the
DS2132A shares the signals necessary to drive the CODEC. T o “record” an audio signal, the following occurs.
The analog signal applied at the AIN pin of the CODEC
is converted to eight bit values and output at PCMOUT
every 125 µs. The DS2132A takes these eight bit samples in at the PCMIN pin and effectively compresses
them to either 9.8Kbps or 4.9Kbps. See Figure 2. The
compressed data is then passed to the microcontroller
via the CDOUT pin (CD stands for Compressed Data).
The microcontroller then stores the compressed
speech in the DRAM array. The inverse of this process
is required to “playback” the message at the AOUT pin
of the CODEC.
041295 3/17
DS2132A/Q
DS2132A BLOCK DIAGRAM Figure 2
PCMIN
PCMOUT
To CODEC
“PCM” Side
Record
Gain Control
Playback
Gain Control
Loopback
DTMF/Level/
FAX Tone
Detection
Threshold
Speech
Compression
Command
Processor
Speech
Expansion
DTMF/Musical
Tone
Generation
CDOUT
T o Microcontroller
“Compressed Data” Side
CDIN
OPERATION OF THE CD AND PCM PORTS
As mentioned earlier, the DS2132A essentially contains
two separate serial ports, one for the DS2132A to microcontroller interface (the CD Port ) and one for the CODEC to DS2132A interface (the PCM Port). The Compressed Data (CD) Port is used to send compressed
speech information from the DS2132A to the microcontroller and vice versa. The CD Port is also used to monitor the current status of the DS2132A and it is used to
issue instructions to the DS2132A. The CD Port consists of the CDIN, CDOUT , CLK, and FS pins (the CLK
041295 4/17
and FS pins are shared with the CODEC). The PCM
Port is used to transfer uncompressed speech data between the DS2132A and the CODEC. It consists of the
PCMIN, PCMOUT, CLK, and FS pins. Figure 3 details
the DS2132A CD and PCM port signals. All communication begins with the frame sync (FS) signal. It indicates to the DS2132A and the CODEC that a byte of information will follow. Note that the PCM Port operates
on a MSB first basis and the CD Port operates on a LSB
first basis.
CD & PCM PORT I/O DIAGRAM Figure 3
1
CLK
2
FS
PCMIN
PCMOUT
CDIN
CDOUT
MSB LSB
MSB LSB
LSB MSB
LSB MSB
NOTES:
1. The CLK period must be between 128 KHz and 4.096 MHz
2. The FS pulse must be between 1 and 9 (inclusive) CLK periods long
DS2132A/Q
3-STATE
3-STATE
On the PCM Port, data will be transferred from the CODEC to the DS2132A via one path and transferred from
the DS2132A to the CODEC via another path. These
transfers take place every 125 µs (as determined by the
FS signal). Although the CD Port also transfers data every 125 µs, it operates much differently than does the
PCM Port. The CD Port constantly toggles back and
forth in its data transfer direction. During one frame
sync, the microcontroller will transfer either compressed speech data or command information to the
DS2132A and during the next frame sync, the transfer
direction will switch and the DS2132A will send either
compressed speech data or status information to the
microcontroller. Hence, the CD Port is truly bidirectional. See Figure 4.
041295 5/17
DS2132A/Q
CD PORT FLOW STRUCTURE Figure 4
Tone Generation or Idle Recording Mode Playback Mode
CD Port CD Port CD Port
cmd.
status*
cmd.
data
cmd.
status
cmd.
status*
cmd.
data
cmd.
status
DS2132
Microcontroller
DS2132
cmd.
status
cmd.
status
cmd.
status
cmd.
status
cmd.
status
cmd.
status
DS2132
Microcontroller
NOTE: Status Bytes marked with an asterisk (*) indicate bytes with the MSB set to 1.
CD PORT I/O STRUCTURE Figure 5
cmd.
status*
data
status
cmd.
status
cmd.
status
cmd.
status*
data
status
Microcontroller
Tone Generation or Idle
FS
CDIN
CDOUT
Record Mode
FS
CDIN
CDOUT
command
Playback Mode
FS
CDIN
CDOUT
command
command
command command
status status status
command
status*
command data
status status* status
data
command
status
041295 6/17
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