Rainbow Electronics DS2130Q User Manual

DS2130Q

Voice Messaging Processor

FEATURES

• Per-channel voice messaging processor for digitized

voice storage and retrieval

• High fidelity speech recording and playback at 8, 12,

16, 24 and 32 Kbits/sec

• Integral DTMF transceiver for remote touch-tone con-

trol and dialing

• Connects to popular PCM codec/filters for analog in-

terfacing

• Direct PCM serial data bus interfaces to any of 32 pos-

sible TDM time slots

• Monitors and reports audio energy levels for call prog-

ress and voice detection

• Selectable beep generator for sound prompts

• 3-wire synchronous serial control port

• 28-pin DIP or PLCC (DS2130Q) packages

DESCRIPTION

The DS2130 Voice Messaging Processor is a CMOS DSP processor that serves as a voice messaging engine for digitized voice storage and retrieval applications. It offers half-duplex speech compression or expansion at either 8, 12, 16, 24 or 32 Kbits/sec. The advanced speech compression algorithm maintains excellent audio clarity even at low bit rates. The algorithm also incorporates a DTMF transceiver for decoding or generating touch-tone signals for remote control and automatic dialing. The tone generator can be used to create single-tone beeps used in popular answering machines. Voice and call progress detection can be easily implemented using the energy threshold detect outputs.

PIN ASSIGNMENT

DT1

RST

TM0

TM1

DT0

6 7

A1 A2

SPS

MCLK

GND

TM1

432

DT0

A1 A2

8 9

A3 A4

10 11

12 1314 15 16 1718

MCLK

SPS

The DS2130 can be used together with a low-cost codec/filter device for analog interfacing in standalone applications such as answering machines or feature phones. It can also interface directly to a serial PCM bus on any of up to 32 possible time slots using an internal software-selectable time slot assigner circuit (TSAC). This configuration can be used in digital switching systems for adding voice messaging services to existing backplane designs.

Applications include digital answering machines, embedded voice response, speech annunciators, voice mail, key telephone systems and automatic operator services.

TM0

GND

RST

DT3

DT1

CPXIN

28 27 26 25

24 23 22 21

20 19 18

17 16

VCC

PCMIN

27 2628

CPXCLK

Vcc PCMIN PCMCLK PCMFS PCMOUT

SDI SCLK CPXOUT DT2 CPXFS CPXCLK CPXIN

DT3

PCMCLK

25 24 23 22

21 20

CPXFS

PCMFS PCMOUT CS

SDI SCLK CPXOUT DT2

Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

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PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1 19 15

2 RST I Reset input. When this pin is low, the internal DSP algorithm is in a reset state

9 10 11

12 SPS I Serial Port Select. This pin must be tied to VCC for proper operation of the serial

13 MCLK I Master processing clock. This is the clock used for the internal DSP engine and

14 GND - Ground. Tie this pin to the system logic ground. 16 CPXIN I Compressed data in. This is the serial data input for the compressed audio data

17 CPXCLK I Compression/expansion side data clock. This is the clock used to sample data

18 CPXFS I Compression/expansion side frame sync. This input must be an 8 KHz clock

20 CPXOUT O Compressed data out. This is the serial data output for the compressed audio

21 SCLK I Serial port clock. This is the clock used to write configuration data to the serial

22 SDI I Serial data input. Data source for the serial port registers. 23 CS I Chip select input. This pin must transition high to low before each write operation

24 PCMOUT O PCM output. This is the output for expanded data which is in the standard 8-bit

DT0 DT1 DT2 DT3

TM0 TM1

A0 A1 A2 A3 A4 A5

Detect outputs 0-3. These are the four output detect lines that report energy

threshold levels and DTMF tones. DTMF tone detection always has precedence

over energy level reporting.

for proper initialization. The DS2130 should always be reset for at least 1 ms after each power-up occurrence.

IITest mode pins. These pins are used for factory testing and must be tied to GND

for proper operation.

Address Select. Provides serial address ID of the DS2130. The states of A0-A5

must match the address sent in the command byte to enable the serial port. A0

= LSB.

I I I

port. The hardware mode is not

supported on the DS2130.

should be in the range of 10.5 - 13 MHz. MCLK can be asynchronous to any other clock signal on the DS2130. The duty cycle should be nominally 50%.

sampled on falling edges of CPXCLK during selected time slots. This data is expanded to 8-bit PCM that is output on PCMOUT except in PCM bypass mode.

at CPXIN, to output data at CPXOUT and to determine the proper time slot. CPXCLK must be synchronous with CPXFS. See “Special Clock Requirements” section for more details.

for proper operation. CPXFS must be the same frequency as PCMFS (normally they are tied together).

data, updated on rising edges of CPXCLK during selected time slots.

port registers.

to the serial port.

PCM u/A-law format. Data is updated on rising edges of PCMCLK.

DS2130Q

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DS2130Q

PIN DESCRIPTIONTYPESYMBOL

25 PCMFS I PCM side frame sync. An 8 KHz clock signal must be applied for the PCM data

interface. Lower sample rates can be used to reduce the effective bit rate but may result in unusable DTMF detection and generation as well as lower voice quality. PCMFS is normally tied to CPXFS.

26 PCMCLK I PCM side data clock. This is the clock used to sample PCM serial data at

PCMIN, to output data at PCMOUT and to determine the proper time slot. PCMCLK must be synchronous with PCMFS.

27 PCMIN I PCM data input. This is the input for the 8-bit serial PCM data which would nor-

mally be supplied by a codec/filter device. Data is sampled on falling edges of PCMCLK.

28 V

- Positive supply input. Tie to system +5 volt supply.

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DS2130 SIGNAL FLOW DIAGRAM Figure 1

DS2130Q

ENERGY

DETECTOR

FILTER

DTMF LOW-BAND

DT0-DT3

MUX

DTMF

DECODER

Valid digit detect

FILTER

DTMF HIGH-BAND

CPXOUT

CPXCLK

COMPRESSION/

AUDIO

(Record)

COMPRESSION

CPXFS

DATA

EXPANSION

INTERFACE

CPXIN

AUDIO

EXPANSION

(Playback)

SPS

SDI

SCLKCSRST

SERIAL PORT

COMP/EXP SELECT

A0-A5

AND

TIMING

CONTROL

INTERFACE

TONE CONTROL

MULTI-TONE

GENERATOR

MCLK

INTERNAL DSP

PROCESSING CLOCK

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PCMIN

PCM

DATA

INTERFACE

PCMCLK

PCMFS

PCMOUT

DS2130Q

HARDWARE RESET

RST allows the host to reset the DSP algorithms and the contents of the serial port control registers. This pin must be held low for at least 1 ms on system power-up after MCLK is stable to ensure that the device has initialized properly. RST

clears all bits of both control registers except the CPD1 and CPD2 bits, which are set to one. However, these bits are ignored until they have been reset by the host; that is, the DS2130 will not power up in the power-down mode. This permits the host to communicate through the serial port at full speed after power-up.

SERIAL PORT CONTROL

An external host controller writes configuration data to the DS2130 via the serial port through inputs SCLK, SDI, and CS as shown in Figure 2 (read operations are not supported). Each write to the DS2130 is either a 2-byte write or a 4-byte write. A 2-byte write consists of the Address/Command Byte (ACB) followed by a byte to configure either the Voice Control Register (VCR) or

SERIAL PORT WRITE Figure 2

the T one Control Register (TCR). The 4-byte write consists of the ACB followed by a byte to configure the appropriate control register and then two bytes for input and output time slot mapping. When writing to the VCR, the next two bytes program the input and output time slots respectively for the compression/expansion (CPX) side interface. When writing to the TCR , the next two bytes program the input and output time slots respectively for the PCM side interface.

ADDRESS/COMMAND BYTE

The address/command byte is the first byte written to the serial port; it identifies which of the 64 possible DS2130’s sharing the serial bus is to be accessed. Address data must match that at inputs A0 to A5. If no match occurs, the DS2130 ignores the following data at SDI. If an address match occurs, the next three bytes written are accepted as control, input and output time slot data. Bit ACB.6 determines whether the Voice or Tone Control register is to be updated.

SCLK

SDI

A0 A1 A2 A3 A4

NOTE:

A 2-byte write is shown.

A5 0

ADDRESS/COMMAND CONTROL

CR7CR0V/T

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ADDRESS/COMMAND BYTE Figure 3

(MSB) (LSB)

DS2130Q

V/T A5 A4 A3 A2 A1 A0

SYMBOL POSITION NAME AND DESCRIPTION

- ACB.7 Reserved; must be zero for proper operation.

V/T ACB.6 Voice/Tone command byte select.

0 = write to Tone Generator Control register

1 = write to Voice Control register A5 ACB.5 MSB of Device Address. A4 ACB.4 A3 ACB.3 A2 ACB.2 A1 ACB.1 A0 ACB.0 LSB of Device Address.

VOICE CONTROL REGISTER

The Voice Control Register (VCR) determines the compression/expansion bit rate and PCM data format. It also provides power-down and algorithm reset control.

The u/A bit selects either µ-law or A-law PCM data encoding for PCMIN and PCMOUT pins. When u/A = 1, µ-Law is selected; when u/A = 0, A-Law is selected.

Compression or expansion bit rates are determined by bits CXS1, CXS2 and CXS3. See T able 2 for the mapping of these bits. For the reduced bandwidth modes, the incoming PCM data is internally filtered with a 1.7 KHz low-pass and sampled at one-half of the CPXFS/ PCMFS frequency. The PCM Bypass mode (CXS1=1, CXS2=0 and CXS3=1) permits input PCM data at either PCMIN or CPXIN to be routed out to CPXOUT or PCMOUT respectively, bypassing normal compression/expansion.

Voice compression/expansion can be disabled by setting CPD1 to a 1. In this mode, the compression/expansion algorithm is idled and CPXOUT is tri-stated. This

mode should be used when only DTMF/tone generation and detection are desired. When CPD1 and CPD2 (CPD2 is in the Tone Control register) are both equal to a 1, the device enters a low-power standby mode in which all DSP operation is halted.

must not be operated faster than 39 KHz.

CPXRST resets the algorithm coefficients for the expansion/compression algorithm to their initial values. CPXRST will be cleared by the device when the algorithm reset is complete.

The compression/expansion loopback feature is enabled when CXLB is set and CPD1 is cleared. During this loopback, no expansion or compression occurs and input data at CPXIN is looped back to the appropriate time slot at CPXOUT.

Compression or expansion operation is selected via the CP/EX bit (the DS2130 cannot perform both simultaneously).

In this mode, the serial port

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DS2130Q

VOICE CONTROL REGISTER Figure 4

(MSB) (LSB)

CP/EX

CXS1 CPD1 CXRST CXLB U/A CXS2 CXS3

SYMBOL POSITION NAME AND DESCRIPTION

CP/EX VCR.7 Compression/expansion select.

1 = compress (record) 0 = expand (playback)

CXS1 VCR.6 Compression/expansion bit rate select 1; see Table 2.

CPD1 VCR.5 Compression/Expansion power-down 1.

0 = Compression/expansion enabled 1 = Compression/expansion disabled

CXRST VCR.4 Compression/expansion algorithm reset.

0 = normal operation 1 = reset algorithm to initial coefficients

CXLB VCR.3 Compression/expansion interface loopback.

0 = normal operation 1 = bypass selected channel

U/A VCR.2 PCM input/output data format.

0 = A-Law

1 = µ-Law CXS2 VCR.1 Compression/Expansion bit rate select 2; see Table 2. CXS3 VCR.0 Compression/Expansion bit rate select 3.

COMPRESSION/EXPANSION BIT RATE SELECT Table 2

ALGORITHM SELECTED CXS1 CXS2 CXS3

64Kbps to/from 32Kbps 0 0 0 64Kbps to/from 24Kbps 1 1 0 64Kbps to/from 16Kbps 0 1 0 Reserved for future operation 1 0 0 64Kbps to/from 16Kbps 64Kbps to/from 12Kbps 64Kbps to/from 8Kbps 64Kbps to/from 64Kbps

(PCM Bypass mode)

1 1

0 0 1 1 1 1 0 1 1 1 0 1

NOTE:

1. These reduced bandwidth modes use an internal low-pass filter at 1.7 KHz to permit a lower bit rate. The normal bandwidth otherwise is 300 Hz to 3.4 KHz due to the filters typically present in the codec/filter device used with the DS2130.

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